CN112187264B - Broadband clock calibration method of ultra-high-speed time domain interleaved analog-to-digital converter - Google Patents
Broadband clock calibration method of ultra-high-speed time domain interleaved analog-to-digital converter Download PDFInfo
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Abstract
The invention discloses a broadband clock calibration method of an ultra-high-speed time domain interleaved analog-to-digital converter, which comprises the following steps: acquiring a clock jitter range of each channel; based on the obtained clock jitter range, performing at least one round of clock detection on each channel to obtain at least one group of clock jitter values; in each round of clock detection, aiming at each channel, based on a clock jitter range, taking two adjacent channels as reference channels, and searching a clock jitter value corresponding to the minimum clock jitter error by utilizing a bisection method; determining a clock jitter value to be calibrated based on at least one group of clock jitter values; compensating the quantization code according to the clock jitter value to be calibrated; wherein, the detection sequence of the channels in each round of clock detection is different; the clock jitter error for each channel is: the difference between the autocorrelation function values of each of two adjacent ones of the channels and the channel. The invention can further improve the clock calibration precision of the ultra-high speed analog-to-digital converter and reduce the calibration error.
Description
Technical Field
The invention belongs to the technical field of analog-digital hybrid integrated circuits, and particularly relates to a broadband clock calibration method of an ultra-high-speed time domain interleaved analog-digital converter.
Background
In the ultra-high-speed analog-to-digital converter, a time domain interleaving structure can enable N single-channel analog-to-digital converters with low quantization speed and high precision to alternately sample and quantize in parallel, so that the speed of the whole analog-to-digital converter is improved by N times; moreover, the time domain interleaving structure can relax the compromise requirement between power consumption and speed in the design of a single-channel analog-to-digital converter; therefore, the time domain interleaving structure is widely used in ultra-high speed analog-to-digital converters. Due to the variation of factors such as production process, power supply voltage, temperature and the like, many non-ideal factors exist among single-channel analog-to-digital converters, including offset mismatch, gain mismatch, clock jitter, bandwidth mismatch and the like, and the overall performance of the ultra-high-speed analog-to-digital converter is seriously affected. Therefore, in order to reduce the influence of non-ideal factors on the performance of the ultra-high speed analog-to-digital converter, it is necessary to clock the ultra-high speed analog-to-digital converter.
In the related art, some clock calibration methods use an additional auxiliary channel as a reference channel for clock calibration to calibrate the clock of the ultra-high speed analog-to-digital converter, and some clock calibration methods artificially set one of the channels in the interleaving structure as the reference channel to calibrate the clock of the ultra-high speed analog-to-digital converter. However, the use of an additional reference channel not only causes additional power consumption, but also is excessively dependent on the reference channel, which is prone to calibration errors; and a certain channel in the interleaving structure is used as a reference channel, so that the calibration error is easy to generate. Therefore, how to further improve the clock calibration accuracy of the ultra-high speed analog-to-digital converter and reduce the calibration error is a technical problem to be solved urgently.
Disclosure of Invention
In order to further improve the clock calibration precision of the ultra-high-speed analog-to-digital converter and reduce the calibration error, the invention provides a broadband clock calibration method of the ultra-high-speed time domain interleaved analog-to-digital converter.
The technical problem to be solved by the invention is realized by the following technical scheme:
a broadband clock calibration method of a super-high-speed time domain interleaving analog-to-digital converter comprises the following steps:
acquiring a clock jitter range of each channel of the ultra-high-speed time domain interleaved analog-to-digital converter;
performing at least one round of clock detection on each channel based on the acquired clock jitter range to obtain at least one group of clock jitter values; in each round of clock detection, aiming at each channel, based on the clock jitter range of the channel, taking two adjacent channels of the channel as reference channels, searching a clock jitter value corresponding to the minimum clock jitter error of the channel by utilizing a dichotomy, and obtaining the clock jitter value of the channel after detection;
determining a clock jitter value to be calibrated of each channel based on the at least one group of clock jitter values;
compensating the quantization codes of each channel according to the clock jitter value to be calibrated of each channel;
the detection sequence of the channels in each round of clock detection is different; the clock jitter error for each channel is: the difference between the autocorrelation function values of two adjacent channels of the channel.
Optionally, the clock detection comprises two rounds;
the odd channels are preferentially detected in one round of clock detection, the even channels are detected in the next round of clock detection, the even channels are preferentially detected in the other round of clock detection, and the odd channels are detected in the next round of clock detection.
Optionally, the clock detection comprises one round;
in the round of clock detection, an odd channel or an even channel is detected preferentially, and the rest channels are detected later.
Optionally, each round of the clock detection process includes:
aiming at each channel which is preferentially detected, based on the clock jitter range of the channel, two adjacent channels of the channel are taken as reference channels, and a clock jitter value corresponding to the minimum clock jitter error of the channel is searched by utilizing a bisection method to obtain the clock jitter value detected by the channel and the temporarily calibrated quantization code;
and aiming at each non-priority detection channel, based on the clock jitter range of the channel, searching a clock jitter value corresponding to the minimum clock jitter error of the channel by using a dichotomy by taking two temporarily calibrated adjacent channels of the channel as reference channels, and obtaining the clock jitter value detected by the channel.
Optionally, the step of searching, for each channel to be preferentially detected, a clock jitter value corresponding to a minimum clock jitter error of the channel by using a bisection method with two adjacent channels of the channel as a reference channel based on a clock jitter range of the channel to obtain a clock jitter value detected by the channel and a temporarily calibrated quantization code includes:
aiming at each channel which is preferentially detected, searching a clock jitter value by taking a clock jitter range of the channel as a dichotomous searching range until the searched clock jitter value meets a first searching cut-off condition; the first search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using a Taylor series expansion formula about the compensation quantization code, the clock jitter error of the channel calculated according to the compensation quantization code and the quantization codes of two adjacent channels of the channel is minimum;
and taking the clock jitter value searched when the search is ended as the clock jitter value detected by the channel, and taking the compensation quantization code calculated according to the clock jitter value as the quantization code temporarily calibrated by the channel.
Optionally, the obtaining, for each non-priority channel, a clock jitter value corresponding to a minimum clock jitter error of the channel by searching, using two temporally calibrated adjacent channels of the channel as reference channels and using a bisection method, based on the clock jitter range of the channel, a clock jitter value of the channel after detection is obtained includes:
aiming at each channel which is not detected preferentially, searching the clock jitter value by taking the clock jitter range of the channel as a dichotomy searching range until the searched clock jitter value meets a second searching cutoff condition; the second search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using the Taylor series expansion formula, the clock jitter error of the channel calculated according to the compensation quantization code and the quantization codes temporarily calibrated by two adjacent channels of the channel is minimum;
and taking the clock jitter value searched when the search is cut off as the clock jitter value of the channel detection completion.
Optionally, the determining, based on the at least one group of clock jitter values, a clock jitter value to be calibrated for each channel includes:
substituting two groups of clock jitter values obtained by two rounds of clock detection into a first preset unary quadratic function; the first preset unary quadratic function is a function of the proportion of each group of clock jitter values in a group of optimal clock jitter values;
calculating the proportion of each group of clock jitter values in the group of optimal clock jitter values corresponding to the minimum value of the first preset unitary quadratic function;
calculating the clock jitter value to be calibrated of each channel according to the calculated specific gravity and the two groups of clock jitter values;
the first predetermined unary quadratic function is:
wherein, t 1_i Representing the clock jitter value of the ith channel in a group of clock jitter values obtained by one round of clock detection, and u represents the proportion of the group of clock jitter values in the group of optimal clock jitter values; t is t 2_i Representing the clock jitter value of the ith channel in a group of clock jitter values obtained by another round of clock detection, wherein 1-u represents the proportion of the group of clock jitter values in the group of optimal clock jitter values; n represents the total number of channels of the ultra-high speed time-domain interleaved analog-to-digital converter.
Optionally, the calculating a clock jitter value to be calibrated for each channel according to the obtained specific gravity and the two sets of clock jitter values includes:
and for each channel, multiplying the two clock jitter values belonging to the channel by the specific gravity corresponding to the respective group and then summing the two clock jitter values to obtain the clock jitter value to be calibrated of the channel.
Optionally, the determining, based on the at least one group of clock jitter values, a clock jitter value to be calibrated for each channel includes:
substituting a group of clock jitter values obtained by any round of clock detection into a second preset unary quadratic function; the second predetermined unitary quadratic function is a function of a clock baseline for the set of clock jitter values;
calculating a clock baseline corresponding to the minimum value of the second preset unary quadratic function;
calculating the clock jitter value to be calibrated of each channel according to the obtained clock baseline and the group of clock jitter values;
the second predetermined unary quadratic function is:
wherein, t i A clock jitter value, t, representing the ith channel in the set of clock jitter values ref Representing the clock baseline.
Optionally, the calculating a clock jitter value to be calibrated for each channel according to the obtained clock baseline and the set of clock jitter values includes:
and subtracting the obtained clock base line from the clock jitter value of each channel in the group of clock jitter values to obtain the clock jitter value to be calibrated of each channel.
In the broadband clock calibration method of the ultra-high-speed time domain interleaved analog-to-digital converter, clock detection is carried out based on the clock jitter range of each channel of the ultra-high-speed time domain interleaved analog-to-digital converter, and in each round of clock detection, two adjacent channels of each channel are used as reference channels to carry out clock detection on the channel; therefore, an additional auxiliary channel is not needed to be used as a reference channel for clock detection, and a certain channel in a time domain interleaving structure is not needed to be set as the reference channel manually, so that the calibration error caused by excessive dependence on a single reference channel is avoided, the clock calibration precision of the ultra-high-speed analog-to-digital converter can be improved, and the calibration error is reduced; in addition, in the clock detection process, the dichotomy is adopted to improve the detection precision, further improve the clock calibration precision of the ultra-high speed analog-to-digital converter, and improve the calibration speed by adopting the dichotomy.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic flowchart of a method for calibrating a wideband clock of an ultra-high-speed time-domain interleaved analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a diagram schematically illustrating the adjacency between channels of an ultra-high speed time-domain interleaved analog-to-digital converter;
FIG. 3 is a schematic diagram illustrating exemplary wideband clock calibration for an ultra-high speed time-domain interleaved analog-to-digital converter with two clock detection rounds;
fig. 4 is a schematic diagram illustrating a wideband clock calibration of an ultra-high speed time-domain interleaved analog-to-digital converter through one round of clock detection.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
In order to further improve the clock calibration precision of the ultra-high-speed analog-to-digital converter and reduce the calibration error, the embodiment of the invention provides a broadband clock calibration method of the ultra-high-speed time-domain interleaved analog-to-digital converter. As illustrated in fig. 1, the method may include the steps of:
s10: and acquiring the clock jitter range of each channel of the ultra-high-speed time domain interleaved analog-to-digital converter.
In this step, the clock jitter range of each channel can be obtained in advance through simulation. And the clock jitter range of each channel covers the clock jitter value corresponding to the minimum clock jitter error of the channel. Here, the clock jitter error for each channel is: the difference between the autocorrelation function values of two adjacent channels of the channel. In practical applications, the autocorrelation function value of each channel and its neighboring channels can be obtained by calculating the degree of autocorrelation between the quantization code of the channel and the quantization code of its neighboring channels, and specifically, the expectation of the product of the quantization code of the channel and the quantization code of its neighboring channels can be calculated as the autocorrelation function value.
For the 1 st channel of the ultra-high-speed time domain interleaved analog-to-digital converter, the two adjacent channels are the last channel n and the 2 nd channel; and for the last channel n, the two adjacent channels are the (n-1) th channel and the 1 st channel. For example, fig. 2 shows graphically the adjacency relationship between channels, taking a 4-channel ultra-high-speed time-domain interleaved analog-to-digital converter as an example.
S20: based on the obtained clock jitter range, performing at least one round of clock detection on each channel to obtain at least one group of clock jitter values; in each round of clock detection, aiming at each channel, based on the clock jitter range of the channel, two adjacent channels of the channel are used as reference channels, and a clock jitter value corresponding to the minimum clock jitter error of the channel is searched by utilizing a dichotomy, so that the clock jitter value detected by the channel is obtained.
In the step, based on the clock jitter range of each channel, two adjacent channels of the channel are used as reference channels, a clock jitter value corresponding to the minimum clock jitter error of the channel is searched by using a bisection method, specifically, the clock jitter range of each channel is used as a search range of the bisection method, a clock jitter value is searched in the search range, the search range is gradually reduced by reducing the clock jitter error of the channel in the search process, and finally, a clock jitter value is searched to enable the clock jitter error of the channel to be minimum. The minimum clock jitter error referred to herein may be a clock jitter error equal to 0 at a predetermined accuracy. Or it may be the minimum clock jitter error obtained during the search up to a predetermined number of searches.
Clock jitter range t for each channel in search using dichotomy i_min ,t i_max ]In other words, the clock jitter range t is reduced by half each time i_min ',t i_max ']All satisfy
Namely, it is
And
always one is greater than 0 and the other is less than 0. Here, the，
Is according to t i_max ' corresponding to the calculated clock jitter error,
is according to t i_min ' corresponds to the calculated clock jitter error.
It will be appreciated that in each clock round, all channels of the ultra-high speed time-domain interleaved analog-to-digital converter are tested once. In the case of performing multiple rounds of clock detection, the order of detection of the channels in each round of detection is different.
For example, for the case of two clock detection rounds, one round of detection may preferentially detect the odd channel, detect the even channel later, and the other round of clock detection may preferentially detect the even channel and detect the odd channel later; for the case of only one round of clock detection, the odd channels or the even channels may be detected first and then the remaining channels may be detected.
S30: and determining the clock jitter value to be calibrated of each channel based on at least one group of clock jitter values obtained by clock detection.
There are various specific implementations of this step. For example, if only one round of clock detection is performed, a set of clock jitter values may be detected, a further numerical optimization operation may be performed on the basis of the set of clock jitter values, and so on. If multi-round clock detection is performed, further optimization processing can be performed on a plurality of groups of clock jitter values obtained by the multi-round clock detection, so that the final optimal clock jitter value of each channel is obtained and is used as the clock jitter value to be calibrated. For clarity of the layout of the scheme, the clock jitter values to be calibrated for each channel are determined based on at least one set of clock jitter values obtained by clock detection in the following process.
S40: and compensating the quantization codes of the channels according to the clock jitter values to be calibrated of the channels so as to finish clock jitter calibration.
Specifically, the clock jitter value to be calibrated of each channel is substituted into a taylor series expansion formula about the compensation quantization code, so that the quantization code of each channel is compensated, and the clock jitter calibration of each channel is realized.
The taylor series expansion about the compensation quantization code may be a first order taylor series expansion or a second order taylor series expansion. Wherein the first order Taylor series expansion is:
in the first order Taylor series expansion, Y i (k) Representing the quantised code before the i-th channel compensation, Y i_cal (k) Representing the channel compensated quantized code, also called compensated quantized code; t is t i The clock jitter value detected for that channel,
for the ith channel at Y i (k) The value of the derivative can be obtained in a manner of FIR (Finite Impulse Response) filter or the like in practical application; k represents the kth quantization code output by the channel.
In the wideband clock calibration method of the ultra-high-speed time domain interleaved analog-to-digital converter provided by the embodiment of the invention, clock detection is carried out based on the clock jitter range of each channel of the ultra-high-speed time domain interleaved analog-to-digital converter, and in each detection, two adjacent channels of each channel are used as reference channels to detect the channel; therefore, an additional auxiliary channel is not needed to be used as a reference channel for clock detection, and a certain channel in a time domain interleaving structure is not needed to be set as the reference channel manually, so that the calibration error caused by excessive dependence on a single reference channel is avoided, the clock calibration precision of the ultra-high-speed analog-to-digital converter can be improved, and the calibration error is reduced; in addition, in the clock detection process, the dichotomy is adopted to improve the detection precision, further improve the clock calibration precision of the ultra-high-speed analog-to-digital converter, and improve the calibration speed by adopting the dichotomy.
Next, determining the clock jitter value to be calibrated for each channel based on at least one group of clock jitter values obtained by clock detection is further exemplified.
For example, in one implementation, the clock detection described above may include two rounds; the odd channels can be detected preferentially in one round of detection, the even channels can be detected preferentially in the next round of detection, the even channels can be detected preferentially in the other round of detection, and the odd channels can be detected in the next round of detection.
Accordingly, the process of each of the two rounds of clock detection may include:
(1) Aiming at each channel which is preferentially detected, based on the clock jitter range of the channel, searching a clock jitter value corresponding to the minimum clock jitter error of the channel by utilizing a bisection method by taking two adjacent channels of the channel as reference channels to obtain a clock jitter value which is detected by the channel and a temporarily calibrated quantized code;
(2) And aiming at each non-priority detection channel, based on the clock jitter range of the channel, searching a clock jitter value corresponding to the minimum clock jitter error of the channel by using a dichotomy by taking two temporarily calibrated adjacent channels of the channel as reference channels, and obtaining the clock jitter value detected by the channel.
Wherein, the step (1) may specifically include:
aiming at each channel which is preferentially detected, searching the clock jitter value by taking the clock jitter range of the channel as a dichotomous searching range until the searched clock jitter value meets a first searching cutoff condition; the first search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using a Taylor series expansion formula about the compensation quantization code, the clock jitter error of the target channel calculated according to the compensation quantization code and the quantization codes of two adjacent channels of the channel is minimum;
and taking the clock jitter value searched when the search is ended as the clock jitter value detected by the channel, and taking the compensation quantization code calculated according to the clock jitter value as the quantization code temporarily calibrated by the channel.
For the taylor series expansion of the compensated quantized code, see the first-order taylor series expansion mentioned in step S40. And calculating the clock jitter error of the channel under detection according to the compensation quantization code and the quantization codes of two adjacent channels, and calculating according to the following processes:
the quantization codes of two adjacent channels are respectively substituted into the following two equations, and the compensation quantization code is also substituted into the two equations:
R i-1,i ＝E{Y i-1 (k)×Y i (k)}
R i,i+1 ＝E{Y i (k)×Y i+1 (k)}
wherein, Y i (k) Now representing the compensated quantization code of the channel under detection, Y i-1 (k) And Y i+1 (k) Then the quantization codes of two adjacent channels of the channel; e {. Represents expectation; r is i-1,i Representing the channel and output Y in the assay i-1 (k) The degree of autocorrelation of one adjacent channel; r i,i+1 Representing the channel and output Y in the assay i+1 (k) Of another adjacent channel. The autocorrelation degree can be understood as a function value of the autocorrelation function of the channel under test and its neighboring channels. It can be understood that, the channel under test and its adjacent channel all correspond to the same input signal, T represents an ideal sampling interval, and in practice, the sampling intervals of the channel under test and its adjacent channel may have a certain deviation Δ T with respect to T i (ii) a Thus, from the fact that the same input signal corresponds, the clock jitter error of the channel under test can be represented by the difference between the autocorrelation function values of the channel under test and its neighboring channels.
Then, with R i,i+1 Subtracting R i-1,i Namely, the clock jitter error D of the channel in the clock detection i 。
Similar to the step (1) above, the step (2) may specifically include:
aiming at each non-priority detection channel, searching a clock jitter value by taking a clock jitter range of the channel as a dichotomy search range until the searched clock jitter value meets a second search cut-off condition; the second search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using the Taylor series expansion formula, the clock jitter error of the channel calculated according to the compensation quantization code and the quantization codes temporarily calibrated by two adjacent channels of the channel is minimum;
and obtaining the clock jitter value after the channel detection is finished according to the clock jitter value searched when the search is cut off.
It is understood that the difference between step (2) and step (1) is that step (2) uses the quantization code after the temporary calibration of the adjacent channel when calculating the clock jitter error of the channel under test, and uses the quantization code when the adjacent channel is not temporarily calibrated in step (1).
Then, determining the clock jitter value to be calibrated of each channel based on two groups of clock jitter values obtained by two rounds of clock detection, which may specifically include:
(a1) The method comprises the following steps Substituting two groups of clock jitter values obtained by two rounds of clock detection into a first preset unary quadratic function; the first preset unitary quadratic function is a function of the proportion of each group of clock jitter values in a group of optimal clock jitter values;
(b1) The method comprises the following steps Calculating the proportion of each group of clock jitter values in a group of optimal clock jitter values corresponding to the minimum value of the first preset unitary quadratic function;
(c1) The method comprises the following steps And calculating the clock jitter value to be calibrated of each channel according to the calculated specific gravity and the two groups of clock jitter values.
Wherein the first predetermined unary quadratic function is:
in the first predetermined unary-quadratic function, t 1_i Represents a round of clock detection to obtain the clock jitter value of the ith channel in a group of clock jitter values, and u represents the group of clock jitterA weight of values in the set of optimal clock jitter values; t is t 2_i Representing another round of clock detection to obtain a clock jitter value of an ith channel in a group of clock jitter values, wherein 1-u represents the proportion of the group of clock jitter values in a group of optimal clock jitter values; n represents the total number of channels of the ultra-high speed time-domain interleaved analog-to-digital converter.
Wherein, when the value of the first predetermined unary quadratic function is minimum,
correspondingly, the specific implementation manner of the step (c 1) comprises the following steps:
and for each channel, multiplying the two clock jitter values belonging to the channel by the specific gravity corresponding to the respective group in the two groups of clock jitter values obtained by clock detection, and then summing to obtain the clock jitter value to be calibrated of the channel. Is formulated as:
t i '＝[t 2_i ×u+t 2_i ×(1-u)]
wherein, t i ' represents the clock jitter value to be calibrated for the ith channel.
It can be understood that a set of specific gravities corresponding to the minimum value of the first predetermined unitary quadratic function is an optimal specific gravity, and accordingly, the finally obtained clock jitter value to be calibrated in the embodiment of the present invention is a set of optimal clock jitter values.
Fig. 3 is a schematic diagram illustrating a schematic diagram of a wideband clock calibration for implementing an ultra-high speed time-domain interleaved analog-to-digital converter through two rounds of clock detection.
In another implementation manner, the clock detection may include one round, and the process of the clock detection in the round may refer to the process of each round of clock detection in the above two-round clock detection embodiment, which is not described herein again.
Correspondingly, determining the clock jitter value to be calibrated for each channel based on a set of clock jitter values obtained from a round of clock detection may include:
(a2) The method comprises the following steps Substituting a group of clock jitter values obtained by one round of clock detection into a second preset unary quadratic function; the second predetermined unitary quadratic function is a function of a clock baseline for the set of clock jitter values;
(b2) The method comprises the following steps Calculating a clock baseline corresponding to the minimum value of the second preset unary quadratic function;
(c2) The method comprises the following steps And calculating the clock jitter value to be calibrated of each channel according to the obtained clock base line and the group of clock jitter values.
Wherein the second predetermined unary quadratic function is:
in the second predetermined unary-quadratic function, t i Representing the clock jitter value, t, of the ith channel in a set of clock jitter values derived from clock detection ref Representing the derived clock baseline.
In step (b 2), when the value of the second predetermined unitary quadratic function is minimum,
accordingly, in step (c 2),
wherein, t i ' represents the optimal clock jitter value for the ith channel.
It can be understood that the clock baseline obtained based on the minimum value of the second preset unitary quadratic function is an optimal clock baseline, and correspondingly, the clock jitter value to be calibrated finally obtained in the embodiment of the present invention is a set of optimal clock jitter values.
Fig. 4 is a schematic diagram illustrating a schematic diagram of a wideband clock calibration for an ultra-high speed time-domain interleaved analog-to-digital converter with one round of clock detection.
In addition, it is understood that for embodiments larger than two-round clock detection, each channel may be detected in turn after the detection order of the channels is selected, according to the process of each detection in the two-round clock detection embodiment described above; for the channel detected later, when calculating the clock jitter error of the channel, if the adjacent channel of the channel is not temporarily calibrated, the quantization code which is not temporarily calibrated is used, and if the adjacent channel of the channel is temporarily calibrated, the quantization code which is temporarily calibrated is used.
Correspondingly, when the clock jitter values to be calibrated of each channel are determined according to the clock jitter values greater than the two groups, a group of clock jitter values to be calibrated can be calculated according to each group of clock jitter values by referring to the determination mode in the embodiment of the 1-round calibration; then, the average value of each group of clock jitter values to be calibrated is obtained according to the channels, so as to obtain the final clock jitter value to be calibrated of each channel.
The method provided by the embodiment of the invention can be applied to electronic equipment. Specifically, the electronic device comprises a super-high-speed time domain interleaving analog-to-digital converter. The specific device type is not limited herein, and any electronic device to which the wideband clock calibration method provided by the embodiments of the present invention can be applied belongs to the protection scope of the present invention.
It should be noted that, for the embodiment of the electronic device, since it is basically similar to the embodiment of the method, the description is relatively simple, and for the relevant points, reference may be made to part of the description of the embodiment of the method.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the specification, reference to the description of the term "one embodiment", "some embodiments", "an example", "a specific example", or "some examples", etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A wideband clock calibration method for an ultra-high-speed time-domain interleaved analog-to-digital converter is characterized by comprising the following steps:
acquiring a clock jitter range of each channel of the ultra-high-speed time domain interleaved analog-to-digital converter;
performing at least one round of clock detection on each channel based on the acquired clock jitter range to obtain at least one group of clock jitter values; in each round of clock detection, aiming at each channel, based on the clock jitter range of the channel, taking two adjacent channels of the channel as reference channels, and searching a clock jitter value corresponding to the minimum clock jitter error of the channel by using a dichotomy to obtain a clock jitter value detected by the channel;
determining a clock jitter value to be calibrated of each channel based on the at least one group of clock jitter values;
according to the clock jitter value to be calibrated of each channel, compensating the quantization code of each channel to finish clock jitter calibration;
wherein, the detection sequence of the channels in each round of clock detection is different; the clock jitter error for each channel is: the difference between the autocorrelation function values of two adjacent channels of the channel and the channel;
determining the clock jitter value to be calibrated of each channel based on the at least one group of clock jitter values, wherein the method comprises two modes;
the first mode is as follows:
the clock detection comprises two rounds; preferentially detecting an odd channel in one round of clock detection, detecting an even channel in the next round of clock detection, preferentially detecting the even channel in the next round of clock detection, and detecting the odd channel in the next round of clock detection;
the determining the clock jitter value to be calibrated for each channel based on the at least one group of clock jitter values includes:
substituting two groups of clock jitter values obtained by two clock detections into a first preset unary quadratic function; the first preset unary quadratic function is a function of the proportion of each group of clock jitter values in a group of optimal clock jitter values;
calculating the proportion of each group of clock jitter values in the group of optimal clock jitter values corresponding to the minimum value of the first preset unitary quadratic function;
calculating the clock jitter value to be calibrated of each channel according to the calculated specific gravity and the two groups of clock jitter values;
the first predetermined unary quadratic function is:
wherein, t 1_i Representing the clock jitter value of the ith channel in a group of clock jitter values obtained by one round of clock detection, and u represents the proportion of the group of clock jitter values in the group of clock jitter values to be calibrated; t is t 2_i Representing the clock jitter value of the ith channel in a group of clock jitter values obtained by another round of clock detection, 1-u representing the groupThe proportion of the clock jitter value in the group of clock jitter values to be calibrated; n represents the total number of channels of the ultra-high speed time domain interleaved analog-to-digital converter;
the second mode is as follows:
in any round of clock detection, an odd channel or an even channel is detected preferentially, and the rest channels are detected later;
the determining the clock jitter value to be calibrated for each channel based on the at least one group of clock jitter values includes:
substituting a group of clock jitter values obtained by any round of clock detection into a second preset unary quadratic function; the second predetermined unitary quadratic function is a function of a clock baseline for the set of clock jitter values;
calculating a clock baseline corresponding to the minimum value of the second preset unary quadratic function;
calculating the clock jitter value to be calibrated of each channel according to the obtained clock baseline and the group of clock jitter values;
the second predetermined unary-quadratic function is:
wherein, t i A clock jitter value, t, representing the ith channel in the set of clock jitter values ref Representing the clock baseline.
2. The method of claim 1, wherein each round of the clock detection process comprises:
aiming at each channel which is preferentially detected, based on the clock jitter range of the channel, two adjacent channels of the channel are taken as reference channels, and a clock jitter value corresponding to the minimum clock jitter error of the channel is searched by utilizing a bisection method to obtain the clock jitter value detected by the channel and the temporarily calibrated quantization code;
and aiming at each non-priority detection channel, based on the clock jitter range of the channel, searching a clock jitter value corresponding to the minimum clock jitter error of the channel by using a dichotomy by taking two temporarily calibrated adjacent channels of the channel as reference channels, and obtaining the clock jitter value detected by the channel.
3. The method of claim 2, wherein the searching for the clock jitter value corresponding to the minimum clock jitter error of the channel by using bisection method with two adjacent channels of the channel as reference channels based on the clock jitter range of the channel for each channel with priority detection to obtain the clock jitter value after the detection of the channel and the temporarily calibrated quantized code comprises:
aiming at each channel which is preferentially detected, searching a clock jitter value by taking a clock jitter range of the channel as a dichotomous searching range until the searched clock jitter value meets a first searching cut-off condition; the first search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using a Taylor series expansion formula about the compensation quantization code, the clock jitter error of the channel calculated according to the compensation quantization code and the quantization codes of two adjacent channels of the channel is minimum;
and taking the clock jitter value searched when the search is ended as the clock jitter value detected by the channel, and taking the compensation quantization code calculated according to the clock jitter value as the quantization code temporarily calibrated by the channel.
4. The method according to claim 3, wherein the step of searching for the clock jitter value corresponding to the minimum clock jitter error of the channel by using dichotomy for each non-priority detection channel based on the clock jitter range of the channel and using two temporally calibrated adjacent channels of the channel as reference channels to obtain the clock jitter value of the channel after detection comprises:
aiming at each non-priority detection channel, searching a clock jitter value by taking a clock jitter range of the channel as a dichotomy search range until the searched clock jitter value meets a second search cut-off condition; the second search cutoff condition includes: according to the clock jitter value searched currently, after a compensation quantization code is calculated by using the Taylor series expansion formula, the clock jitter error of the channel calculated according to the compensation quantization code and the quantization codes temporarily calibrated by two adjacent channels of the channel is minimum;
and taking the clock jitter value searched when the search is cut off as the clock jitter value of the channel detection completion.
5. The method according to claim 1, wherein said calculating the clock jitter value to be calibrated for each channel according to the calculated specific gravity and the two sets of clock jitter values comprises:
and for each channel, multiplying the two clock jitter values belonging to the channel by the specific gravity corresponding to the respective group, and then summing to obtain the clock jitter value to be calibrated of the channel.
6. The method of claim 1, wherein calculating the clock jitter value to be calibrated for each channel according to the determined clock baseline and the set of clock jitter values comprises:
and subtracting the obtained clock base line from the clock jitter value of each channel in the group of clock jitter values to obtain the clock jitter value to be calibrated of each channel.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9000962B1 (en) * | 2014-01-28 | 2015-04-07 | Cadence Design Systems, Inc. | System and method for interleaved analog-to-digital conversion having scalable self-calibration of timing |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN110048717A (en) * | 2019-03-20 | 2019-07-23 | 新岸线(北京)科技集团有限公司 | It is a kind of to realize the time-interleaved self-alignment method and device of analog-digital converter |
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| US7450043B2 (en) * | 2006-10-31 | 2008-11-11 | Lecroy Corporation | Method of compensating for deterministic jitter due to interleave error |
| CN104038226B (en) * | 2014-06-25 | 2018-06-05 | 华为技术有限公司 | The time-interleaved analog-digital converter of multichannel |
| WO2016082899A1 (en) * | 2014-11-28 | 2016-06-02 | Advantest Corporation | Removal of sampling clock jitter induced in an output signal of an analog-to-digital converter |
| US10917103B2 (en) * | 2019-01-23 | 2021-02-09 | Global Unichip Corporation | Analog-to-digital converter device and method for calibrating clock skew |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9000962B1 (en) * | 2014-01-28 | 2015-04-07 | Cadence Design Systems, Inc. | System and method for interleaved analog-to-digital conversion having scalable self-calibration of timing |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN110048717A (en) * | 2019-03-20 | 2019-07-23 | 新岸线(北京)科技集团有限公司 | It is a kind of to realize the time-interleaved self-alignment method and device of analog-digital converter |
Non-Patent Citations (2)
| Title |
|---|
| 一种时间交替ADC时间失配误差自适应校正方法;秦国杰等;《仪器仪表学报》;20131215(第12期);全文 * |
| 基于FPGA的自适应TIADC数据采集;叶忠辉等;《数学的实践与认识》;20150423(第08期);全文 * |
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