CN112187041A

CN112187041A - Standby voltage regulating method of charge pump circuit

Info

Publication number: CN112187041A
Application number: CN202010931820.8A
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2021-01-05
Anticipated expiration: 2040-09-08
Also published as: CN112187041B

Abstract

The application relates to the field of memories, in particular to a standby voltage adjusting method of a charge pump circuit. The charge pump circuit includes: a charge pump, an oscillator, and a comparator; the standby voltage regulation method of the charge pump circuit comprises the following steps: so that the comparator is in a slow working state; enabling the comparator to collect the output voltage of the charge pump to obtain a sampling voltage; the comparator compares the magnitude relation of the sampling voltage and the reference voltage, delays for a period of slow reaction time, and outputs an enable signal to the oscillator according to the comparison result; when the enable signal is at high level, the oscillator outputs a clock signal; the charge pump outputs a gradually rising output voltage according to the clock signal. The method and the device can solve the problem that in the related technology, the comparator frequently switches the working state at the critical moment, so that the power consumption of the standby state of the charge pump circuit is large.

Description

Standby voltage regulating method of charge pump circuit

Technical Field

The application relates to the field of memories, in particular to a standby voltage adjusting method of a charge pump circuit.

Background

A charge pump is a switched capacitor voltage converter that uses a switching element to control the voltage connected to a capacitive element, and a DC-DC converter that uses a capacitive element to store energy can be used to generate an output voltage that is greater than an input voltage or to generate a negative output voltage.

Fig. 1 is a circuit schematic diagram of a charge pump circuit in the related art, and referring to fig. 1, the charge pump circuit includes: the charge pump, the oscillator and the comparator are used for sampling the output voltage D of the charge pump to obtain a sampling voltage Vde, the inverting input end of the comparator is connected with the sampling voltage Vde, the non-inverting input end of the comparator is connected with a reference voltage source Vre, the output end of the comparator is connected with the oscillator, and the oscillator can output a clock signal Cl to the charge pump; the output enable signal Vout-2 of the comparator is provided to the oscillator, when the enable end EN of the comparator inputs a high level signal, the comparator is in a fast working state, and when the enable end EN of the comparator inputs a low level signal, the comparator is in a slow working state.

Theoretically, when the sampling voltage Vde is smaller than the reference voltage source Vre, the comparator inputs a high-level enable signal Vout-2 to the oscillator, the oscillator generates a clock signal Cl according to the high-level enable signal Vout-2, and the charge pump gradually increases the output voltage D to a target value under the action of the clock signal Cl; when the output voltage D reaches the target value, the value of the sampling voltage Vde is equal to the value of the reference voltage Vre, so that the comparator outputs a low level of the enable signal Vout-2, the clock signal Cl cannot be generated, and the charge pump stops working, so that the output voltage D gradually decreases until the target value is reached again, that is, the charge pump starts working, and the output voltage D climbs, thereby repeating.

However, since the comparator itself has a certain switching speed, i.e. needs a certain response time, the related art generally connects the output terminal of the comparator to the enable terminal EN, and when the enable terminal of the comparator inputs a high-level signal, the comparator is in a fast operating state, and when the enable terminal EN of the comparator inputs a low-level signal, the comparator is in a slow operating state. When the comparator is in a fast working state, the response time of the comparator is shorter, namely the fast response time T2; when the comparator is in the slow operation state, the response time of the comparator is longer, which is the slow response time T1.

Fig. 2 is a timing diagram of a positive input signal Vre, a negative input signal Vde, a theoretical output signal Vout-1, and an actual output signal Vout-2 of a comparator in a related art charge pump circuit, and fig. 2:

in the time period from T0 to T11, the input signal Vde at the inverting terminal continuously falls, and the input signal Vde at the inverting terminal is continuously greater than the input signal Vre at the non-inverting terminal, the theoretical output signal Vout-1 is at a low level, and the actual output signal Vout-2 is at a low level, so that the comparator is in a slow operating state, and the reaction time of the comparator in the slow operating state is T1.

At the time T11, the input signal Vde at the inverting terminal falls to be equal to the input signal Vre at the non-inverting terminal, and the theoretical output signal Vout-1 has a rising edge, but since the comparator is in the slow operation state, there is a reaction time T1, so the actual output signal Vout-2 is still at the low level at the time T11, and the state of the low level continues for a time period T1 from the time T11, the time period T1 is the reaction time of the comparator in the slow state, that is, at the time T12 after the reaction time T1 elapses, the actual output signal Vout-2 has a rising edge, and after the rising edge of the actual output signal Vout-2, the comparator switches to the fast operation state, and the reaction time of the comparator in the fast operation state is T2.

In the time period from t12 to t13, the charge pump continuously raises the output voltage along with the clock signal, that is, the voltage of the input signal Vde at the inverting terminal continuously rises, and the voltage of the input signal Vde at the inverting terminal is smaller than that of the input signal Vre at the non-inverting terminal, the actual output signal Vout-2 is at a high level, and the comparator is in a fast working state.

At the time T13, the input signal Vde at the inverting terminal rises to be equal to the input signal Vre at the non-inverting terminal, and the theoretical output signal Vout-1 has a falling edge, but because the comparator is in a fast operating state and there is a reaction time T2, the actual output signal Vout-2 is still at a high level at the time T13, and the high level state lasts for a time period T2 from the time T13, that is, after the reaction time T2 elapses, the falling edge does not occur to the actual output signal Vout-2 at the time T1, so that during the time period T13-T1, the charge pump continues to operate and can continue to raise its output voltage, and further the voltage of the input signal Vde at the inverting terminal rises during the time period until the actual output signal Vout-2 falls at the time T1, and the charge pump stops operating.

However, at the critical moment when the actual output signal Vout-2 has a rising edge or a falling edge, the comparator will perform the corresponding operation state switching. That is, the time when the actual output signal Vout-2 has a rising edge (for example, the time t12 shown in fig. 2), is a critical time when the comparator is switched from the slow operating state to the fast operating state; at the time when the actual output signal Vout-2 falls (e.g., at time t1 shown in fig. 2), the comparator is switched from the fast operating state to the fast/slow operating state at the critical time. Because the difference between the response time of the comparator in the slow operating state and the response time of the comparator in the fast operating state is large, the voltage value of the input signal Vde at the inverting terminal of the actual output signal Vout-2 in the slow operating state is inconsistent with that in the fast operating state, and the comparator still frequently switches the operating state at the critical moment, so that the power consumption of the charge pump circuit in the standby state is large.

Disclosure of Invention

The application provides a standby voltage adjusting method of a charge pump circuit, which can solve the problem that in the related technology, a critical moment comparator frequently switches working states, so that the power consumption of the charge pump circuit in a standby state is large.

The application provides a standby voltage regulating method of a charge pump circuit, wherein the charge pump circuit comprises: a charge pump, an oscillator, and a comparator; the standby voltage regulation method of the charge pump circuit comprises the following steps:

enabling the comparator to be in a slow working state;

enabling the comparator to collect the output voltage of the charge pump to obtain a sampling voltage;

the comparator compares the magnitude relation between the sampling voltage and the reference voltage, delays for a period of slow reaction time, and outputs an enable signal to the oscillator according to the comparison result;

when the enable signal is at a high level, the oscillator outputs a clock signal;

the charge pump outputs a gradually rising output voltage according to the clock signal.

Optionally, an inverting input terminal of the comparator is connected to the output terminal of the charge pump, a non-inverting input terminal of the comparator is connected to the reference voltage, and an output terminal of the comparator is connected to the oscillator, where the oscillator is capable of outputting a clock signal to the charge pump.

Optionally, when the comparator is in a slow operation state, the signal output time of the comparator is delayed by a slow response time than the signal input time.

Optionally, one of the slow reaction times is from 35ns to 45 ns.

Optionally, the specific oscillation frequency of the clock signal is 8.7MHZ-11.2 MHZ.

Optionally, the clock signal has a specific oscillation frequency that matches the slow operating state of the comparator.

Optionally, if the sampling voltage is smaller than the reference voltage, delaying for a slow response time, and outputting the low level of the enable signal to the oscillator;

when the enable signal is at a low level, the oscillator does not output a clock signal;

the charge pump stops working, and the output voltage is gradually reduced.

Optionally, when the sampling voltage is equal to the reference voltage, delaying for a slow response time, and then outputting a rising edge or a falling edge of the enable signal to the oscillator;

the oscillator is in a critical state of outputting and not outputting the Clock signal Clock;

the charge pump is in a critical state of working and stopping working, and the output voltage is bent.

The technical scheme at least comprises the following advantages: since the comparator is always in the slow operation state when the charge pump circuit is in the standby state, the delays at the respective points are the same and are the reaction time T1, and the magnitude of the sampling voltage Vdet at which the comparator enable signal Vout switches (from the high level to the low level, or from the low level to the high level) at the critical time coincides with the reference voltage Vref, and further, the enable signal Vout does not frequently switch at the critical time, and the power consumption of the charge pump circuit in the standby state can be reduced.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a circuit schematic diagram of a charge pump circuit in the related art;

FIG. 2 is a timing diagram of signals in a related art charge pump circuit;

fig. 3 is a schematic diagram of a charge pump circuit according to an embodiment of the present application;

fig. 4 is a flowchart of a method for adjusting a standby voltage of a charge pump circuit according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of signals in a charge pump circuit according to an embodiment of the present disclosure;

fig. 6 is a flowchart of a method for adjusting a standby voltage of a charge pump circuit according to another embodiment of the present application;

fig. 7 is a timing diagram of signals in a charge pump circuit and related technologies on the same time axis according to an embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other. The positive phase input end of the comparator is connected with a reference voltage source, and the negative phase input end of the comparator is used for collecting the output voltage of the charge pump;

fig. 3 is a schematic diagram of a charge pump circuit, and referring to fig. 3, the charge pump circuit includes: a charge pump, an oscillator, and a comparator. The charge pump is connected with an oscillator capable of inputting a Clock signal Clock to the charge pump, the oscillator is connected with a comparator capable of inputting an enable signal Vout to the oscillator, the comparator samples an output voltage VD of the charge pump to obtain a sampling voltage Vdet, an inverting input end of the comparator is connected with the sampling voltage Vdet, a non-inverting input end of the comparator is connected with a reference voltage Vref, and an output end of the comparator is connected with the oscillator. The enable terminal EN of the comparator is connected to the low level signal "0" so that the comparator is in a slow operation state. When the comparator is in the slow operation state, the signal output time of the comparator is delayed by a slow reaction time T1 from the signal input time.

Referring to fig. 4 and 5, a flowchart of a method for adjusting a standby voltage of a charge pump circuit according to an embodiment of the present application is shown in fig. 4, and a timing diagram of the charge pump circuit according to an embodiment of the present application is shown in fig. 5, where the method for adjusting a standby voltage of a charge pump circuit according to an embodiment of the present application includes the following steps:

step S1: so that the comparator is in a slow operating state.

Step S2: and enabling the comparator to collect the output voltage VD of the charge pump to obtain a sampling voltage Vdet.

Step S3: and enabling the comparator to compare the magnitude relation between the sampling voltage Vdet and the reference voltage Vref, delaying for a slow reaction time T1, and outputting an enable signal Vout to an enable end of the oscillator according to the comparison result.

As an example, the slow reaction time T1 is 35ns to 45 ns.

In this embodiment, if the sampling voltage Vdet in the step S3 is smaller than the reference voltage Vref, the high-level signal of the enable signal Vout is output to the oscillator after a delay of a slow response time T1.

Step S4: when the enable signal Vout is high, the oscillator outputs a Clock signal Clock.

As an embodiment, when the enable signal Vout is high, the oscillator outputs a Clock signal Clock having a specific oscillation frequency that matches the slow operation state of the comparator. The Clock signal Clock has a specific oscillation frequency of 8.7MHZ-11.2 MHZ.

In order to match the slow reaction time T1 with the specific oscillation frequency of the Clock signal Clock, optionally, when the slow reaction time T1 is 40ns, the specific oscillation frequency of the Clock signal Clock is 10 MHZ.

Step S5: the charge pump outputs a gradually raised output voltage VD according to the Clock signal Clock.

It should be explained that when the specific oscillation frequency of the Clock signal Clock matches the slow operation state of the comparator, the output voltage VD of the charge pump is not raised to an excessive degree by the Clock signal Clock during the operation of the charge pump in step S5, and the problem of high voltage overshoot of the output voltage VD can be avoided.

The embodiment executes step S2 after step S5 is completed, so as to implement the standby state of the charge pump circuit.

Referring to fig. 5, the sampled voltage Vdet is less than the reference voltage Vref for a time period T11-T21, and the comparator outputs a high level of the enable signal Vout after a delay of a slow reaction time T1, i.e., for a time period T12-T2. In a period in which the enable signal Vout is high, i.e., a t12-t2 period, the oscillator outputs the Clock signal Clock. The charge pump outputs a gradually raised output voltage VD according to the Clock signal Clock, and then the sampling voltage Vdet is raised along with the raising of the output voltage VD.

In this embodiment, since the comparator is always in the slow operation state when the charge pump circuit is in the standby state, the delays at the respective points are the same and are the reaction time T1, and the magnitude of the sampling voltage Vdet at which the comparator enable signal Vout switches (from the high level to the low level, or from the low level to the high level) at the critical time coincides with the reference voltage Vref, and further, the enable signal Vout does not frequently switch at the critical time, and the power consumption of the charge pump circuit in the standby state can be reduced.

Fig. 6 shows a flowchart of a standby voltage adjustment method of a charge pump circuit according to another embodiment of the present application.

Referring to fig. 6, if the sampled voltage Vdet in step S3 is less than the reference voltage Vref, a low level signal of the enable signal Vout is output to the oscillator after a delay of a slow reaction time T1, and then steps S6 and S7 are sequentially performed.

Step S6: when the enable signal Vout is low, the oscillator does not output the Clock signal Clock.

Step S7: the charge pump stops working, and the output voltage VD is gradually reduced.

The embodiment executes step S2 after step S7 is completed, so as to implement the standby state of the charge pump circuit.

Referring to fig. 5, the sampled voltage Vdet is greater than the reference voltage Vref for a time period T0-T11, and the comparator outputs a low level of the enable signal Vout after a delay of a slow reaction time T1, i.e., before a time T12. In the time period when the enable signal Vout is at the low level, the oscillator does not output the clock signal, the charge pump stops operating, the output voltage VD gradually decreases, and the sampling voltage Vdet decreases with the decrease of the output voltage VD.

With continued reference to fig. 5, the sampled voltage Vdet is greater than the reference voltage Vref for a time period T21-T2, and the comparator outputs a low level of the enable signal Vout after a delay of a slow reaction time T1, i.e., after time T2. In the time period when the enable signal Vout is at the low level, the oscillator does not output the clock signal, the charge pump stops operating, the output voltage VD gradually decreases, and the sampling voltage Vdet decreases with the decrease of the output voltage VD.

If the sampled voltage Vdet in the step S3 is equal to the reference voltage Vref, a rising edge or a falling edge of the enable signal Vout is output to the oscillator after a delay of a slow response time T1, and then the steps S6 and S7 are sequentially performed.

When the enable signal Vout rises or falls, the enable signal Vout performs a switching operation, that is, switching from high level to low level or from low level to high level.

Step S8: the oscillator is in a critical state to output and not output the Clock signal Clock.

Step S9: the charge pump is in a critical state of working and stopping working, and the output voltage VD is bent at the critical state moment of working and stopping working of the charge pump.

The embodiment executes step S2 after step S9 is completed, so as to implement the standby state of the charge pump circuit.

Referring to fig. 5, at time T11, the sampled voltage Vdet drops to be equal to the reference voltage Vref, and after a delay of a slow response time T1, i.e., at time T12, the rising edge of the enable signal Vout is output to the oscillator. When the oscillator receives the rising edge of the enable signal Vout, the oscillator is in a critical state that the Clock signal Clock is not output and the Clock signal Clock is switched to be output, and the charge pump is in a critical state that the operation is stopped and the operation is switched to be started. From the time t12, the output voltage VD transitions from a decreasing trend to a rising trend, and thus the sampled voltage Vdet also undergoes a rising transition at the time t 12.

With continued reference to fig. 5, at time T21, the sampled voltage Vdet rises to be equal to the reference voltage Vref, and after a delay of a slow reaction time T1, i.e., at time T2, the falling edge of the output enable signal Vout is given to the oscillator. When the oscillator receives the falling edge of the enable signal Vout, the oscillator is in a critical state that the output Clock signal Clock turns to start stopping the output Clock signal Clock, and the charge pump is in a critical state that the work turns to start stopping the work. From time t2, the output voltage VD transitions from a rising trend to a falling trend, and thus the sampled voltage also transitions from falling at time t 2.

The process is that the charge pump circuit is in a standby state, and the standby voltage adjusting method of the charge pump circuit provided by the embodiment can avoid the problem that the comparator still frequently switches the working state for a period of time after the critical moment, so that the power consumption of the charge pump circuit in the standby state is reduced.

Fig. 7 is a timing chart of the related art and the embodiment of the present application on the same time axis.

Referring to fig. 7, the comparator in the related art and the embodiment of the present application is in a slow operation state during the time period t0-t 12. For the related art, the fast operation state is transferred at the time t12, and the comparator is continuously in the fast operation state for the time period t12-t1 until the slow operation state is transferred at the time t 1.

For the embodiment of the application, the comparator is in a slow-speed working state, that is, the change of the sampling voltage Vdet in the related art in the corresponding time period t12-t1 is prolonged to the change of the sampling voltage Vdet in the corresponding time period t12-t2, and the period of the Clock signal Clock oscillation in the time period t12-t2 is the same as the period of the Clock signal Clock oscillation in the time period t12-t1 in the related art, so that the problem of high-voltage overshoot of the output voltage VD can be avoided.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A method for adjusting a standby voltage of a charge pump circuit, the charge pump circuit comprising: a charge pump, an oscillator, and a comparator; the standby voltage regulation method of the charge pump circuit comprises the following steps:

enabling the comparator to be in a slow working state;

2. The method of claim 1, wherein the comparator has an inverting input connected to the output of the charge pump, a non-inverting input connected to a reference voltage, and an output connected to the oscillator, wherein the oscillator is capable of outputting a clock signal to the charge pump.

3. The method of claim 1, wherein when the comparator is in a slow operation state, the signal output time of the comparator is delayed by a slow response time from the signal input time.

4. A method for regulating standby voltage of a charge pump circuit as claimed in claim 1 or 3, characterized in that a period of said slow reaction time is 35ns-45 ns.

5. The standby voltage adjusting method of a charge pump circuit according to claim 1, wherein the specific oscillation frequency of the clock signal is 8.7MHZ-11.2 MHZ.

6. The method of regulating standby voltage of a charge pump circuit according to claim 1, wherein said clock signal has a specific oscillation frequency matched to a slow operation state of said comparator.

7. The method of claim 1, wherein if the sampled voltage is less than the reference voltage, delaying a slow response time and outputting the low level of the enable signal to the oscillator;

the charge pump stops working, and the output voltage is gradually reduced.

8. The method of adjusting a standby voltage of a charge pump circuit according to claim 1, wherein when the sampled voltage is equal to the reference voltage, the rising edge or the falling edge of the enable signal is output to the oscillator after a delay of a slow response time;

the oscillator is in a critical state of outputting and not outputting a clock signal;