Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first circuit may be termed a second circuit, and, similarly, a second circuit may be termed a first circuit, without departing from the scope of the present application. The first circuit and the second circuit are both circuits, but they are not the same circuit. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a block diagram of a module connection between an electromagnetic induction door lock and a key according to a first embodiment of the present invention, which is applicable to a situation of unlocking by wireless electromagnetic induction, and specifically, the electromagnetic induction door lock and the key according to the first embodiment of the present invention include: keys and door locks.
The key 1 is used for generating an electromagnetic field according to an unlocking signal or a locking signal. The key 1 comprises: wireless transmitting circuit 11, first master control circuit 12, battery circuit 13, decoding circuit 14 and detection circuitry 15, wireless transmitting circuit 11 with first master control circuit 12 is connected, battery circuit 13 with first master control circuit 12 with wireless transmitting circuit 11 connects, decoding circuit 14 with first master control circuit 12 connects, detection circuitry 15 with first master control circuit 12 connects.
In this embodiment, the key 1 can receive a control instruction of a user, where the control instruction includes an unlocking signal or a locking signal, and the user may contact the key 1 through a key or touch, or generate the control instruction through a communication connection between a terminal and the key 1. The wireless transmitting circuit 11 can generate an electromagnetic field after being energized, and electromagnetic induction is generated between the wireless receiving circuit 21, so that an induced current is generated in the wireless receiving circuit 21, and the induced current drives the motor driving circuit 23 to generate kinetic energy to control the door lock 2 to open or close. The first main control circuit 12 is an mcu (micro controller unit), also called a microcomputer or a single chip, which properly reduces the frequency and specification of the cpu, and integrates the peripheral interfaces such as memory, counter, USB, a/D conversion, UART, PLC, DMA, etc., and even the LCD driving circuit on a single chip to form a chip-level computer, which is controlled in different combinations for different applications. The battery circuit 13 may be used to supply power to the door lock 2 from an external battery, and may be connected to an external charger or an adapter, for example, to supply operating power to the door lock 2. The decoding circuit 14 is used for matching between the key 1 and the door lock 2, and illustratively, after the key 1 and the door lock 2 are connected through electromagnetic induction, the digital code ID carried by the door lock 2 can be identified, so that each door lock 2 is matched with each key 1. The detection circuit 15 is used for detecting various values in the circuit to ensure the smooth operation of the circuit, and may be, for example, voltage and current detection, etc.
The door lock 2 is used for generating induction current according to the electromagnetic field and driving an internal motor of the door lock 2 to close or open the door lock 2 through the induction current. The door lock 2 includes: wireless receiving circuit 21, second master control circuit 22, motor drive circuit 23, decode and send a yard circuit 24 and position detection circuit 25, wireless receiving circuit 21 with second master control circuit 22 is connected, motor drive circuit 23 with second master control circuit 22 is connected, decode and send a yard circuit 24 with second master control circuit 22 is connected, position detection circuit 25 with second master control circuit 22 is connected.
In this embodiment, the second master control circuit 22 is the same as the first master control circuit 12, and both use MCU. The motor driving circuit 23 includes an electric motor and a driving circuit, and the electric motor is driven to operate by an induced current generated by the wireless receiving circuit 21, and the electric motor unlocks or locks the door lock 2. The position detection circuit 25 is used to accurately position the door lock 2 according to the electric motor drive.
The embodiment discloses an electromagnetic induction's lock and key, includes: the key is used for generating an electromagnetic field according to an unlocking signal or a locking signal; and the door lock is used for generating induction current according to the electromagnetic field and closing or opening the door lock through the induction current. According to the electromagnetic induction door lock and the electromagnetic induction key, the electric drive is arranged in the door lock, so that the condition that power supply voltage is supplied from the outside of the door lock is avoided, the problems that the safety is low and the door lock is easy to crack due to the fact that the power supply voltage is supplied from the outside to the door lock in the prior art are solved, the effects of safely unlocking and safely locking are achieved, and the user experience is improved.
Example two
Fig. 2 is a module connection diagram of an electromagnetic induction door lock and key according to a second embodiment of the present invention, which is applicable to a situation of unlocking by wireless electromagnetic induction, and the present embodiment is divided into the following embodiments in detail on the basis of the first embodiment, specifically, the electromagnetic induction door lock and key according to the second embodiment of the present invention includes: a key 1 and a door lock 2.
The key 1 is used for generating an electromagnetic field according to an unlocking signal or a locking signal. The key 1 comprises: wireless transmitting circuit 11, first master control circuit 12, battery circuit 13, decoding circuit 14 and detection circuitry 15, wireless transmitting circuit 11 with first master control circuit 12 is connected, battery circuit 13 with first master control circuit 12 with wireless transmitting circuit 11 connects, decoding circuit 14 with first master control circuit 12 connects, detection circuitry 15 with first master control circuit 12 connects.
The wireless transmitting circuit 11 comprises a first wireless transmitting circuit 111 and a second wireless transmitting circuit 112, the first wireless transmitting circuit 111 is connected with the first main control circuit 12, and is configured to generate a first electromagnetic field according to the unlocking signal generated by the first main control circuit 12; the second wireless transmitting circuit 12 is connected to the first main control circuit 12, and is configured to generate a second electromagnetic field according to the lock-off signal generated by the first main control circuit 12.
Referring to fig. 3, fig. 3 is a circuit diagram of the wireless transmitting circuit 11 in the present embodiment, the first wireless transmitting circuit 111 includes: a resistor R11, a resistor R5, a capacitor C17, a chip U1, a capacitor C7, a resistor R6, a resistor R7, a resistor R12, a resistor R13, a chip U1, a chip Q1, a capacitor C2, a capacitor C3, a resistor FR1, a capacitor FC1, a capacitor CL1, and an inductor L2, a first end of the resistor R11 is connected to the voltage terminal VOUT, a second end of the resistor R11 is connected to the 5 th pin of the chip U1, a first end of the resistor R5 is connected to the voltage terminal VOUT, a second end is connected to the first end of the capacitor C17, a second end of the capacitor C17 is grounded, a first end of the capacitor C7 is connected to the 8 th pin of the chip U1, a second end of the capacitor C7 is connected to the 1 st pin of the chip U7, a first end of the resistor R7 is connected to the 3 rd pin of the chip U7, a second end of the resistor R7 is connected to the first end of the resistor R7, a second end of the resistor R7 is connected to the second end of the chip U7, a resistor R7 is connected to the, the second end of the resistor R13 is connected to the 3 rd pin of the chip Q1, the first end of the capacitor C2 is connected to the 6 th pin of the chip Q1, the second end of the capacitor C2 is connected to the voltage terminal ICOIL0, the first end of the capacitor C2 is connected to the 6 th pin of the chip Q1, the second end of the capacitor C3 is connected to the voltage terminal ICOIL0, the first end of the resistor FR1 is connected to the 8 th pin of the chip Q1, the second end of the resistor FR1 is connected to the first end of the capacitor FC1, the second end of the capacitor FC1 is connected to the voltage terminal ICOIL0, the first end of the capacitor CL1 is connected to the 8 th pin of the chip Q1, and the second end of the capacitor CL1 is connected to the first end of the inductor.
The second wireless transmission circuit 112 includes: a resistor R15, a resistor R8, a capacitor C18, a chip U2, a capacitor C7, a resistor R9, a resistor R10, a resistor R16, a resistor R17, a chip U2, a chip Q2, a capacitor C4, a capacitor C5, a resistor FR2, a capacitor FC2, and a resistor R29, a first end of the resistor R15 is connected to the voltage terminal VOUT, a second end of the resistor R15 is connected to the 5 th pin of the chip U2, a first end of the resistor R8 is connected to the voltage terminal VOUT, a second end is connected to the first end of the capacitor C18, a second end of the capacitor C18 is grounded, a first end of the capacitor C7 is connected to the 8 th pin of the chip U2, a second end of the capacitor C7 is connected to the 1 st pin of the chip U2, a first end of the resistor R9 is connected to the 3 rd pin of the chip U2, a second end of the resistor R2 is connected to the first end of the resistor R2, a second end of the resistor R2 is connected to the second end of the chip U2, a second end of the resistor R2 is, the second end of the resistor R17 is connected to the 3 rd pin of the chip Q2, the first end of the capacitor C4 is connected to the 6 th pin of the chip Q2, the second end of the capacitor C4 is connected to the voltage terminal ICOIL0, the first end of the capacitor C5 is connected to the 6 th pin of the chip Q2, the second end of the capacitor C5 is connected to the voltage terminal ICOIL0, the first end of the resistor FR2 is connected to the 8 th pin of the chip Q2, the second end of the resistor FR2 is connected to the first end of the capacitor FC2, the second end of the capacitor FC2 is connected to the first end of the resistor R29, and the second end of the resistor R29 is grounded.
Fig. 4 is a circuit diagram of the first master control circuit 12 in this embodiment. The first main control circuit 12 includes a chip U4, and the chip U4 is an MCU, which may be replaced by a chip such as a CPU in alternative embodiments.
The battery circuit 13 comprises a battery charging and discharging circuit 131, a battery protection circuit 132, a 3.3V voltage stabilizing circuit 133 and a 9V voltage boosting circuit 134, wherein the battery charging and discharging circuit 131 is used for being connected with an external power supply to charge and discharge the battery; the battery protection circuit 132 is connected with the battery charging and discharging circuit 131 and is used for protecting the battery from stable power supply; the 3.3V voltage stabilizing circuit 133 is connected between the battery protection circuit 132 and the first main control circuit 12, and the 3.3V voltage stabilizing circuit 133 is configured to reduce the battery voltage to 3.3V and input the reduced battery voltage into the first main control circuit 12; the 9V boost circuit 134 is connected between the battery protection circuit 132 and the wireless transmission circuit 11, and is used for boosting the battery voltage to 9V and inputting the battery voltage into the wireless transmission circuit 11.
Fig. 5 is a circuit diagram of the battery charging and discharging circuit 131 in the present embodiment, and the battery charging and discharging circuit 131 includes: a resistor R68, a resistor R70, a resistor R71, a resistor R69, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C67, a chip IC1, a capacitor C68, a capacitor C69, a capacitor C70, an inductor L1, a resistor R74, a capacitor C74, a resistor R74, an LED 74, and an LED 74, a first end of the resistor R74 is connected to a terminal J74, a second end of the resistor R74 is connected to a battery, a first end of the resistor R74 is connected to the terminal J74, a second end of the resistor R74 is connected to the first end of the capacitor C74, a second end of the capacitor R74 is connected to the first end of the capacitor C74, a first end of the resistor R74 is connected to the terminal J74, a second end of the capacitor C74 is connected to the capacitor C74, a terminal C74 is connected to the capacitor C74, a second end of the capacitor C74 is connected to the capacitor C74, a capacitor C, an anode of the LED1 is connected to the 2 nd pin of the chip IC1, a cathode of the LED1 is connected to an anode of the LED2, a cathode of the LED2 is connected to the 2 nd pin of the chip IC1, a cathode of the LED3 is connected to the chip IC 3, an anode of the LED3 is connected to the 4 th pin of the chip IC 3, a first end of the capacitor C3 is connected to the 8 th pin of the chip IC 3, a second end of the capacitor C3 is grounded, a first end of the inductor L3 is connected to the 7 th pin of the chip IC 3, a second end of the resistor R3 is connected to the first end of the capacitor C3, a second end of the capacitor C3 is grounded, a first end of the capacitor L3 is connected to the second pin of the inductor L3, a second end of the capacitor R3 is connected to the second pin of the capacitor C3, and a second end of the capacitor C365 is connected to the second pin of the capacitor C3 is connected to the ground, the second terminal of resistor R72 is connected to the first terminal of resistor R73.
Fig. 6 is a circuit diagram of the battery protection circuit 132 in the present embodiment, and the battery protection circuit 132 includes: the circuit comprises a resistor R75, a capacitor C73, a capacitor C74 and a chip U2, wherein a first end of the resistor R75 is connected to a battery, a second end of the resistor R75 is connected to a first end of the capacitor C73, a second end of the capacitor C73 is connected to a pin 6 of the chip U2, a first end of the capacitor C74 is grounded, and a second end of the capacitor C74 is connected to a pin 9 of the chip U2.
Fig. 7 is a circuit diagram of the 3.3V regulator circuit 133 in this embodiment, and the 3.3V regulator circuit 133 includes: the chip U8, the electric capacity C81 and electric capacity C82, the first end of electric capacity C81 is connected to the 3 rd pin of chip U8, the second end ground of electric capacity C81, the first end of electric capacity C82 is connected to the 2 nd pin of chip U8, the second end ground of electric capacity C82.
Fig. 8 is a circuit diagram of the 9V boost circuit 134 in the present embodiment, and the 9V boost circuit 134 includes: capacitor C63, diode D1, resistor R61, resistor R62, chip U3, inductor L2, resistor R63, resistor R64, capacitor C61 and capacitor C62, a first end of capacitor C63 is grounded, a second end of capacitor C63 is connected to the negative electrode of diode D1, the positive electrode of diode D1 is connected to the first end of inductor L2, a second end of inductor L2 is connected to the first end of capacitor C61, the second end of capacitor C61 is grounded, the first end of capacitor C62 is connected to the second end of inductor L2, the second end of capacitor C62 is grounded, the first end of resistor R61 is connected to the second end of capacitor C63, the second end of resistor R61 is connected to the 3 rd pin of chip U3, the first end of resistor R62 is grounded, the second end of resistor R62 is connected to the 3 rd pin of chip U3, the second end of resistor R63 is connected to the first end of resistor R64, and the second end of resistor R64 is grounded.
The decoding circuit 14 includes a first voltage decoding circuit 141 and a first current decoding circuit 142, the first voltage decoding circuit 141 is connected to the first main control circuit 12, the first current decoding circuit 142 is connected to the first main control circuit 12, and the first voltage decoding circuit 141 and the first current decoding circuit 142 are configured to generate or receive an identification code, which is used to identify a key ID.
Fig. 9 is a circuit diagram of the first voltage decoding circuit 141 in this embodiment, and the first voltage decoding circuit 141 includes: diode D5, resistor R43, resistor R44, resistor R4, resistor R42, capacitor C26, capacitor C22, resistor R20, capacitor C28, capacitor C30, diode D6, diode D7, resistor R45, resistor R47, capacitor C27, capacitor C16, resistor R25, resistor R48, resistor R36, resistor R22, capacitor C22, and capacitor C22, wherein the anode of diode D22 is connected to the voltage terminal VPP, the cathode of diode D22 is connected to the first terminal of resistor R22, the second terminal of resistor R22 is connected to ground, the first terminal of capacitor C22 is connected to the voltage terminal VPP, the second terminal of capacitor C22 is connected to ground, the second terminal of resistor R22 is connected to the second terminal of resistor R22, and the second terminal of resistor R22 is connected to the second terminal of capacitor C22, a second terminal of the capacitor C22 is grounded, a first terminal of the resistor R20 is connected to a second terminal of the resistor R43, a second terminal of the resistor R20 is connected to a first terminal of the large capacitor C28, a second terminal of the capacitor C28 is grounded, a first terminal of the capacitor C30 is connected to a second terminal of the resistor R20, a second terminal of the capacitor C30 is connected to a first terminal of the resistor R45, a second terminal of the resistor R45 is connected to the first terminal of the capacitor C45, a second terminal of the capacitor C45 is grounded, a cathode of the diode D45 is connected to the voltage terminal VMCU, an anode of the diode D45 is connected to a cathode of the diode D45, an anode of the diode D45 is connected to a first terminal of the capacitor C45, a second terminal of the capacitor C45 is connected to a first terminal of the resistor R45, a second terminal of the resistor R45 is connected to the first terminal of the resistor R45, and the second terminal of the resistor R45 are connected to the first terminal of the resistor R36, the first end of the capacitor C25 is connected to the second end of the resistor R36, the second end of the capacitor C25 is grounded, the first end of the capacitor C32 is connected to the second end of the resistor R22, the second end of the capacitor C32 is grounded, the first end of the capacitor C13 is connected to the second end of the resistor R23, and the second end of the capacitor C13 is grounded.
Fig. 10 is a circuit diagram of the first current decoding circuit 142 in the present embodiment, in which the first current decoding circuit 142 includes: a resistor R30, a resistor R31, a capacitor C29, a resistor R46, a resistor R34, a resistor R18, a resistor R19, a capacitor C24, a capacitor C31 and a capacitor C12, wherein a second end of the resistor R30 is connected to a first end of the capacitor C29, a second end of the capacitor C29 is grounded, a second end of the resistor R29 is connected to a first end of the resistor R29, a second end of the resistor R29 is connected to first ends of the resistor R29 and the resistor R29, a first end of the capacitor C29 is connected to a second end of the resistor R29, a second end of the capacitor C29 is grounded, a first end of the capacitor C29 is connected to a second end of the resistor R29, and a second end of the capacitor C29 is grounded.
The detection circuit 15 comprises a battery voltage detection circuit 151, a PCB temperature detection circuit 152 and a 9V input voltage detection circuit 153, wherein the battery voltage detection circuit 151 is connected with the first main control circuit 12 and is used for detecting whether the battery voltage is stable; the PCB temperature detection circuit 152 is connected to the first main control circuit 12, and is configured to detect a PCB temperature of the circuit; the 9V input voltage detection circuit 153 is connected to the first main control circuit 12, and is configured to detect whether the voltage of the wireless transmission circuit reaches 9V.
Fig. 11 is a circuit diagram of the battery voltage detection circuit 151 in the present embodiment, and the battery voltage detection circuit 151 includes: a resistor R53 and a resistor R54, a first end of the resistor R53 is connected to the battery, a second end of the resistor R53 is connected to a first end of the resistor R54, a second end of the resistor R54 is grounded, and P36 is a voltage detection endpoint.
Fig. 12 is a circuit diagram of the PCB temperature detecting circuit 152 in the present embodiment, wherein the PCB temperature detecting circuit 152 includes: the sensor RT-type sensor comprises a sensor RT1, a capacitor C14 and a resistor R24, wherein a first end of the capacitor C14 is connected to a first end of the sensor RT1, a second end of the capacitor C14 is grounded, a first end of the resistor R24 is connected to a first end of the sensor RT1, and a second end of the resistor R24 is grounded.
Fig. 13 is a circuit diagram of the 9V input voltage detection circuit 153 in this embodiment, where the 9V input voltage detection circuit 153 includes a resistor R1, a resistor R2, and a capacitor C6, a first end of the resistor R1 is connected to the voltage terminal 9V, a second end of the resistor R1 is connected to a first end of the resistor R2, a second end of the resistor R2 is grounded, a first end of the capacitor C6 is connected to a second end of the resistor R1, and a second end of the capacitor C6 is grounded.
The door lock 2 is used for generating induction current according to the electromagnetic field and driving an internal motor of the door lock 2 to close or open the door lock 2 through the induction current. The door lock 2 includes: wireless receiving circuit 21, second master control circuit 22, motor drive circuit 23, decode and send a yard circuit 24 and position detection circuit 25, wireless receiving circuit 21 with second master control circuit 22 is connected, motor drive circuit 23 with second master control circuit 22 is connected, decode and send a yard circuit 24 with second master control circuit 22 is connected, position detection circuit 25 with second master control circuit 22 is connected.
The wireless receiving circuit 21 comprises a first wireless receiving circuit 211, a 3.3V voltage reducing circuit 212 and a 5V voltage reducing circuit 213, wherein the first wireless receiving circuit 211 is used for inducing the electromagnetic field and generating induction current; the 3.3V step-down circuit 212 is connected to the first wireless receiving circuit 211, and is configured to reduce an induced voltage corresponding to the induced current to 3.3V and provide the reduced induced voltage to the motor driving circuit 23; the 5V step-down circuit 213 is connected to the first wireless receiving circuit 211, and is configured to reduce the induced voltage corresponding to the induced current to 5V and provide the reduced induced voltage to the second main control circuit 22.
Fig. 14 is a circuit diagram of the first wireless receiving circuit 211 in this embodiment, and the first wireless receiving circuit 211 includes: a receiving coil L1, a capacitor C10, a diode D10, a capacitor C10, a resistor R10, a MOS transistor Q10, a capacitor C10, a resistor R10, a MOS transistor Q10 and a resistor R10, first terminals of the capacitor C10 and the capacitor C10 are connected to a first terminal of the receiving coil L10, second terminals of the capacitor C10 and the capacitor C10 are connected to a second terminal of the receiving coil L10, first terminals of the capacitor C10, the capacitor C10 and the capacitor C10 are connected to the first terminal of the capacitor C10, second terminals of the capacitor C10, the capacitor C10 and the diode D10 are connected to a cathode of the capacitor C10, a cathode of the capacitor C10 and a diode D10, a cathode of the capacitor C10 is connected to a diode C10, a cathode of the capacitor C10 and a diode D10, the anodes of the diode D3 and the diode D4 are connected to the second end of the capacitor C8, the first end of the capacitor C7 is connected to the first end of the capacitor C8, the first end of the capacitor C7 is connected to the second end of the capacitor C8, the first end of the resistor R4 is connected to the first end of the capacitor C7, the second end of the resistor R4 is connected to the first end of the resistor R8, the second end of the resistor R8 is grounded, the resistor R2 is connected to the first end of the MOS transistor Q1, the second end of the resistor R2 is connected to the first end of the resistor R6, the second end of the resistor R6 is connected to the first end of the MOS transistor Q2, the second end of the MOS transistor Q2 is connected to the first end of the resistor R9, the third end of the MOS transistor Q2 is grounded, the first ends of the capacitor C6 and the capacitor C6 are connected to the second end of the MOS transistor Q.
Fig. 15 is a circuit diagram of the 3.3V step-down circuit 212 in the present embodiment, where the 3.3V step-down circuit 212 includes: chip IC1, capacitor C3, capacitor C1, resistor R1, resistor R3, resistor R5, capacitor C12, resistor R7, resistor R10, inductor LR1, capacitor C16, capacitor C17 and capacitor C15, a first terminal of capacitor C3 is connected to pin 1 of chip IC1, a second terminal of capacitor C3 is connected to a first terminal of inductor LR1, a second terminal of inductor LR1 is connected to capacitors C15, C16 and a first terminal of capacitor C17, second terminals of capacitors C15, C16 and C17 are grounded, a first terminal of capacitor C1 is connected to pin 1 of chip IC1, a second terminal of capacitor C1 is connected to a first terminal of resistor R1, a second terminal of resistor R1 is connected to voltage terminal VPP, a first terminal of resistor R1 is connected to a second terminal of resistor R1, a second terminal of resistor R1 is connected to pin 1, the second terminal of the capacitor C12 is connected to the second terminal of the resistor R7, the first terminal of the resistor R10 is connected to the first terminal of the resistor R7, and the second terminal of the resistor R10 is connected to the second terminal of the inductor LR 1.
Fig. 16 is a circuit diagram of the 5V step-down circuit 213 in this embodiment, and the 5V step-down circuit 213 includes: diode D5, electric capacity C22, chip U1 and electric capacity C21, the positive pole of diode D5 is connected to voltage end DCIN, and the negative pole of diode D5 is connected to the first end of electric capacity C22, and the second end of electric capacity C22 ground, and the first end of electric capacity C21 is connected to 2 nd pin of chip U1, and the second end of electric capacity C21 ground.
Fig. 17 is a circuit diagram of the second master control module 22 in this embodiment, in which the second master control module 22 includes a chip U4, and the chip U4 is an MCU, and may be replaced with a chip such as a CPU in an alternative embodiment.
Fig. 18 is a circuit diagram of the motor driving circuit 23 in the present embodiment, and the motor driving circuit 23 includes: the motor comprises a chip U3, a capacitor C25, a motor M1, a resistor R19, a resistor R21, a resistor R28 and a resistor R29, wherein a first end of the capacitor C25 is connected to a voltage terminal DC, a second end of the capacitor C25 is connected to a 1 st pin of the chip U3, a first end of the motor M1 is connected to a 4 th pin of the chip U3, a second end of the motor M1 is connected to a 2 nd pin of the chip U3, a first end of the resistor R21 is grounded, a second end of the resistor R21 is connected to a first end of the resistor R19, a second end of the resistor R19 is connected to a first end of the capacitor C27, a second end of the capacitor C27 is grounded, a first end of the resistor R28 is grounded, and a second end of the resistor R28 is connected.
The decoding and code sending circuit 24 includes a second voltage decoding circuit 241 and a code sending circuit 242, the voltage decoding circuit 241 is connected to the second main control circuit 22 for receiving and analyzing the identification code, and the code sending circuit 242 and the second main control circuit 22 are used for generating the identification code.
Fig. 19 is a circuit diagram of the second voltage decoding circuit 241 in this embodiment, and the second voltage decoding circuit 241 includes: a resistor 27, a diode D6, a resistor R24, a resistor R31, a resistor R22, a capacitor C31, a capacitor C32, a capacitor C28, a resistor R20, a capacitor C26, a resistor R30, a capacitor C29, a resistor R23, a capacitor C30, a capacitor C35, a resistor R32, a resistor R33, a resistor R25, a resistor R26, a resistor R34, a capacitor C33, a first end of the resistor R33 is connected to a voltage terminal V back, a second end of the resistor R33 is connected to an anode of the diode D33, a cathode of the diode D33 is connected to a first end of the resistor R33, a second end of the resistor R33 is connected to a cathode of the diode D33, a second end of the resistor R33 is connected to a first end of the capacitor C33, a second end of the capacitor C33 is connected to a ground, a second end of the resistor R33 is connected to a second end of the capacitor C33, a second end of the resistor R33 is connected to a capacitor C, a second end of the capacitor C26 is grounded, a first end of the resistor R30 is connected to a first end of the resistor R20, a second end of the resistor R30 is connected to a first end of the capacitor C29, a second end of the capacitor C362 is connected to a first end of the resistor R23, a second end of the resistor R23 is connected to a first end of the capacitor C30, a second end of the capacitor C30 is connected to a first end of the capacitor C35, a second end of the capacitor C35 is connected to a first end of the resistor R32, a second end of the resistor R32 is connected to a first end of the capacitor R32, a second end of the capacitor C32 is grounded, a first end of the resistor R32 is connected to a second end of the resistor R3669572, a second end of the resistor R32 is connected to a first end of the capacitor C32, a second end of the resistor R32 is connected to a second end of the capacitor C32, the second terminal of the capacitor C36 is connected to ground.
Fig. 20 is a circuit diagram of the code transmitting circuit 242 in the present embodiment, and the code transmitting circuit 242 includes: capacitor C19, MOS transistor Q3, resistor R12, resistor R42, capacitor C20, MOS transistor Q4, resistor R13, the first end of capacitor C19 is connected to the first end of MOS transistor Q3, the second end of MOS transistor Q3 is connected to the first end of resistor R12, the second end of resistor R12 is connected to the first end of resistor R42, the second end of resistor R42 is grounded, the first end of capacitor C20 is connected to the first end of MOS transistor Q4, and the second end of MOS transistor Q4 is connected to the first end of resistor R13.
Fig. 21 is a circuit diagram of the position detection circuit 25 in the present embodiment, and the position detection circuit 25 includes: the LED driving circuit comprises a resistor R16, an LED U4, a resistor R17, a resistor R40, an LED U5 and a resistor R41, wherein a first end of a resistor R16 is connected to a voltage end VDD, a second end of a resistor R16 is connected to a first end of an LED U4, a second end of an LED U4 is connected to a first end of a resistor R17, a second end of a resistor R17 is connected to a voltage end 3.3V, a first end of a resistor R40 is connected to the voltage end VDD, a second end of a resistor R40 is connected to a first end of an LED U5, a second end of an LED U5 is connected to a first end of a resistor R41, and a second end of a resistor R41 is connected to the voltage end 3.3V.
The embodiment discloses an electromagnetic induction's lock and key, includes: the key is used for generating an electromagnetic field according to an unlocking signal or a locking signal; and the door lock is used for generating induction current according to the electromagnetic field and closing or opening the door lock through the induction current. According to the electromagnetic induction door lock and the electromagnetic induction key, the electric drive is arranged in the door lock, so that the condition that power supply voltage is supplied from the outside of the door lock is avoided, the problems that the safety is low and the door lock is easy to crack due to the fact that the power supply voltage is supplied from the outside to the door lock in the prior art are solved, the effects of safely unlocking and safely locking are achieved, and the user experience is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.