CN112182491A - Walsh-adama conversion device based on memristor array - Google Patents
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Abstract
The invention discloses a Walsh-adam conversion device based on a memristor array, belongs to the field of microelectronic devices and circuits, and comprises a processor and at least one circuit structure which are connected. The processor is used for mapping elements in the binary matrix F into a voltage matrix and splitting the equal-dimension Aldamard matrix H into HAAnd HB(ii) a Each circuit structure includes: two memristor arrays, respectively for writing HAAnd HB(ii) a Respectively applying the input voltage matrix to word lines of the two memristor arrays; the plurality of subtracters are connected with the two memristor arrays and used for subtracting the currents read from the tail ends of the two memristor arrays to obtain a current matrix; when a plurality of circuit structures exist, the voltage matrix corresponding to the output current matrix of the previous circuit structure is used as the input voltage of the next circuit structure, and the processor acquires target transformation based on the current matrix output by the last circuit structureAnd a matrix W. The method and the device can improve the calculation efficiency, reduce the energy consumption and reduce the time delay.
Description
Technical Field
The invention belongs to the field of microelectronic devices and circuits, and particularly relates to a Walsh-adama transformation device based on a memristor array.
Background
The Walsh-adama transform is a generalized Fourier transform, the orthogonal basis of the Walsh-adama transform has more concise operation property, the Walsh-adama transform is a typical non-sinusoidal function transform, a square wave function is taken as a basis function, operation elements are only-1 and 1, the Walsh-adama transform has more important application in rapid spectrum analysis, and the Walsh-adama transform has incomparable advantages with other transforms as a spectrum method for solving equations.
However, in high-dimensional signal processing, the size of a matrix to be processed is large, a large amount of data is moved in the operation process of a processor, so that the calculation power consumption is large, the time delay is serious, the hardware overhead of parallel calculation is extremely high, and the circuit size is large. Particularly, in mobile communication, it is not in line with the requirements of low power consumption and miniaturization of portable devices.
Disclosure of Invention
In view of the above defects or improvement requirements of the prior art, the present invention provides a walsh-hadamard transform apparatus based on memristor arrays, which aims to improve the computational efficiency of walsh-hadamard transforms in the high-dimensional signal processing process, thereby solving the technical problems of large computational power consumption, serious delay and large hardware references in the corresponding processor operation process.
To achieve the above object, according to an aspect of the present invention, there is provided a walsh-hadamard transform device based on a memristor array, including:
a processor for converting Vx 2WMapping elements in the dimension binary matrix F to high and low levels to obtain a corresponding voltage matrix, and constructing 2W×2WThe hadamard matrix H is split into a differential matrix HAAnd HB；
At least one circuit structure coupled to the processor, each circuit structure comprising:
two memristor arrays respectively for writing into the differential matrix HAAnd HB(ii) a Then applying the input voltages to the differential matrix HAAnd HBOn a word line of a corresponding memristor array;
the subtractors are connected with the two memristor arrays and used for subtracting the currents read from the tail ends of the two memristor arrays to output a current matrix;
when the circuit structure is one, the input voltage is a voltage matrix corresponding to the matrix F to be processed, and the processor is further used for acquiring a target transformation matrix W of the Walsh-adam transformation based on a current matrix output by the circuit structure;
when the number of the circuit structures is at least two, the at least two circuit structures are sequentially connected, the input voltages of two memristor arrays in the first circuit structure are voltage matrixes corresponding to the matrix F to be processed, the input voltages of the two memristor arrays in the rest circuit structures are voltage matrixes corresponding to current matrixes output by subtracters in the adjacent previous circuit structure, and the processor is further used for obtaining the target transformation matrix W based on the output current matrixes in the last voltage structure.
In one embodiment, when the apparatus is used for performing one-dimensional hadamard forward transformation, the processor is further configured to multiply a voltage matrix corresponding to a current matrix output by the first circuit structure by a first preset coefficient a to obtain the target transformation matrix W; wherein the first preset coefficient a is 1/2W。
In one embodiment, when the apparatus is configured to perform a one-dimensional hadamard inverse transformation, the processor is further configured to use a voltage matrix corresponding to a current matrix output by the first circuit structure as the target transformation matrix W.
In one embodiment, when the matrix to be processed F is a speech vector, the processor is configured to treat the target transformation matrix W as a compressed vector of the speech vector;
and when the matrix F to be processed is a voice compression vector, the processor is used for regarding the target transformation matrix W as a reconstruction vector of the voice compression vector.
In one embodiment, when the apparatus is used to perform a binary field mxn dimensional homogeneous equation solution,
the processor is further configured to obtain a coefficient matrix M of the homogeneous equation, and convert the M row vectors into M decimal numbers MiTo construct aBinary row vectors, each m-th of the binary row vectorsiSetting +1 elements as 1 and the rest as 0, and taking the binary row vector as the matrix F to be processed;
the device further comprises: and the encoder is connected with the output end of the subtracter in the first circuit structure and is used for sequentially accessing all elements except the first bit in the voltage sequence corresponding to the target transformation matrix W and outputting a solution sequence, wherein the solution sequence is a non-trivial solution of the homogeneous equation.
In one embodiment, when the apparatus performs two-dimensional hadamard forward transformation, the processor is further configured to multiply a voltage matrix corresponding to a current matrix output by the second circuit structure by a second preset coefficient a to obtain the target transformation matrix W; wherein the second predetermined coefficient a is 1/22W。
In one embodiment, when the apparatus performs the two-dimensional hadamard inverse transformation, the processor is further configured to take a voltage matrix corresponding to a current matrix output by the second circuit structure as the target transformation matrix W.
In one embodiment, when the matrix to be processed F is an image matrix, the processor is configured to treat the target transformation matrix W as a compression matrix of the image matrix;
and when the matrix F to be processed is an image compression matrix, the processor is used for regarding the target transformation matrix W as a reconstruction matrix of the image compression matrix.
In one embodiment, the structure of the memristor array is a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure.
In one embodiment, the memristor in the memristor array is a resistive random access memory, a phase change memory, a self-selection transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
1. the Walsh-adama transformation device based on the memristor array is used for Walsh-adama transformation, matrix elements are stored in the memristor array in a resistance mode in the calculation process, a large amount of data do not need to be moved back and forth in a memory and an arithmetic unit, energy consumption can be reduced, time delay can be reduced, compared with the method of using the CPU and other prior art for transformation, the calculation time can be greatly shortened, and the calculation efficiency can be improved;
2. because the same differential matrix is used for the forward transformation and the inverse transformation corresponding to the Walsh-adama, the differential matrix corresponding to the adama matrix is stored in the memristor array without erasing and writing, and can be repeatedly used, and further, the calculation efficiency can be improved and the hardware cost can be reduced;
3. homogeneous equation solution can be rapidly realized by utilizing one-dimensional Walsh-adama forward transform;
4. the image compression can be realized by utilizing two-dimensional Walsh-adam forward transform, and the image reconstruction can be realized by utilizing two-dimensional Walsh-adam inverse transform.
Drawings
FIG. 1 is a schematic structural diagram of a one-dimensional Walsh-adam transformation device based on a memristor array in an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a two-dimensional Walsh-adam transform device based on a memristor array in an embodiment of the present application;
FIG. 3 is a flow chart of a one-dimensional Walsh-adama transformation device based on a memristor array for solving equations thereof in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a signal processing system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The application provides a Walsh-adama conversion device based on memristor array, includes: a processor and at least one circuit arrangement, wherein the processor is configured to convert Vx 2WMapping elements in the dimension binary matrix F to high and low levels to obtain a corresponding voltage matrix, and constructing 2W×2WThe Aldamard matrix H is split into a differential matrix HAAnd HB(ii) a At least one circuit structure is coupled to the processor. Each circuit structure includes: two memristor arrays and 2WA subtractor, wherein two memristor arrays are respectively used for writing into the differential matrix HAAnd HB(ii) a Then, the input voltages are applied to the differential matrix HAAnd HBOn a word line of a corresponding memristor array; 2WAnd the subtracter is connected with the two memristor arrays and is used for subtracting the current read from the tail ends of the two memristor arrays to output a current matrix.
It should be noted that the element in the matrix F to be processed is 0 or 1, and the dimension thereof is V × 2WV is an integer greater than or equal to 1, and W is an integer greater than or equal to 0, i.e., the processing matrix F may be a row vector or a matrix composed of a plurality of row vectors. The voltage matrix corresponding to the matrix F to be processed means that the element 1 in the matrix F to be processed is mapped to a high level, and the element 0 in the matrix F to be processed is mapped to a low level, so that the voltage matrix corresponding to F can be obtained. The dimension of the hadamard matrix H is 2W×2WI.e. the pending matrix F can be multiplied by the hadamard matrix H. Splitting the hadamard matrix H into a difference matrix HAAnd HBI.e. H ═ HA-HBTake 4 × 4 as an example, as shown in the formula
That is, element 1 in the hadamard matrix is converted into 1 and 0 respectively as HAAnd HBThe element-1 in the hadamard matrix is multiplied by 0 and 1 as HAAnd HBOf corresponding position inAnd (4) elements. Writing a differential matrix H in two memristor arraysAAnd HBMeans when HAAnd HBThe memristor array corresponding to the medium element of 1 is written into the high resistance state when the H isAAnd HBThe memristor array corresponding to the middle element of 0 is written into a low resistance state.
When the circuit structure is one, the input voltage is a voltage matrix corresponding to the matrix F to be processed, and the processor is further used for acquiring a target transformation matrix W of Walsh-adam transformation based on the current matrix output by the circuit structure.
Specifically, when the Walsh-adam transformation device based on the memristor array only comprises one circuit structure, one-dimensional Walsh-adam forward transformation and Walsh-adam inverse transformation can be carried out. The structure is shown in fig. 1, a processor obtains a matrix F to be processed corresponding to row vectors, maps the matrix F to be processed into a voltage matrix, and then respectively sends H signals to H by using the voltage matrixACorresponding memristor array and HBAnd inputting the current sequences at the tail ends of the two memristor arrays to the subtracter according to the corresponding bit to obtain a current matrix. In one embodiment, when the device is used for one-dimensional hadamard forward transformation, the processor is further used for multiplying a voltage matrix corresponding to a current matrix output by the first circuit structure by a first preset coefficient a to obtain a target transformation matrix W; wherein the first predetermined coefficient a is 1/2W. In another embodiment, when the apparatus is configured to perform a one-dimensional hadamard inverse transformation, the processor is further configured to use a voltage matrix corresponding to the current matrix output by the first circuit configuration as the target transformation matrix W.
In addition, when the Walsh-adama transformation device based on the memristor array only comprises one circuit structure, the device can be used for compressing and reconstructing a one-dimensional signal, and in one embodiment, when the matrix F to be processed is a voice vector, the processor is used for regarding the target transformation matrix W as a compressed vector of the voice vector; when the matrix F to be processed is a voice compression vector, the processor is used for regarding the target transformation matrix W as a reconstruction vector of the voice compression vector.
When the number of the circuit structures is at least two, the at least two circuit structures are sequentially connected, the input voltages of the two memristor arrays in the first circuit structure are voltage matrixes corresponding to the matrix F to be processed, the input voltages of the two memristor arrays in the rest circuit structures are voltage matrixes corresponding to current matrixes output by the subtractors in the adjacent previous circuit structures, and the processor is further used for obtaining a target transformation matrix W based on the output current matrixes in the last voltage structure.
Specifically, when the walsh-adam transformation device based on the memristor array only comprises C circuit structures, the walsh-adam transformation device based on the memristor array can perform C-dimensional walsh-adam forward transformation and walsh-adam inverse, and C is a positive integer greater than 1. For example, when C is 2, fig. 2 is a structural schematic diagram of a two-dimensional memristor array-based walsh-hadamard transform device. The device comprises two circuit structures which are connected in sequence, wherein a current matrix output by a subtracter in the first circuit structure is used as an input voltage matrix in a memristor array in the second circuit structure. And after the operation is completed in the second circuit structure, transmitting the output current matrix of the subtracter in the second circuit structure to a processor, converting the current matrix into a corresponding voltage matrix by the processor, and then obtaining a target conversion matrix based on the voltage matrix. In one embodiment, when the device performs two-dimensional hadamard forward transformation, the processor is further configured to multiply a voltage matrix corresponding to a current matrix output by the second circuit structure by a second preset coefficient a to obtain a target transformation matrix W; wherein the second predetermined coefficient a is 1/(2)W)2. In one embodiment, when the apparatus performs the two-dimensional hadamard inverse transformation, the processor is further configured to take a voltage matrix corresponding to the current matrix output by the second circuit configuration as the target transformation matrix W.
In addition, when the Walsh-adama transformation device based on the memristor array only comprises two circuit structures, the device can be used for compressing and reconstructing two-dimensional signals, such as image signals. In one embodiment, when the matrix F to be processed is an image matrix, the processor is configured to treat the target transformation matrix W as a compression matrix of the image matrix; and when the matrix F to be processed is an image compression matrix, the processor is used for regarding the target transformation matrix W as a reconstruction matrix of the image compression matrix.
In one embodiment, when the apparatus is configured to perform a solution of a homogeneous equation in a binary domain of mxn dimensions, the processor is further configured to obtain a coefficient matrix M of the homogeneous equation, convert the M row vectors into M decimal numbers MiConstructing a binary row vector, each m-th row vector in the binary row vectoriSetting +1 elements as 1 and the rest as 0, and taking the binary row vector as a matrix F to be processed; the device still includes: and the encoder is connected with the output end of the subtracter in the first circuit structure and is used for sequentially accessing all elements except the first bit in the voltage sequence corresponding to the target transformation matrix W and outputting a solution sequence, wherein the solution sequence is a non-trivial solution of the quadratic equation.
For example, as shown in FIG. 3, the process of solving a homogeneous system of linear equations for the binary domain is as follows:
s1, converting the row vectors of the coefficient matrix of the homogeneous equation into decimal numbers 0 and 3;
s2, since the dimension of the homogeneous equation is 2 x 2, a 1 x 2 is constructed2And setting the 1 st element and the 4 th element in the row vector V to be 1 and setting the rest to be 0 to obtain V ═ 1001](ii) a Wherein, the row vector V is a matrix F to be processed;
s3, construction of 22Aldamard matrix of order H4And the memristor array is split into two differential matrixes through disassembly, the two differential matrixes are written into the memristor array, 0 is a high-resistance state, and 1 is a low-resistance state:
s4, converting the pending matrix F to [1001] into a corresponding voltage sequence, where 1 is high and 0 is low, and applying the voltage sequence to the word lines of the two arrays respectively; as shown in fig. 1.
And S5, converting the current sequence output by the subtracter into a voltage sequence, discarding the first voltage signal, connecting the last three voltage signals to the high 3 bits of a 4-2 encoder, grounding the lowest bit, and finally outputting the encoder as [11], namely the non-trivial solution of the equation.
In one embodiment, the structure of the memristor array is a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure.
In one embodiment, the memristor in the memristor array is a resistive random access memory, a phase change memory, a self-selection transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.
In one embodiment, as shown in fig. 4, the present application further provides a signal processing system, which includes a walsh-hadamard transform device based on a memristor array, connected to an external circuit module, and including a signal acquisition system, a preprocessing algorithm, a read-write and control circuit, and an analog-to-digital/digital-to-analog converter around a computation core. The signal acquisition system can acquire acoustic, optical, electric and other signals and transmit the signals to the computing core. The calculation core analyzes signal data based on an algorithm in a Walsh-adama conversion device based on a memristor array, measures the dimensionality of a signal and the like, and then transmits the signal data to the read-write/control circuit, and the read-write/control circuit presets the calculation core according to the relevant characteristics of the signal. For example, writing a transformation matrix, etc., after the computation is approved, inputting the preprocessed signals into a computation core, and performing post-processing, such as calibration, etc., on the obtained results by an auxiliary algorithm, and finally storing the results.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A walsh-hadamard transform device based on memristor arrays, comprising:
a processor for converting Vx 2WMapping elements in the dimension binary matrix F to high and low levels to obtain a corresponding voltage matrix, and constructing 2W×2WA dimensional hadamard matrix H, splitting the hadamard matrix H into a difference matrix HAAnd HB；
At least one circuit structure coupled to the processor, each circuit structure comprising:
two memristor arrays respectively for writing into the differential matrix HAAnd HB(ii) a Then applying the input voltages to the differential matrix HAAnd HBOn a word line of a corresponding memristor array;
the subtractors are connected with the two memristor arrays and used for subtracting the currents read from the tail ends of the two memristor arrays to output a current matrix;
when the circuit structure is one, the input voltage is a voltage matrix corresponding to the matrix F to be processed, and the processor is further used for acquiring a target transformation matrix W of the Walsh-adam transformation based on a current matrix output by the circuit structure;
when the number of the circuit structures is at least two, the at least two circuit structures are sequentially connected, the input voltages of two memristor arrays in the first circuit structure are voltage matrixes corresponding to the matrix F to be processed, the input voltages of the two memristor arrays in the rest circuit structures are voltage matrixes corresponding to current matrixes output by subtractors in the adjacent previous circuit structure, and the processor is further used for obtaining the target transformation matrix W based on the output current matrixes in the last voltage structure.
2. The apparatus of claim 1, wherein when the apparatus is configured to perform a one-dimensional hadamard forward transform, the processor is further configured to multiply a voltage matrix corresponding to a current matrix output by the first circuit structure by a first preset coefficient a to obtain the target transform matrix W; wherein the first preset coefficient a is 1/2W。
3. The apparatus of claim 2, wherein the processor is further configured to use a voltage matrix corresponding to a current matrix output by the first circuit structure as the target transform matrix W when the apparatus is configured to perform a one-dimensional inverse hadamard transform.
4. The apparatus of claim 3,
when the matrix F to be processed is a voice vector, the processor is used for regarding the target transformation matrix W as a compressed vector of the voice vector;
and when the matrix F to be processed is a voice compression vector, the processor is used for regarding the target transformation matrix W as a reconstruction vector of the voice compression vector.
5. The apparatus of claim 2, wherein when the apparatus is used to perform a binary domain MxN dimensional homogeneous equation solution,
the processor is further configured to obtain a coefficient matrix M of the homogeneous equation, and convert the M row vectors into M decimal numbers MiConstructing a binary row vector, each m-th row vector in the binary row vectoriSetting +1 elements as 1 and the rest as 0, and taking the binary row vector as the matrix F to be processed;
the device further comprises: and the encoder is connected with the output end of the subtracter in the first circuit structure and is used for sequentially accessing all elements except the first bit in the voltage sequence corresponding to the target transformation matrix W and outputting a solution sequence, wherein the solution sequence is a non-trivial solution of the homogeneous equation.
6. The apparatus of claim 1, wherein when the apparatus performs a two-dimensional hadamard forward transform, the processor is further configured to multiply a voltage matrix corresponding to a current matrix output by the second circuit structure by a second predetermined coefficient a to obtain the target transform matrix W; wherein the second predetermined coefficient a is 1/22W。
7. The apparatus of claim 6, wherein the processor is further configured to use a voltage matrix corresponding to a current matrix output by the second circuit arrangement as the target transform matrix W when the apparatus performs a two-dimensional Hadamard inverse transform.
8. The apparatus of claim 7,
when the matrix F to be processed is an image matrix, the processor is used for regarding the target transformation matrix W as a compression matrix of the image matrix;
and when the matrix F to be processed is an image compression matrix, the processor is used for regarding the target transformation matrix W as a reconstruction matrix of the image compression matrix.
9. The apparatus of any of claims 1-8, in which the structure of the memristor array is a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure.
10. The apparatus of any one of claims 1-8, wherein the memristor in the memristor array is a resistive random access memory, a phase change memory, a free transfer torque-magnetic random access memory, a NOR Flash device, or a NAND Flash device.
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