CN112181495B - Method and device for realizing operand instruction of predicate register - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Abstract
The invention discloses a method and a device for realizing a predicate register operand instruction, wherein the method for realizing the predicate register operand instruction comprises the steps of decoding a microprocessor instruction; judging whether the instruction is an operand assertion instruction according to the decoding result of the microprocessor instruction, if so, sending the operand assertion instruction to an integer execution unit for processing, wherein the processing process comprises control signal decoding and source operand acquisition of the operand assertion instruction, and operand assertion calculation; and writing back the result after the execution is finished. The invention designs the execution method and the hardware device for the interrupt language register operand instruction of the microprocessor, reuses the data path of the integer execution part of the existing microprocessor, and reduces the design complexity and the realization cost.
Description
Technical Field
The invention relates to an instruction implementation technology of a microprocessor, in particular to an implementation method and device for a predicate register operand instruction.
Background
Vector processing is one of the main forms of data processing currently performed by microprocessors. At present, mainstream microprocessor manufacturers propose vector processing instructions and processors for the high-performance computing field. Such as: the Intel corporation introduced the advanced vector processing instruction set AVX-512 in 2016, and is currently mainly used in server products such as Xeon Phi; AMD company released an extended instruction set SSE5 based on an x86 architecture in the previous year, which is mainly used for enhancing the high-performance computing capability of AMD company; the ARM company successively and respectively promotes the Neon instruction set and the SVE instruction set, thereby accelerating the pace of high-performance calculation of marching.
Assertion-based vector element processing is a flexible vector processing mode and is widely applied to vector processing technology of microprocessors. Taking the SVE instruction set of ARM as an example, for a vector register length of VL, a predicate register bit width is defined as PL = VL/8, and each binary bit of the predicate register corresponds to each byte of the vector register. The vector register contains a plurality of vector elements, each element being 8 bits, 16 bits, 32 bits and 64 bits wide, and correspondingly the predicate register contains a plurality of predicate elements, each element being 1 bit, 2 bits, 4 bits and 16 bits wide corresponding to the vector element. In order to support the new data type of the predicate register and the instruction execution related to the predicate register operand, the existing processor needs to add a data path and a corresponding predicate register operand execution unit, and therefore the problems of complex design and high implementation cost are faced.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a method and a device for realizing a predicate register operand instruction, which reduce the design complexity and the realization cost by multiplexing the data path of the integer execution unit of the existing microprocessor.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method for implementing a predicate register operand instruction, the implementation steps comprising:
1) Decoding the microprocessor instruction;
2) Judging whether the microprocessor instruction is a predicate operand instruction according to the decoding result of the microprocessor instruction, and if the microprocessor instruction is the predicate operand instruction, jumping to execute the step 3); otherwise, processing other instructions, ending and exiting;
3) Performing control signal decoding on the assertion operand instruction and obtaining a source operand of the assertion operand instruction;
4) Performing assertion operand calculation and obtaining a calculation result;
5) Writing the calculation result of the predicate operand instruction into a corresponding destination register, and jumping to execute the step 1).
Optionally, the detailed steps of step 3) include:
3.1 According to the operation type and the calculation mode of the predicate register operand instruction, acquiring a control signal required by the instruction to execute, wherein the process is also called control signal decoding;
3.2 A source operand data path multiplexing existing integer components, adding a source operand data type field for distinguishing whether the source operand is an integer operand or a predicate register operand; judging according to the data type field of the source operand, if the source operand is an assertion register type operand, acquiring a corresponding assertion register operand from a bypass or assertion register file according to a data selection signal;
optionally, the detailed steps of step 4) include: sending a control signal and a source operand required by the execution of the predicate register operand instruction into a predicate operand calculation unit for execution, and obtaining a calculation result;
in addition, the present invention also provides an implementation apparatus for a predicate register operand instruction, comprising:
the instruction decoding control unit is used for decoding the microprocessor instruction, judging whether the microprocessor instruction is a predicate register operand instruction according to the decoding result of the microprocessor instruction, and sending the predicate register operand instruction to the integer component unit for execution if the predicate register operand instruction is the predicate register operand instruction;
the control signal decoding unit is used for acquiring a control signal required by instruction execution and registering;
a source operand obtaining unit, configured to obtain a source operand and register the source operand;
the predicate operand calculation unit is used for completing the execution process of the predicate register operation instruction and acquiring a calculation result;
optionally, the source operand obtaining unit includes:
a predicate register file read circuit for reading source operand data from the predicate register file as needed;
source operand selection circuitry to select correct source operand data from either the bypass data or the register file;
the source operand register unit is used for registering the finally obtained source operand so as to be used by the assertion operand calculation unit;
optionally, the predicate operand computation unit includes:
the assertion operand operation execution control circuit is used for controlling the execution processes of different types of assertion operands and ensuring the correctness of a final calculation result;
and the assertion operand operation execution circuit is used for processing the assertion operands, and comprises various types of assertion operations such as assertion bit splicing, active element counting, first assertion active element positioning and the like.
In addition, the invention also provides a device for realizing the predicate register operand instruction, which comprises a microprocessor supporting the predicate register operation, wherein the microprocessor is programmed or configured to execute the steps of the method for realizing the predicate register operand instruction.
Furthermore, the present invention also provides a computer device comprising a microprocessor supporting predicate register operations, the microprocessor being programmed or configured to perform steps of an implementation method of the predicate register operand instruction.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention avoids the new increase of the bypass of the operand data path of the interrupt register by multiplexing the integer execution part of the prior processor, and reduces the design complexity and the realization cost.
2. The invention can be suitable for the design of other relevant instructions in the processor and has the characteristics of wide application range and flexible and convenient use.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating control signal decoding and register source operand selection according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating the control signals, source operands of predicate registers, and the predicates calculation unit according to the embodiment of the present invention.
FIG. 4 is a block diagram of an apparatus according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the implementation steps of the implementation method of the predicate register operand instruction of the present embodiment include:
1) Decoding the microprocessor instruction;
2) Judging whether the microprocessor instruction is an operand predication instruction according to the decoding result of the microprocessor instruction, and if so, skipping to execute the step 3); otherwise, processing other instructions, ending and exiting;
3) Performing control signal decoding on the assertion operand instruction and obtaining a source operand of the assertion operand instruction;
4) Performing assertion operand calculation and obtaining a calculation result;
5) And writing the calculation result of the operand-predicated instruction into a corresponding destination register, and jumping to execute the step 1).
As shown in fig. 2, the detailed steps of step 3) include:
3.1 According to the operation type and calculation mode of the operand instruction of the predicate register, obtaining a control signal required by the instruction execution, thereby completing the decoding of the control signal;
3.2 A source operand data path multiplexing existing integer components, adding a source operand data type field for distinguishing whether the source operand is an integer operand or a predicate register operand; and if the source operand is an assertion register type operand, acquiring the corresponding assertion register operand from the bypass or assertion register file according to the data selection signal according to the judgment of the data type field of the source operand.
Fig. 3 is a schematic diagram illustrating the control signal, the source operand of the predicate register, and the source operand register are sent to the predicate operand calculation unit for execution according to the embodiment of the present invention, and as shown in fig. 3, the detailed steps of step 4) are: and sending a control signal and a source operand required by the execution of the predicate register operand instruction into a predicate operand calculation unit for execution, and obtaining a calculation result.
As shown in fig. 4, this embodiment further provides an apparatus for implementing a predicate register operand instruction, including:
the instruction decoding control unit is used for decoding the microprocessor instruction, judging whether the microprocessor instruction is a predicate register operand instruction according to the decoding result of the microprocessor instruction, and sending the predicate register operand instruction to the integer component unit for execution if the predicate register operand instruction is the predicate register operand instruction;
the control signal decoding unit is used for acquiring a control signal required by instruction execution and registering;
a source operand obtaining unit, configured to obtain a source operand and register the source operand;
and the predicate operand calculation unit is used for completing the execution process of the predicate register operation instruction and acquiring a calculation result.
Wherein, the source operand obtaining unit includes:
a predicate register file read circuit for reading source operand data from the predicate register file as needed;
source operand selection circuitry for selecting correct source operand data from either the bypass data or the register file;
and the source operand registering unit is used for registering the finally acquired source operand so as to be used by the predicate operand calculation unit.
Wherein the predicate operand calculation unit includes:
the assertion operand operation execution control circuit is used for controlling the execution processes of different types of assertion operands and ensuring the correctness of the final calculation result;
and the assertion operand operation execution circuit is used for processing the assertion operands, and comprises various types of assertion operations such as assertion bit splicing, active element counting, first assertion active element positioning and the like.
In addition, the present embodiment also provides an implementation apparatus of a predicate register operand instruction, including a microprocessor supporting predicate register operation, the microprocessor being programmed or configured to execute the steps of the implementation method of the predicate register operand instruction.
Furthermore, the present embodiment also provides a computer device comprising a microprocessor supporting predicate register operations, the microprocessor being programmed or configured to perform the steps of the method for implementing the predicate register operand instruction described above.
In summary, the present embodiment discloses a method and an apparatus for implementing a predicate register operand instruction, where the method for implementing a predicate register operand instruction of the present embodiment includes decoding a microprocessor instruction; judging whether the instruction is an operand assertion instruction according to the decoding result of the microprocessor instruction, if so, sending the operand assertion instruction to an integer execution unit for processing, wherein the processing process comprises control signal decoding and source operand acquisition of the operand assertion instruction, and an operand assertion calculation unit; and writing back the result after the execution is finished. The implementation method and the implementation device for the predicate register operand instruction in the embodiment design an execution method and a hardware device for the interrupt register operand instruction of the microprocessor, multiplex the data path of an integer execution unit of the existing microprocessor, and reduce the design complexity and the implementation cost.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is directed to methods, apparatus (systems), and computer program products according to embodiments of the application wherein instructions, which execute via a flowchart and/or a processor of the computer program product, create means for implementing functions specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (6)
1. A method for implementing a predicate register operand instruction, the method comprising:
1) Decoding the microprocessor instruction;
2) Judging whether the microprocessor instruction is a predicate register operand instruction according to the decoding result of the microprocessor instruction, and if the microprocessor instruction is the predicate register operand instruction, skipping to execute the step 3); otherwise, processing other instructions, ending and exiting; the predicate register operand instruction is an instruction used for calculating a source operand of the predicate register operand instruction through a predicate operand calculation unit, and the calculation comprises predicate bit splicing, active element counting and first predicate active element positioning multiple types of predicate operations;
3) Performing control signal decoding on the predicate register operand instruction and acquiring a source operand of the predicate register operand instruction;
4) Performing source operand calculation of a predicate register operand instruction and acquiring a calculation result;
5) Writing a calculation result of the predicate register operand instruction into a corresponding destination register, and jumping to execute the step 1);
the detailed steps of the step 3) comprise:
3.1 According to the operation type and calculation mode of the operand instruction of the predicate register, obtaining a control signal required by the instruction execution, thereby completing the decoding of the control signal;
3.2 A source operand data path multiplexing an existing integer execution unit, adding a source operand data type field for distinguishing whether the source operand is a source operand of the integer execution unit or a source operand of a predicate register operand instruction; and if the source operand is the source operand of the predicate register operand instruction according to the judgment of the data type field of the source operand, the source operand of the predicate register operand instruction is obtained from a source operand data path bypass of the integer execution unit according to the data selection signal, or the source operand of the corresponding predicate register operand instruction is obtained from the predicate register file.
2. The method for implementing a predicate register operand instruction according to claim 1, wherein the detailed step of step 4) is: and sending the control signal and the source operand required by the predicate register operand instruction to a predicate operand calculation unit for execution, and obtaining a calculation result.
3. An apparatus for implementing a predicate register operand instruction, comprising:
the instruction decoding control unit is used for decoding the microprocessor instruction, judging whether the microprocessor instruction is a predicate register operand instruction according to the decoding result of the microprocessor instruction, and sending the predicate register operand instruction to the predicate operand calculation unit for execution if the microprocessor instruction is the predicate register operand instruction; the predicate register operand instruction is an instruction used for processing a source operand of the predicate register operand instruction through a predicate operand calculation unit, and the processing comprises performing predicate bit splicing, active element counting and first predicate active element positioning multiple types of predicate operations;
the control signal decoding unit is used for acquiring a control signal required by instruction execution and registering;
a source operand obtaining unit, configured to obtain a source operand and register the source operand;
the predicate operand calculation unit is used for completing the execution process of the predicate register operation instruction and acquiring a calculation result;
the source operand acquisition unit includes:
a predicate register file read circuit to read source operand data from a predicate register file;
source operand selection circuitry to select correct source operand data from either the bypass data or the register file; the bypass data is from a source operand datapath of the multiplexed integer execution unit, and a source operand of the source operand datapath of the integer execution unit contains a source operand data type field to distinguish whether the source operand is a source operand of the integer execution unit or a source operand of the predicate register operand instruction;
and the source operand registering unit is used for registering the finally acquired source operand so as to be used by the predicate operand calculation unit.
4. The apparatus as in claim 3, wherein the predicate operand calculation unit comprises:
the assertion operand operation execution control circuit is used for controlling the execution processes of different types of assertion operands and ensuring the correctness of the final calculation result;
and the predicate operand operation execution circuit is used for processing the source operand of the predicate register operand instruction, and comprises a plurality of types of predicate operations of predicate bit splicing, active element counting and first predicate active element positioning.
5. An apparatus for implementing a predicate register operand instruction, comprising a microprocessor supporting predicate register operations, wherein the microprocessor is programmed or configured to perform the steps of a method for implementing the predicate register operand instruction of claim 1 or 2.
6. A computer device comprising a microprocessor supporting predicate register operations, wherein the microprocessor is programmed or configured to perform the steps of a method of implementing the predicate register operand instruction of claim 1 or 2.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110515656B (en) * | 2019-08-28 | 2021-07-16 | 中国人民解放军国防科技大学 | CASP instruction execution method, microprocessor and computer equipment |
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| CN104011650A (en) * | 2011-12-23 | 2014-08-27 | 英特尔公司 | Systems, apparatuses and methods for setting output mask in destination writemask register from source write mask resigter using input writemask and immediate |
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