CN1121696C

CN1121696C - Semiconductor memory device capable of realization stable test mode operation

Info

Publication number: CN1121696C
Application number: CN97115334A
Authority: CN
Inventors: 松冈秀人
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1997-08-04
Filing date: 1997-08-04
Publication date: 2003-09-17
Anticipated expiration: 2017-08-04
Also published as: CN1207559A

Abstract

The present invention relates to a semiconductor memory. In the usual operation, data is written in four selected memory units according to external write data DQ0 to DQ3 respectively supplied to four data input and output terminals; on the other hand, the same data is together written in the four selected memory units according to the write data DQ0 supplied to one data input and output terminal in an inspection mode. In the operation of the inspection mode, signal transmission among the other three data input and outlet terminals and corresponding input buffer circuits is cut off through CMOS logic gates which are arranged among the three data input and output terminals and the corresponding input buffer circuits and are controlled by specified signals/TE of the inspection mode.

Description

Can realize the semiconductor memory of stable check system operation

Technical field

The present invention relates to semiconductor memory, particularly relate to the structure of the check reliability that is used to improve semiconductor memory.The present invention more specifically relates in the semiconductor memory with a plurality of input and output leading-out ends, in check system operation, write, read and the input of control signal, the structure of the semiconductor memory of the operation of can testing by data from specific input and output leading-out end.

Background technology

Intermediate survey operation in semiconductor memory wafer manufacturing process (for example, Pre-testing before the laser reconditioning or the wafer inspection that carries out thereafter etc.) in, in order to implement check, a plurality of probes are contacted with a plurality of corresponding respectively solder joints of wafer semiconductor-on-insulator chip.

Fig. 9 is the figure of such probe of expression and the relation of the pad configuration on the semi-conductor chip.

Be accompanied by the increase of semiconductor memory memory capacity etc., and be accompanied by the many of data input and output than specialization, the increase of data bit width when promptly carrying out input and output, the solder joint number of semiconductor memory has the trend of increase.In view of the above, welded spot pitch narrows down, so, probe is contacted with whole input and output solder joints just become difficulty.

Therefore, wish that structure probe does not contact with whole input and output solder joints and the structure of the operation of testing in above-mentioned intermediate survey operation.

On the other hand, be accompanied by the complicated of the increase of semiconductor memory memory capacity and circuit, in the stage before being about to shipment, have the chip that has the defective factor that in production process, produces and hidden with certain frequency inevitably.

Promptly, exist result from that the structural detail of semiconductor memory is that the gate insulating film of MOS transistor is defective, the interlayer dielectric disconnection defective, wiring between wiring is defective, the leakage between wiring is defective and the unfavorable condition of the impurity of sneaking into during with production process and situation about being hidden, as it is is intactly loaded and transported as product, then become the failure cause that so-called " incipient failure mode " takes place.

Therefore, generally be that semiconductor memory is worked under the condition of High Temperature High Pressure, above-mentioned initial stage unfavorable condition is obviously changed, the unacceptable product before the shipment is excluded, carry out screening according to so-called " wearing out " check.On the other hand, " wear out " proving time at this, simple write and readout interval also increases pro rata with memory capacity, the growth of proving time directly and the rising of chip cost interrelate.

For this reason, make a plurality of semiconductor memories are configured in the structure of concurrently a plurality of semiconductor memories being tested on the inspection panel, can seek to suppress the increase of above-mentioned proving time.

But as mentioned above, when semiconductor memory further was tending towards high capacity in recent years, the structure of its data input and output became many than specialization.

As a result, the number of the semiconductor memory that each verifier can be checked has simultaneously reduced, even adopt the above-mentioned like that also structure of performing check, also increase proving time, and then cause the increase of inspection cost.

As its countermeasure, the method according to the reduction inspection cost of data bit compression function has been proposed.That is, make following structure: as the function of semiconductor memory, carry out in semiconductor storage inside relatively reaching whether consistent detection between a plurality of sense datas, this decision signal is outputed on the specific input and output terminal from semiconductor memory.By such mode, make the input/output terminal subnumber seen from the verifier beyond become possibility in the apparent check system operation that has reduced.By means of such structure, can suppress the minimizing of the semiconductor memory number that each verifier can measure simultaneously.

Thereby, in semiconductor memory, under check system, do not need whole data that provide to a plurality of data input and output solder joints with data bit compression function as described above.For this reason, for example, in common operation, be under the situation that the semiconductor memory conduct * 1 structure is tested of what is called * 4 structures, if only data are provided on the data input and output solder joint in the data input and output solder joint of a plurality of existence, can carry out the intermediate survey in the wafer operation.

Figure 10 is the general block diagram of structure that expression has the semiconductor memory 301 of existing above-mentioned data bit compression function.

In the read operation in common mode of operation, according to the external address signal Ao～Ai that provides by address signal input terminal 8, select the storage data of particular storage from memory cell array 15, amplify by means of the sensor amplifier in sensor amplifier and I/O circuit 14 and 16, the I/O circuit by wherein outputs on the internal data bus as inner sense data q0～q3.

Input and output buffer circuit 61～64 comprises the commutation circuit 91～94 that switches to one of following two states respectively with the connection status of outside input and output terminal 65～68.

That is, commutation circuit 91～94, couples together input and output buffer circuit 61～64 and input and output terminal 65～68 respectively in common mode of operation one by one according to the check system specification signal TE that takes place with control signal generation circuit 11.That is, among Figure 10, each commutation circuit 91～94 be connected to represent with solid line beyond on.

Thereby output buffer 61～64 is accepted respectively to produce outside sense data DQ0～DQ3 from inside sense data q0～q3 that 4 storage unit are read, and it is outputed to respectively on each data input and output terminal 65～68.

In the write operation in common mode of operation, by means of the operation opposite with above-mentioned read operation, the outside that input and output buffer circuit 61～64 is accepted to be provided to respectively on the outside input and output terminal 65～68 writes data DQ0～DQ3, data by the I/O circuit, are one by one exported 4 storage unit being selected by external address signal Ao～Ai.

On the other hand, written allowance signal EXT./W, output that control signal generation circuit 11 is accepted external control signal allow signal EXT./OE, rwo address strobe signals EXT./RAS and column address gating signal EXT./CAS, detect and specified check system (for example, aging check system) information, the check system specification signal TE that output activates.

Commutation circuit 91～94 is according to the activation of check system specification signal TE, and input and output buffer circuit 61～64 and specific input and output terminal (for example, input and output terminal 65) are coupled together jointly.That is, among Figure 10, commutation circuit 91～94 becomes the connection status that dots.

Thereby, in the write operation in check system, the data that write that are provided on the input and output terminal 65 are offered 4 storage unit selecting with external address signal Ao～Ai by the I/O circuit jointly.

In the read operation in check system, the inside read output signal q0～q3 from 4 storage unit selecting by external address signal Ao～Ai is input on the logic synthesis circuit 47, logic synthesis circuit 47 is judged the consistent or inconsistent of these signals.

Logic synthesis circuit 47 outputs to decision signal Tmqo on the input and output terminal 65 according to the consistent or inconsistent result of determination of input data.

Thereby, when check system is operated, only become and carry out the input and output of data by input and output terminal 65.That is, make becoming possibility for the semiconductor memory conduct of * 4 structures * 1 structure is tested in the operation usually.

For this reason, though the structure of semiconductor memory input and output many than specialization situation under, the semiconductor memory number that can check concurrently simultaneously with a verifier does not reduce.

Figure 11 be the expression to having the semiconductor memory of such data bit compression function, when making probe touch on the input and output solder joint in the intermediate survey in the wafer operation, the figure of the configuration of probe and semi-conductor chip.

As mentioned above, because the solder joint that input and output are used as data only uses the solder joint corresponding to outside inputoutput data DQ0 to get final product, thus do not need to make the solder joint of probe contact corresponding to other DQ1～DQ3, so, can produce allowance aspect the interval of probe.

Certainly, in the intermediate survey operation, for example, in the common operation for the semiconductor memory of * 16 structures in the check system operation with * 4 structures situation such as test, probe number required in the time of can making checked operation further reduces, and can make the interval between probe produce allowance.

Figure 12 is the general block diagram of expression corresponding to the structure of the first order input buffer circuit of such data input and output solder joint setting.

First order input buffer circuit 500 comprises: accept the outer input data DQi from corresponding input and output solder joint on an input node, another input node is fixed to the NAND circuit 510 on the power supply potential Vcc; And accept the output of NAND circuit 510, its paraphase cooperation is the inner phase inverter 520 that writes data Qi output.

That is, NAND circuit 510 is fixed on the power supply potential Vcc because of an one input node, so say equivalently, it comes work as the side circuitry phase.

Figure 13 is the circuit diagram that illustrates in greater detail the structure of first order input buffer circuit 500 shown in Figure 12.

NAND circuit 510 comprises: the P

channel MOS transistor

512 and 514 that is connected in parallel between the node of output node OUT1 and supply power current potential Vcc; And the N-

channel MOS transistor

516 and 518 that between output node OUT1 and ground potential GND, is connected in series mutually.

The grid of P channel MOS transistor 514 and N-channel MOS transistor 516 is connected with input node IN1 together, and power supply potential Vcc is supplied with input node IN1.

On the other hand, the grid of P channel MOS transistor 512 and N-channel MOS transistor 518 is connected with input node IN2 together, the outside of correspondence is write data DQi offer and import node IN2.

On the other hand, phase inverter 520 comprises: P channel MOS transistor 522 that is connected in series between power supply potential Vcc and ground potential GND and N-channel MOS transistor 524.

Transistor

522 and 524 grid are connected with input node IN3 together, import node IN3 and are connected with the output node OUT1 of NAND circuit 510.

On the other hand, transistor 522 is connected with output node OUT2 with 524 tie point, writes data qi from output node OUT2 output inside.

Here, as mentioned above, examination considers in the relevant intermediate survey in the wafer operation by means of the data bit compression function, and probe is not touched corresponding to the situation on the input and output solder joint of the input node IN2 of first order input buffer circuit shown in Figure 13.

At this moment, the potential level of input node IN2 becomes electric quick condition.

For this reason, because the potential level of node IN2 (has for example become uncertain value, for a certain reason, this input node IN2 is charged to more than the ground potential GND), become the situation for 1/2Vcc if consider potential level, then N-channel MOS transistor 518 has become and has not been the state that ends fully.

On the other hand, when input node IN2 was such potential level, P channel MOS transistor 512 also became and has not been the state that ends fully.The grid potential of N-channel MOS transistor 516 is fixed on the power supply potential Vcc, and transistor 516 is a conducting state.Therefore, from having formed electric current leakage paths between power supply potential Vcc and the earth potential GNP through P channel MOS transistor 512, N-channel MOS transistor 516 and N-channel MOS transistor 518.Thereby, for example in the intermediate survey operation, when measuring the characteristic of the such small current value of current sinking under the stand-by state of semiconductor memory, exist this measured value not settle out in the problem that a steady state value or measured value have become the value of not representing the original ability of semiconductor memory.

Such problem is not limited to have the situation of the semiconductor memory of data bit compression function as described above, for example, in the semiconductor memory of dual-port structure, in the intermediate survey operation, even under the situation that only relevant port is tested to one of them, because exist the data input and output solder joint that does not contact with probe, so, also can produce same problem.

Summary of the invention

The present invention's purpose is, provide a kind of and common operation to compare in the check system operation and can reduce the semiconductor memory that the solder joint of control signal or data number must be provided, in the inspection process of this semiconductor memory in the wafer operation, can suppress to be connected to the power consumption electric current change of the first order input buffer circuit on the input and output solder joint that does not contact with probe.

Another purpose of the present invention is, the semiconductor memory of the mensuration that can stably carry out the such small electric flow valuve of under stand-by state power consumption electric current in a kind of inspection process in the wafer operation is provided.

The present invention's another purpose is, provide in a kind of inspection process in the wafer operation of semiconductor memory with many bit compression function, by means of the data bit compression function, even become under the situation of open circuit, also can carry out the semiconductor memory of stable checked operation at the data input and output solder joint that will not need to supply with data.

If briefly describe the present invention, then be a kind of like this semiconductor memory, comprising: many word lines; Right with the multiple bit lines that described many word lines intersect; Be connected to a plurality of storage unit that are the configuration of ranks shape on described word line and the described bit line; The memory cell selecting device, according to external address signal, with corresponding storage unit between store reading/write operation of data; The mode of operation pick-up unit detects given check system stable condition really according to the control signal from the outside, thereby the check system signal activation; A plurality of input and output solder joints are accepted a plurality of input data from the outside respectively, and a plurality of output datas are provided to the outside; A plurality of buffered input/output sections, be provided with corresponding to described input and output solder joint, when write operation, accept described a plurality of input data, output on the described memory cell selecting device, when read operation, acceptance is from the data of described memory cell selecting device, output on the corresponding described input and output solder joint, described a plurality of buffered input/output section comprises: the 1st buffered input/output section, no matter mode of operation is described given check system, all accept described input data, and a plurality of the 2nd buffered input/output sections, when mode of operation is described given check system, do not accept described input data from the described input and output solder joint of correspondence; It is characterized in that: described semiconductor memory also comprises: a plurality of cmos logic gates, be provided with corresponding to described the 2nd buffered input/output section, in described given check system, the signal transmission between the input node that is breaking at described the 2nd buffered input/output section under the control of described check system signal and corresponding described input and output solder joint; Switching device shifter in described given check system, is provided on described a plurality of the 2nd input buffer jointly in following input data that are provided on described the 1st input buffer of the control of described check system signal; And many bit trial device, in the read operation in described given check system, according to making peace inconsistently, corresponding assay signal is provided on described the 1st buffered input/output section from having write one of a plurality of sense datas of reading from the storage unit of the common described input data of the described the 1st and the 2nd input buffer.

Thereby major advantage of the present invention is in the checked operation in the wafer operation, even there is the input and output solder joint that does not contact with probe, also can be suppressed in the cmos circuit of acceptance from the input data of this input and output solder joint and produces punchthrough current.

Another advantage of the present invention is, in the check system operation in the wafer operation, can stably carry out the mensuration of the small power consumption electric current etc. of stand-by state.

Description of drawings

Fig. 1 is the general block diagram of structure of the semiconductor memory 101 of expression the present invention the 1st embodiment;

Fig. 2 is the circuit diagram of the storage unit and the sensor amplifier structure partly of expression semiconductor memory 101;

Fig. 3 is the circuit diagram of structure of the input buffer circuit of expression semiconductor memory 101;

Fig. 4 is the circuit diagram of structure of the first order input buffer circuit of expression input buffer circuit shown in Figure 3;

Fig. 5 is the 1st circuit diagram of structure of the control signal generation circuit 11 of expression semiconductor memory 101;

Fig. 6 is the 2nd circuit diagram of the structure of expression control signal generation circuit 11;

Fig. 7 is the time diagram that is used to illustrate the operation of control signal generation circuit 11;

Fig. 8 is the circuit diagram of variation of the input buffer circuit of expression semiconductor memory 101 of the present invention;

Fig. 9 is the figure of configuration of the input and output solder joint of probe in the intermediate survey in the expression wafer operation and semi-conductor chip;

Figure 10 is the general block diagram of the structure of expression conventional semiconductor storer 301;

Figure 11 is the figure of the relation of the pad configuration of probe and semi-conductor chip when being illustrated in the data bit squeeze operation;

Figure 12 is the block scheme of structure of the 1st grade of input buffer circuit 500 of expression conventional semiconductor storer 301;

Embodiment

Fig. 1 is the general block diagram of the structure of expression embodiment of the invention semiconductor memory 101.

Among Fig. 1, semiconductor memory 101 comprises: external control signal EXT./W, EXT./OE, EXT./RAS and EXT./CAS that acceptance provides by external control signal input terminal 2～5, produce the control signal generation circuit 11 of internal control signal, storage unit is the memory cell array 15 that the ranks shape is arranged; External address signal Ao～Ai that acceptance provides by address signal input terminal 8, the address buffering circuit 12 of generation inner row address signal and internal column address signal under the control of control signal generation circuit 11; Under the control of control signal generation circuit 11, be activated, thereby the outer row address signal that provides from address buffer 12 deciphered the line decoder 13 of the row (word line) of select storage unit array 15.

Be provided to signal EXT./W on the external control signal input terminal 2 and be that specific data writes writes the permission signal.The signal EXT./OE that is provided on the external control signal input terminal 3 is the output permission signal of specific data output.The signal EXT./RAS that is provided on the external control signal input terminal 4 is the built-in function of beginning semiconductor memory 101 and the rwo address strobe signals between definite built-in function active period.When activating this signal EXT./RAS, make the circuit relevant become state of activation with the operation of the row of selecting memory cell array 15 such as line decoder 13.The signal EXT./CAS that is provided on the external control signal input terminal 5 is a column address gating signal, makes the circuit of the row in the select storage unit array 15 become state of activation.

Control signal generation circuit 11 is according to outer row gating signal EXT./RAS output internal rows gating signal int.RAS; According to outer array gating signal EXT./CAS output inner array gating letter int.CAS; Export inner written allowance signal WBE according to outside written allowance signal EXT./W; Allow the inner output of signal EXT./OE output to allow signal OEM according to outside output.

Semiconductor memory 101 and then comprise: under the control of control signal generation circuit 11, be activated,, produce the array decoding circuit 17 of array selecting signal of the row of select storage unit array 15 to deciphering from the internal column address signal of address buffering circuit 12; Detection is connected to the data of the storage unit on the selected row in the memory cell array 15 and the sensor amplifier that amplifies; In response to selecteed row in the memory cell array 15 being connected to I/O circuit on the internal data bus from the array selecting signal of array decoding circuit 17; Under the control of control signal generation circuit 11, accept to be provided to first input buffer circuit 71～74 of the outer input data DQ0～DQ3 on the data input and output terminal 65～68; Accept the output of first order input buffer circuit 71～74 respectively, output to the output buffer 61～64 on the corresponding internal data bus.

Semiconductor memory 101 and then comprise logic synthesis circuit 47, this circuit controlled signal generation circuit 11 is controlled, identical with conventional semiconductor storer 201 in the check system operation, the inside read output signal q0～q3 of 4 storage unit of external address signal Ao～Ai selection accepts use by oneself, judge the consistent inconsistent of these signals, output decision signal TEMqo.

Among Fig. 1, input and output buffer circuit 61～64 is controlled by the signal TE from 11 outputs of control signal generation circuit, in common data write operation, the output data from each corresponding first order input buffer circuit 71～74 is outputed on the corresponding respectively internal data bus; In the checked operation mode, all input and output buffer circuit 61～64 outputs to corresponding internal data bus to the signal from 71 outputs of the 1st grade of input buffer circuit jointly according to the signal DQ0 that is provided on the data input and output terminal 65.

Moreover, in structure shown in Figure 1, for purposes of simplicity of explanation, though only show the structure of the data that provide from data input and output terminal 65～68 being supplied with internal data bus respectively; But input and output buffer circuit 61～64 has the sense data from selecteed storage unit of reading respectively on the internal data bus of correspondence, outputs to the structure on the corresponding data input and output terminal 65～68 respectively.

Moreover among Fig. 1, sensor amplifier and I/O circuit are represented with 1 square frame 14 and 16.

Input and output buffer circuit 61～64 allows the activation (changing towards " H " level) of signal OME and becomes state of activation according to the inside output that allows signal EXT./OE to take place in control signal generation circuit 11 in response to outside output in read operation; In write operation, become state of activation according to the activation of the inside written allowance signal WBE that in control signal generation circuit 11, takes place in response to outside written allowance signal EXT./W.

Though be not particularly limited, but control signal generation circuit 11 is accepted external control signal EXT./W, EXT./OE, EXT./RAS and EXT./CAS, stable condition is (for example really to detect check system, aging check system), make check system detecting signal TE become state of activation (" H " level state).At this moment, for example external control signal EXT./W, EXT./OE, EXT./RAS and EXT./CAS can make the structure of specifying check system by so-called WCBR condition [before signal EXT./RAS activated (" L " level), signal EXT./W and signal EXT./CAS became the condition of state of activation (" L " level)].

Though be not particularly limited, Fig. 2 is the circuit diagram that expression has one of the memory cell array 15 of semiconductor memory 101 of data bit compression function and structure of sensor amplifier+I/O14 and 16 example.

Among Fig. 2,

sensor amplifier

20,22 and 24 and

sensor amplifier

21,23 and 25 clip bit line to and be disposed at two ends, each bit line that is connected on the relative sensor amplifier disposes alternately with each other.That is, for example become be connected to bit line on the sensor amplifier 20 to BL00 and ZBL00 between, configuration is connected to bit line on the sensor amplifier 21 to the structure of the bit line ZBL10 among BL10 and the ZBL10.

Bit line is connected respectively on internal data bus IO0 and the ZIO0 by N-

channel MOS transistor

26a and 26b BL00 and ZBL00.Bit line, is connected respectively on internal data bus IO1 and ZI01, IO2 and ZIO2 and IO3 and the ZIO3 similarly by N-

channel MOS transistor

26c and 26d, 26e and 26f and 26g and 26h BL10 and ZBL10, BL20 and ZBL20 and BL30 and ZBL30.

Grid potential by identical array selecting signal CSLO control N-channel MOS transistor 26a～26h.

Sensor amplifier 20 is connected to bit line on BL00 and the ZBL00, according to the power supply potential of supplying with from sensor amplifier control line S2N and S2P, amplify this bit line between potential difference (PD).Be connected respectively to bit line the

sensor amplifier

21,22 and 23 on BL10 and ZBL10, BL20 and ZBL20 and BL30 and the ZBL30 is similarly amplified respectively the bit line that connects between potential difference (PD).

Internal data bus IO0 and ZI00 are connected on the input and output buffer circuit 61, transmit inner write signal q0.Similarly, internal data bus IO1 and ZIO1, IO2 and ZIO2 and IO3 and ZIO3 are connected respectively on input and output buffer circuit 62,63 and 64, transmit inner write signal q1, q2 and q3.

On the intersection point of word line WLO and bit line BLO0, be connected storage unit 28a; With the intersection point of bit line BL10 on be connected storage unit 28b; With the intersection point of bit line BL20 on be connected storage unit 28c; With the intersection point of bit line BL30 on be connected storage unit 28d.

In the write operation of common mode of operation, outside from outside terminal 65～68 inputs is write data DQ0～DQ3 input and output buffer circuit 61～64, be transformed into corresponding respectively complementary interior write signal, on internal data bus IO0 and ZIO0～IO3 and ZIO3, transmit.For example select word line WLO according to external address signal Ao～Ai; As according to array selecting signal CSLO internal data bus IO0 and ZIO0～IO3 and ZIO3 and respectively corresponding bit lines just become to respectively one by one being written among storage unit 28a～28d coupling together corresponding to the storage data that are input to the data on the outside input and output terminal 65～68.

In contrast, in the write operation when the data bit squeeze operation, for example being transferred to jointly on totality data bus IO0 and ZIO0～IO3 and the ZIO3 corresponding to the complementary signal that is input to the data DQ0 on the outside input and output terminal 65.For example, this writes data when " L " level, and when data being write the storage unit 28a that selected by word line WLO and array selecting signal CSLO～28d, the bit line BL00～BL30 that is connected on these storage unit all becomes " L " level.On the other hand, the bit line ZBL00～ZBL30 with these bit line pairings becomes " H " level.

As mentioned above, in check system,, in above-mentioned example, just can write 4 storage unit to identical data simultaneously by only data DQ0 being provided on the data input and output terminal 65.

Moreover, in the superincumbent explanation, though what illustrate is to carry out the situation that the data of * 1 structure write in the semiconductor memory of what is called * 4 structures in check system, but, can understand that by following explanation the present invention is not limited to such situation, data bit squeeze operation to other word line structure, for example in operating usually, the semiconductor memory of right * 16 structures also can be used under the situation that the data that can carry out * 4 structures write in check system.

And then, more generally, be not limited in a plurality of data input and output terminals under check system, to exist the situation of the data input and output terminal that does not need to carry out the data input; For example, in the input and output terminal of input control signal, under check system, exist under the situation of the input and output terminal do not need input control signal and also can similarly use.

Fig. 3 is the circuit diagram of structure of the input buffer circuit of expression semiconductor memory 101 of the present invention.

Input buffer circuit

31a, 31b, 31c and 31d are included in respectively in the input buffer circuit 61,62,63 and 64 among Fig. 1.Because the structure of input buffer circuit 31b～31d is substantially the same with input buffer circuit 31a respectively, so structure and the operation of the relevant input buffer circuit 31a of following main explanation.

The data that are provided on the input and output terminal 65～68 are transferred on corresponding

input buffer circuit

31a, 31b, 31c and the 31d by first order input circuit 71～74 respectively.

That is, the outside that first order input buffer circuit 71 is accepted to be provided on the data input and output terminal 65 writes data DQ0, and output inside writes data dq0.

The outside that first order input buffer circuit 72～74 accepts to offer corresponding data input and output terminal 66～68 respectively writes data DQ1～DQ3, and the corresponding inside of output writes data dq1～dq3 respectively.

First order input buffer circuit 71 comprises: the potential level that input node is connected with data input and output terminal 65, another imports node is fixed in the NAND circuit 712 on the power supply potential Vcc; And accept the inner phase inverter 714 that writes data dq0 of output, output of NAND circuit 712.

On the other hand, first order input buffer circuit 72 comprises: an input node is the NAND circuit 722 of signal/TE with 66 connections of corresponding data input and output terminal, another inversion signal of importing the mode specification signal TE that accepts inspection on node; And accept the phase inverter 724 of the output of NAND circuit 722.

First order

input buffer circuit

73 and 74 structure are except the data input and output terminal of correspondence and corresponding input buffer circuit difference, identical with the structure of first order input buffer circuit 72.

Input buffer circuit 31a comprises: the commutation circuit 311 of switching input data path according to check system specification signal TE; And be subjected to inner written allowance signal WBE control, accept the output of commutation circuit 311, internal data bus IO0 and the complementary inside of ZIO0 output are write the input control circuit 321 of data.

Commutation circuit 311 comprises: acknowledge(ment) signal dq0, be subjected to the control of check system specification signal TE, become the clock phase inverter 312 of state of activation when " L " level as signal TE; Acknowledge(ment) signal dq0, becoming clock phase inverter 313 when " H " level as signal TE under the control of check system specification signal TE for state of activation; And the mode specification signal TE that accepts inspection, control signal is outputed to phase inverter 314 on

clock phase inverter

312 and 313.

Input control circuit 321 comprises: phase inverter 322; NAND circuit 323,324; Phase inverter 325,326; N-channel MOS transistor Q1, Q2, Q3 and Q4.

NAND circuit 323 is accepted the output of inner written allowance signal WBE and commutation circuit 311.Phase inverter 325 is accepted the output of NAND circuit 323.Phase inverter 322 is accepted the output of commutation circuit 311, and NAND circuit 324 is accepted the output of inner written allowance signal WBE and phase inverter 322.Phase inverter 326 is accepted the output of NAND circuit 324.N-channel MOS transistor Q1 and Q2 are connected in series to the power supply potential that is equivalent to " H " level and are equivalent between the earth potential of " L " level, and N-channel MOS transistor Q3 and Q4 also are connected in series between power supply potential and the earth potential.

The grid of N-channel MOS transistor Q1 and Q4 is connected with the output of phase inverter 325.The grid of N-channel MOS transistor Q2 and Q3 is connected with the output of phase inverter 326.N-channel MOS transistor Q1 is connected with internal data bus IO0 with the tie point of Q2, and N-channel MOS transistor Q3 is connected with internal data bus ZIO0 with the tie point of Q4.

Secondly, the operation of relevant input buffer circuit 31a is described.

At first, relevant mode of operation usually is described, promptly check system specification signal TE is the situation of " L " level.

At this moment, in commutation circuit 311, clock phase inverter 312 is a state of activation, and input signal paraphase and output, clock phase inverter 313 is a unactivated state.Thereby the output of phase inverter 714 was cut off with being connected of input control circuit 321.

When signal DQ0 for example was " H " level, the output of clock phase inverter 312 became the level for " L ".

Inner written allowance signal WBE be unactivated state (" L " level state) during in no matter commutation circuit 311 output signal level how,

NAND circuit

323 and 324 output all are " H " level, and

phase inverter

325 and 326 output also become the level for " L ".Thereby N-channel MOS transistor Q1～Q4 all becomes cut-off state, and internal data bus IO0 and ZIO0 become and be high-impedance state.

In contrast, when inner written allowance signal WBE becomes to state of activation (" H " level state), because the output of commutation circuit 311 is the output signal of clock phase inverter 312 is " L " as described above level, so, the output of NAND circuit 323 becomes " H " level, and the output of NAND circuit 324 becomes the level for " L ".

Thereby the output of phase inverter 325 becomes the level for " L ", and N-channel MOS transistor Q1 and Q4 are cut-off state.

On the other hand, phase inverter 326 is output as " H " level, and N-channel MOS transistor Q2 and Q3 become and be conducting state.Thereby internal data bus IO0 becomes " H " level, and internal data bus ZIO0 becomes the level for " L ".That is, the current potential of internal data bus IO0 and ZIO0 changes for " H " level corresponding to signal dq0.

Secondly, the state of relevant check system is described, the operation of input buffer circuit 31a when promptly check system specification signal TE is state of activation (" H " level state).

At this moment, in commutation circuit 311, clock phase inverter 312 is a unactivated state, and clock phase inverter 313 becomes state of activation.Thereby the output of the output dq0 of phase inverter 714 is connected with input control circuit 321.

That is,, produce internal circuit data dq0, in view of the above, drive the potential level of internal data bus IO0 and ZIO0 even in the check system state, also write data DQ0 on the data input and output terminal 65 according to being provided to.

In contrast, the operation of input buffer circuit 31b is as described below.

That is, in common mode of operation, the reversed phase signal of check system specification signal TE is that signal/TE is " H " level, and the operation of NAND circuit 722 becomes identical with the operation of NAND circuit 712 in the first order input buffer circuit 71 in the first order input buffer circuit 72.

Thereby, input buffer circuit 31b drives corresponding internal data bus IO2 and the potential level of ZIO2 according to the internal circuit data dq1 that the outside that is provided on the data input and output terminal 66 writes data DQ1 and exports according to the phase inverter from first order input buffer circuit 72 724.

In contrast, under the check system state, input buffer circuit 31b writes data DQ0 and writes data dq0 according to the inside from 71 outputs of first order input buffer circuit according to the outside, drives corresponding internal data bus IO2 and the potential level of ZIO2.

Relevant

input buffer circuit

31c and 31d, under common mode, write data DQ2 and DQ3 and, drive corresponding internal data bus IO1 and the potential level of ZIO1 and IO3 and ZIO3 according to being provided to outside on the corresponding data input and

output terminal

67 and 68 respectively similarly according to internal circuit data dq2 and dq3 from first order

input buffer circuit

73 and 74 outputs.

In contrast, under the check system state,

input buffer circuit

31c and 31d drive the potential level of internal data bus IO1 and ZIO1 and IO3 and ZIO3 according to being provided to writing data DQ0 and writing data dq0 according to the inside from 71 outputs of first order input buffer circuit on the data input and output terminal 65.

By means of aforesaid operations, in operating usually, write data according to the outside that is provided on the corresponding data input and output terminal respectively, drive the potential level of internal data bus IO0 and ZIO0～IO3 and ZIO3; Under the check system state, internal data bus IO0 and ZIO0～IO3 and ZIO3 write data DQ0 according to the outside that is provided on the data input and output terminal 65, drive its potential level.

That is, only, just common data can be write selected 4 storage unit by being provided on the data input and output terminal 65 writing data.

Fig. 4 is the more detailed circuit diagram of the structure of expression first order input buffer circuit 72 shown in Figure 3.

Structure about the 1st grade of input buffer circuit shown in Figure 4, except the structure that reversed phase signal/TE of check system specification signal TE is input to input node IN1, identical with the structure of the first order input buffer circuit in past shown in Figure 13, to being marked with prosign, do not repeat its explanation with a part.

Secondly, its relevant operation is described.

Because in first order input buffer circuit 72, in common mode of operation, signal/TE is " H " level, so, carry out the same operation of operation with the first order input buffer circuit in past shown in Figure 13.

In contrast, under the check system state, signal/TE becomes the level for " L ".For this reason, N-channel MOS transistor 516 becomes and is cut-off state.

Thereby, different with the first order input buffer circuit in past, though the data input and output terminal of correspondence " potential level become under the situation for Vcc/2, in NAND circuit 722, do not produce the punchthrough current that flows to ground potential GND from power supply potential Vcc yet.

That is, even be not all to become under the situation of ending fully, because N-channel MOS transistor 516 is fixed in cut-off state, so become the structure that does not produce the punchthrough current path at P channel MOS transistor 512 and N-channel MOS transistor 518 yet.

The structure of first order input buffer circuit 71 is identical with the structure of the first order input buffer circuit in past shown in Figure 13, and the structure with first order input buffer circuit 72 is identical basically for first order

input buffer circuit

73 and 74 structure.

Thereby, under the check system state, thereby probe contact data input and output terminal 66～68 is not become under the situation of electric quick condition, with first order input buffer circuit 72～74 that this data input and output terminal 66～68 is connected in do not produce punchthrough current.

Thereby, in such checked operation mode, even thereby in the number of cutting down probe probe separation is produced under the situation of allowance, also can stably carry out the mensuration of the such small electric flow valuve of the power consumption electric current of stand-by state.

Fig. 5 is the expression basis provides check system specification signal TE from the outside signal EXT./W, signal EXT./RAS and signal EXT./CAS, output internal control signal φ _MSAnd signal psi _MRThe circuit diagram of structure of internal control circuit 200; Fig. 6 is that expression is according to signal psi _MSAnd signal psi _MR, make check system specification signal TE become the block scheme of structure of the RS trigger circuit 25 0 of state of activation or unactivated state.

With reference to Fig. 5, internal control circuit 200 comprises: be received in the control signal generation circuit 11 the signal int./WE that takes place according to signal EXT./W and the NOR circuit 210 of these two signals of signal int./CAS of taking place according to signal EXT./CAS; On grid, accept signal int./RAS, the N-channel MOS transistor 216 that a certain utmost point of source electrode and drain electrode is connected with the output of NOR circuit 210 according to signal EXT./RAS generation; The latch cicuit 218 of the potential level of another node P in the source electrode of maintenance N-channel MOS transistor 216 and the drain electrode; Acknowledge(ment) signal int.RAS on grid (reversed phase signal of signal int./RAS), a certain utmost point of source electrode and drain electrode is connected with node P, another utmost point and output internal control signal φ _MSThe N-channel MOS transistor 222 that connects of node P '; And be connected between node P ' and the earth potential N-channel MOS transistor 226 of acknowledge(ment) signal int./RAS on grid.

Internal control circuit 200 also comprises: the phase inverter 212 of acknowledge(ment) signal int./WE; The NOR circuit 214 of the output of acknowledge(ment) signal int./CAS and phase inverter 212; Acknowledge(ment) signal int./RAS on grid, a certain utmost point of source electrode and drain electrode is connected with the output of NOR circuit 214, the N-channel MOS transistor 220 that another utmost point is connected with node Q; The latch cicuit 224 that keeps the potential level of node Q; Acknowledge(ment) signal int.RAS on grid, a certain utmost point of source electrode and drain electrode is connected with node Q, another utmost point and output signal φ _MRThe N-channel MOS transistor 228 that connects of node Q '; And on grid acknowledge(ment) signal int./RAS, be connected to the N-channel MOS transistor 230 between node Q ' and the earth potential.

With reference to Fig. 6, control signal generation circuit 11 and then comprise RS trigger circuit 250, this circuit is signal psi _MSAccept as asserts signal, signal psi _MRThereby accept output check system specification signal TE as reset signal.

Secondly, the operation of relevant internal control circuit 200 of simple declaration and RS trigger circuit 250.Fig. 7 is the time diagram of the operation of explanation internal control circuit 200 and RS trigger circuit 250.

At moment t1, signal EXT./CAS and EXT./WE drop to " L " level from " H " level.After this, at moment t2, signal EXT./RAS also drops to " L " level.That is, set so-called WCBR condition.

During from moment t1 to t2, all be " L " level according to signal EXT./WE and EXT./CAS, the output level of NOR circuit 210 becomes the level for " H ".During moment t1～moment t2, because signal EXT./RAS, promptly signal int./RAS is " H " level, and N-channel MOS transistor 216 is a conducting state, so the potential level of node P also becomes " H " level.Keep this potential level by latch cicuit 218.

On the other hand, the potential level of the node Q that is connected with the output node of NOR circuit 214 is " L " level, and latch cicuit 224 keeps this potential level.

In moment t1～moment t2, the N-

channel MOS transistor

222 and 228 of acknowledge(ment) signal int.RAS on grid (reversed phase signal of signal int./RAS) all is a not on-state; N-

channel MOS transistor

226 and 230 at grid acknowledge(ment) signal int./RAS all is a conducting state.Thereby the potential level of node P ' and Q ' all is " L " level, signal psi _MSAnd φ _MRIt all is " L " level.

At moment t2, signal EXT./RAS one drops to " L " level from " H " level, and N-channel MOS transistor 216,220,226 and 230 is not on-state with regard to all becoming.In contrast, because all becoming, the N-

channel MOS transistor

222 and 228 of acknowledge(ment) signal int.RAS on grid (reversed phase signal of int./RAS) is conducting state, so, at moment t3, the potential level of node P ' rises to " H " level, and the potential level of node Q ' is maintained " L " level.

That is, as shown in Figure 7, in moment t2, signal psi _MSChange over " H " level.

Secondly, with reference to Fig. 6, according to signal psi _MSBecome the level for " H ", at moment t3, the output signal of RS trigger circuit 250 is " H " level that check system specification signal TE set becomes state of activation.

Specify the operation of check system by means of aforesaid operations, during check system in, the level of signal TE is maintained " H " level, the level of signal/TE is maintained " L " level.

At moment t4, become level according to signal EXT./RAS for " H ", N-

channel MOS transistor

226 and 230 all becomes and is conducting state, the potential level of node P ' and Q ', i.e. signal psi _MSAnd signal psi _MRLevel all become level for " L ".

During above-mentioned, finish the set cycle of check system operation.

Then, in check system operation, for example resemble usually according to the decline of " L " level of signal EXT./RAS along the taking-up row address; According to the decline of signal EXT./CAS along taking out column address signal, the operation of testing thus.

Checked operation one finishes, and has begun the reset cycle with that.

In the reset cycle, at moment t5, signal EXT./CAS drops to " L " level, and then, at moment t6, signal EXT./RAS drops to " L " level.

That is, set so-called CBR condition.

In moment t5～moment t6, the potential level of NOR circuit 214 output nodes becomes the level for " H ", and the output node of NOR circuit 210 is maintained " L " level.With identical in the set cycle, according to (potential level of NOR circuit 210 in the moment t5～t6) and 214 output node separately, φ in the output signal on the down position of the signal EXT./RAS of moment t6 during this period _MSAnd φ _MR

That is, in moment t6, signal psi _MSBe maintained " L " level, signal psi _MRRise to " H " level.In view of the above, RS trigger circuit 250 reset output level, and at moment t7, check system specification signal TE becomes the level for " L ".

At moment t8, according to signal EXT./RAS and/CAS turns back to " H " level, signal psi _MRAlso turn back to " L " level.

By the operation of internal control circuit 200 described above and RS trigger circuit 250, can become state of activation or unactivated state to check system specification signal TE and reversed phase signal/TE setting thereof according to the combination of external control signal.

In the superincumbent explanation, first order input buffer circuit 71～74 is as comprising that the circuit of NAND circuit illustrates.

But, in order to form first order input circuit 71～74, be not limited to such structure, also can use other cmos logic gate circuit.

Fig. 8 is the circuit diagram of the variation of expression first order input buffer circuit shown in Figure 3.

Be with the difference of the structure of first order input buffer circuit shown in Figure 3, the outside that provides from data input and output terminal 65～68 write the cmos logic gate that data DQ0～DQ3 accepts as an input constitute the NOR circuit.

That is, the first order input buffer circuit 71 that is provided with corresponding to data input and output terminal 65 comprises: accept power supply potential Vcc on an input node, the NOR circuit 716 that another input node is connected with data input and output terminal 65; And accept the output of NOR circuit 716, will the inner phase inverter 714 that writes data dq0 of output after its paraphase.

The first order input buffer circuit 72 that is provided with corresponding to data input and output terminal 66 comprises: the mode specification signal TE that accepts inspection on an input node, the NOR circuit 726 that another input node is connected with data input and output terminal 66; And accept the output of NOR circuit 726, will the inner phase inverter 724 that writes data dq1 of output after its paraphase.

Corresponding to data input and

output terminal

67 and 68 and the first order input buffer circuit 73 that is provided with and 74 structure are basic identical with the structure of input first order buffer circuit 72.

By such structure, also can access the circuit identical effect illustrated with Fig. 3.

In addition, if can transmit the cmos logic gate of cut-out to corresponding data input and output terminal and the signal between the corresponding input buffer, also can play same effect according to signal TE.

Claims

1. semiconductor memory comprises:

Many word lines;

Right with the multiple bit lines that described many word lines intersect;

Be connected to a plurality of storage unit that are the configuration of ranks shape on described word line and the described bit line;

The memory cell selecting device, according to external address signal, with corresponding storage unit between store reading/write operation of data;

The mode of operation pick-up unit detects given check system stable condition really according to the control signal from the outside, thereby the check system signal activation;

A plurality of input and output solder joints are accepted a plurality of input data from the outside respectively, and a plurality of output datas are provided to the outside;

A plurality of buffered input/output sections, be provided with corresponding to described input and output solder joint, when write operation, accept described a plurality of input data, output on the described memory cell selecting device, when read operation, acceptance outputs on the corresponding described input and output solder joint from the data of described memory cell selecting device

Described a plurality of buffered input/output section comprises:

The 1st buffered input/output section no matter mode of operation is described given check system, is all accepted described input data, and

When a plurality of the 2nd buffered input/output sections, mode of operation are described given check system, do not accept described input data from the described input and output solder joint of correspondence;

It is characterized in that:

Described semiconductor memory also comprises:

A plurality of cmos logic gates, be provided with corresponding to described the 2nd buffered input/output section, in described given check system, the signal transmission between the input node that is breaking at described the 2nd buffered input/output section under the control of described check system signal and corresponding described input and output solder joint;

Switching device shifter in described given check system, is provided on described a plurality of the 2nd buffered input/output section jointly in following input data that are provided on described the 1st buffered input/output section of the control of described check system signal; And

Many bit trial device, in the read operation in described given check system, according to making peace inconsistently, corresponding assay signal is provided on described the 1st buffered input/output section from having write one of a plurality of sense datas of reading from the storage unit of the common described input data of the described the 1st and the 2nd buffered input/output section.

2. semiconductor memory according to claim 1 is characterized in that:

Described cmos logic gate circuit is to accept described check system signal on an input node, the NAND circuit with two input ends of another input node and corresponding input and output solder joint connection.

3. semiconductor memory according to claim 1 is characterized in that:

Described cmos logic gate circuit is to accept described check system signal on an input node, the NOR circuit with two input ends of another input node and corresponding input and output solder joint connection.