CN112164358A

CN112164358A - Feedback signal detection method and pixel external analog domain compensation display system

Info

Publication number: CN112164358A
Application number: CN202011037598.3A
Authority: CN
Inventors: 林兴武; 张盛东; 张敏; 焦海龙; 黄杰; 邱赫梓; 李成林; 文金元
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-01
Anticipated expiration: 2040-09-28
Also published as: CN112164358B; WO2022061998A1

Abstract

The invention provides a feedback signal detection method and an off-pixel analogue domain compensation display system, wherein the system comprises M rows of driving channels; each column driving channel comprises a pixel unit and a detection unit; the detection unit comprises a source driving module and a detection module; the detection module includes a comparator. A first digital-to-analog converter and a second digital-to-analog converter are arranged in the source driving module. The source driving module is connected to the pixel unit through a display signal line. The first input end of the comparator is connected to the pixel unit through a feedback signal line, the second input end of the comparator is connected to the second digital-to-analog converter, and the output end of the comparator is used for outputting the detection result. The invention utilizes the digital-to-analog converter and the comparator to match with the aging information fed back by the detection target pixel unit, can detect devices such as TFT, OLED, QLED and the like, also utilizes the existing modules in the display system, can not increase the area of a chip, and optimizes the overall design of the display system.

Description

Feedback signal detection method and pixel external analog domain compensation display system

Technical Field

The invention relates to the field of photoelectric technology, in particular to a feedback signal detection method and an off-pixel analog domain compensation display system.

Background

In the prior art, there are various Display products, such as an AMOLED (Active matrix Organic Light Emitting Diode or Active matrix Organic Light Emitting Diode) which uses a TFT (Thin Film Transistor) for pixel unit circuit Display and adds an OLED (Organic Light Emitting Diode or Organic electroluminescent Display, also called as an Organic Light Emitting Diode, an Organic electroluminescent Display or an Organic Light Emitting semiconductor) Display screen thereon.

The micro-display product of OLED-on-Silicon or QLED-on-Silicon type is a pixel unit circuit array made of Silicon, and OLED or QLED (Quantum Dot Light Emitting Diodes T1) Light Emitting devices are added on the micro-display product.

TFT, OLED, QLED, etc. all suffer from aging problems after light emission, e.g., TFT threshold voltage rise causes the TFT to age the same display signal giving less current. When the display screen starts displaying, the threshold voltage of the aging TFT or the threshold voltage of the aging OLED can shift. The increase in OLED threshold voltage results in a decrease in OLED current. The light emitting efficiency of an aging OLED decreases, i.e., the same input current, and the light emitted by the aging OLED decreases.

Besides the aging problem, the TFT, the OLED, the QLED, and the like have the problem of uneven threshold voltage, for example, uneven threshold voltage and uneven light emitting brightness of the display screen may be caused during the production process due to the process. Due to the different display positions of the pixel units on the display screen, the uneven power supply voltage of the pixel units can be caused by the flowing of current when the display screen emits light, and the uneven temperature can cause the uneven current of the driving tubes. The unevenness of each channel source driving module can cause the unevenness of the feedback driving current.

In addition, the display driving chips of all pixel systems have the problem of uneven driving of different driving channels, i.e. driving circuits.

Disclosure of Invention

The invention provides an off-pixel analogue domain compensation display system of a feedback signal detection method, which comprises M rows of driving channels; each column driving channel comprises a pixel unit and a detection unit; the detection unit comprises a source driving module and a detection module; the detection module comprises a comparator; the system is an out-of-pixel compensation double-digital-analog converter display system, and a first digital-analog converter and a second digital-analog converter are arranged in the source driving module; the source driving module is connected to the pixel unit through a display signal line; a first input end of the comparator is connected to the pixel unit through a feedback signal line and used for receiving a feedback voltage corresponding to a feedback signal of the pixel unit; the second input end of the comparator is connected to the second digital-to-analog converter and used for receiving the comparison voltage output by the second digital-to-analog converter; the output end of the comparator is used for outputting a detection result obtained by comparing the feedback voltage with the comparison voltage; wherein M is an integer of 1 or more.

The invention also provides a feedback signal detection method, which is applied to the display system and comprises the following processes:

sequentially gating the writing channels of the pixel units in the 1 st row to the Nth row and carrying out detection operation when the writing channel of each row of pixel units is gated;

repeating the operation, gating the writing channels of the pixel units in the 1 st row to the Nth row again, and performing detection operation when the writing channel of each row of pixel units is gated;

the detection operation process comprises the following steps: when the write-in channel of the nth row of pixel units is gated, controlling the pixel units to generate feedback voltage and controlling the second digital-to-analog converter to output comparison voltage, so that the first input end of the comparator receives the feedback voltage corresponding to the feedback signal, and the second input end of the comparator receives the comparison voltage; comparing the feedback voltage with the comparison voltage; the control comparator feeds back the detection result obtained by comparison to the aging information memory through the shift-out circuit.

The invention provides a feedback signal detection method and an off-pixel Analog domain compensation display system, the system is an off-pixel compensation double-DAC (Digital-to-Analog Converter) display system, aging information fed back by a target pixel unit is detected by matching a Digital-to-Analog Converter and a comparator of the off-pixel compensation display system, namely, the threshold voltage of a light-emitting device and the threshold voltage of a driving tube in the pixel unit are detected, devices such as TFT, OLED, QLED and the like can be detected, further, the problems of device aging, uneven threshold voltage, uneven driving and the like are analyzed, the invention is suitable for various types of products such as AMOLED, OLED-on-Silicon, QLED-on-Silicon, PMOLED (Passive matrix organic electroluminescent diode, Passive matrix OLED), LCD driving chip, OLED lighting driving chip and the like, and the invention also fully utilizes the existing modules in the display system, the area of the chip is not increased, and the overall design of the display system is optimized.

The prior art has the disadvantages that the pixel unit can only feed back a fixed expected current by using a compensated correction signal, and the aging information detection module compares the current with a reference current and indirectly calculates the aging degree of the pixel unit driving tube. In the invention, the threshold voltage of the pixel unit driving tube and the threshold voltage change condition of the OLED are directly detected by repeatedly using the existing modules (namely the DAC and the comparator).

Drawings

FIG. 1 is a schematic diagram of a conventional external compensation display system;

FIG. 2 is a resistor string of a display DAC and a compensation DAC of a source driver module of an out-of-pixel compensated dual DAC display system;

FIG. 3 is a schematic diagram illustrating gamma curve correction performed by 256 reference voltages in a resistor string;

FIG. 4 is a schematic diagram of a pixel unit structure suitable for the present invention;

FIG. 5 is a schematic diagram of a pixel unit structure suitable for the present invention;

FIG. 6 is a schematic layout diagram of a conventional off-pixel compensated dual DAC display system;

FIG. 7 is a schematic partial structure diagram of a display system according to a first embodiment;

FIG. 8 is a schematic partial structure diagram of a display system according to a second embodiment;

FIG. 9 is a schematic view of the detection operation of the present invention;

FIG. 10 is a diagram illustrating comparison between a feedback voltage and a comparison voltage.

Reference numerals: the display device comprises a controller 10, a row scanning driver 20, a source driver 30, a display panel 40, a timing control module 11, a compensation algorithm module 12, an aging information memory 13, a first shift-in circuit 34, a second shift-in circuit 35, a detection unit 32, a shift-out circuit 33, a source driving module 321, a detection module 322, a first digital-to-analog converter 61, a second digital-to-analog converter 62, an analog adder 63, a comparator 72, a current source 73, a pixel unit 41, a display address line 42, a feedback address line 43, a display signal line 44, a feedback signal line 45, a second switching tube Q2, a third switching tube Q3, a driving tube Q1, a light emitting diode T1, a first resistor string 81, a second resistor string 82, a resistor 08, a first switch sw1 and a second switch sw 2.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present invention have not been shown or described in the specification in order to avoid obscuring the present invention from the excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they can be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.

Herein, N is an integer of 1 or more and N or less; m is an integer greater than or equal to 1, and M is an integer greater than or equal to 1 and less than or equal to M; k is a natural number greater than 0, and K is a natural number greater than 0.

In the technical field, schemes for compensating an AMOLED display system are divided into in-pixel compensation and out-pixel compensation (or external compensation), an out-pixel compensation method is divided into a real-time compensation method and a non-real-time compensation method, the non-real-time compensation method is divided into a digital domain compensation method and an analog domain compensation method, and the AMOLED display system adopts an analog domain compensation method.

Fig. 1 is a schematic structural diagram of a conventional external compensation display system, which includes a controller 10, a line scan driver 20, a source driver 30, and a display panel 40, wherein the controller 10 is connected to the line scan driver 20 and the source driver 30. The controller 10 includes a timing control module 11, a compensation algorithm module 12 and an aging information memory 13 connected in sequence. The source driver 30 includes a first shift-in circuit 34, a second shift-in circuit 35, a shift-out circuit 33, and M detection units 32; the detection unit 32 includes a source driving module 321 and a detection module 322; the source driving module 321 includes a first digital-to-analog converter, a second digital-to-analog converter and an analog adder, and the detecting module 322 includes a comparator.

The display panel 40 comprises N rows and M columns of pixel units 41, and the row scanning driver 20 draws out N rows of display address lines 42 and feedback address lines 43; wherein, the nth row display address line 42 and the feedback address line 43 are respectively connected to each pixel unit 41 of the nth row; the row scan driver 20 is configured to receive a row control signal from the controller 10 and gate the write channels of the pixel units in the rows 1 to N sequentially through the row 1 to N display address lines. The pixel units in the first row are respectively numbered as [1,1]. to. [1, M ]. to. [1, M ], the pixel units in the nth row are respectively numbered as [ N,1]. to. [ N, M ], and the pixel units in the nth row are respectively numbered as [ N,1]. to. [ N, M ].

The sequential control module 11, the first shift-in circuit 34 and the mth column of first digital-to-analog converters are connected in sequence, and the compensation algorithm module 12, the second shift-in circuit 35 and the mth column of second digital-to-analog converters are connected in sequence. The source driving module 321 of the m-th column detection unit 32 is connected to the m-th column display signal line 44 and further connected to each pixel unit 41 of the m-th column, respectively.

The detection module 322 in the m-th column of the detection unit 32 is respectively connected to each pixel unit 41 in the m-th column through the m-th column feedback signal line 45, and is configured to receive a feedback voltage corresponding to a feedback signal of the pixel unit 41. It should be understood by those skilled in the art that the detection module 322 in the m-th column of detection units 32 can also be used for receiving the feedback current corresponding to the feedback signal of the pixel unit 41, and the technical effects of the present invention can also be achieved.

The output end of the detection module 322 in the mth row detection unit 32, the shift-out circuit 33, and the aging information memory 13 are sequentially connected, so that the output end of the mth row detection unit 322 compares the feedback voltage with the comparison voltage through the shift-out circuit 33, and feeds back a detection result obtained by comparing the feedback voltage with the comparison voltage to the controller 10 through the shift-out circuit 33.

The M-th row of the pixel units 41 and the M-th row of the detecting units 32 form an M-th row of the driving channels, and the display system is divided into M rows of the driving channels.

In the analog domain compensation method, a compensation algorithm in a controller 10 only calculates a compensation value (digital compensation signal), the digital compensation signal and a digital display signal are synchronously input to a source driver 30 from the controller 10, 2 DACs are used in the source driver 30 to respectively convert the digital compensation signal and the digital display signal into analog signals, then 2 analog signals are added by an analog adder to obtain a compensated analog display signal, the compensated analog display signal is output to a display signal line, and then the compensated analog display signal is written into a pixel unit.

The bit width of the two DACs in each channel can be smaller than that of a single DAC display system (for example, 2 DACs are all 8 bits, the compensation of a single DAC digital field needs to realize gamma correction and reserve a voltage space for aging of a pixel unit, and the DAC generally needs more than 10 bits). The difference between the pixel external compensation dual DAC display system and the pixel external compensation single DAC display system is that the dual DAC display system does not output the digital display signal to the source driver 30 after the controller 10 completes compensation to convert the digital display signal into a 10-bit compensated digital display signal, but simultaneously outputs the 8-bit digital display signal and the 8-bit digital compensation signal calculated by the compensation algorithm to the source driver 30, and two DACs in the source driving module corresponding to each column of pixel units respectively convert the digital display signal and the digital compensation signal into an analog display signal (voltage) and an analog compensation signal (voltage), and then adds the analog display signal and the analog compensation signal by the analog adder to convert the analog display signal and the analog compensation signal into a compensated analog display signal to be output to the display signal line.

As shown in fig. 2, in the prior art, a source driving module 321 of an off-pixel compensation dual DAC display system includes a first DAC 61, a second DAC 62, and an analog adder 63, wherein 2 DACs respectively convert a digital display signal and a digital compensation signal into analog signals (voltages), and the analog signals are added by the analog adder to form a compensated analog display signal and output the compensated analog display signal to a display signal line connected to the source driving module. Each source driving module has two groups of 256 reference voltage signal lines, one group of reference voltages is V _ disp _0, V _ disp _1.. V _ disp _255 which represents 256 reference voltages with different sizes for the display DAC, and the other group of reference voltages is V _ comp _0, V _ comp _1.. V _ comp _255 which represents 256 reference voltages with different sizes for the compensation DAC. The DAC in each source driving module is only a simple decoding circuit, and after 8-bit digital signals are decoded and input, a corresponding reference voltage is selected from 256 voltages and distributed to an output end. The 2 groups of 256 reference voltage lines are shared by all the source driving modules, and are from 2 resistor strings, namely a first resistor string 81 and a second resistor string 82, each group has at least 255 resistors 08, 256 different reference voltages are divided between a highest reference voltage (V _ high, such as 4V) and a lowest reference voltage (V _ low, such as 0V) by using resistor division, the highest reference voltage of the first resistor string 81 is V _ disp _ high, and the lowest reference voltage is V _ disp _ low; the highest reference voltage of the second resistor string 82 is V _ comp _ high, and the lowest reference voltage is V _ comp _ low. The digital display signal is disp _ m and the digital compensation signal is comp _ m.

FIG. 3 shows how the resistor string generates 256 reference voltages with different magnitudes and performs gamma correction (gamma correction) in the prior art. Wherein the horizontal axis (X-axis) is the 8-bit number of the DAC input, from 0 to 255; the vertical axis (Y-axis) is 256 reference voltages, each corresponding to an 8-bit number for each input. V _ high is the highest voltage of the resistor string, and V _ low is the lowest voltage of the resistor string. If there are no intermediate 4 gamma correction voltages (V _ gamma0, V _ gamma1, V _ gamma2, and V _ gamma3), then the 8-bit input number for the reference voltage will be a straight line (curve L1). The voltage difference between each step (step) is

ΔV＝(V_high–V_low)/255 (1)

If 4 gamma correction voltages (V _ gamma0, V _ gamma1, V _ gamma2, and V _ gamma3) are inserted into the resistor string, a curve with gamma correction, i.e., a curve L2, can be generated. The middle insertion of 4 gamma correction voltages corresponds to DAC input values of G0, G1, G2 and G3. These 4 gamma correction voltages may force G0, G1, G2, and G3 to output reference voltages V _ gamma0, V _ gamma1, V _ gamma2, and V _ gamma3, respectively.

The line row DACs are generated by taking out the gamma correction voltages (V _ gamma0, V _ gamma1, V _ gamma2, and V _ gamma3) by placing the buffers that output the gamma correction voltages into a disabled state, which allows the buffers to output a floating state.

V _ gamma0 is inserted into the node of the resistor string output G0 to force the node to output V _ gamma0 voltage; v _ gamma1 is inserted into the node of the resistor string output G1 to force the node to output V _ gamma1 voltage; v _ gamma2 is inserted into the node of the resistor string output G2 to force the node to output V _ gamma 2; v _ gamma3 is inserted into the node of resistor string output G3, forcing the node to output V _ gamma3, which is the voltage.

The pixel units form an array, and the pixel units suitable for the off-pixel compensation display system need to have feedback channels, and aging information in the pixel units needs to be fed back to an aging signal detection module in the source driver 30 for aging detection.

The row scan driver 20 sends out row scan signals to the display address lines (corresponding to the display address signals) and the feedback address lines (corresponding to the feedback address signals), respectively. When the display address signal is asserted, the pixel circuit of the row connected to the display address line is turned on to write the signal (e.g., the correction signal or the compensated analog display signal) on the display signal line to the pixel cell connected thereto. When the feedback address signal is effective, the feedback channel of the pixel unit can be conducted, and the information of the aging or the uneven threshold voltage of the pixel unit is transmitted to the feedback signal line in the form of current or voltage.

The aging signal detection module is used for detecting whether the aging signal fed back from the pixel unit deviates from the expected aging degree. The detection result is a one-bit number, which represents that the expected aging degree is low or high, and the detection result is outputted to the controller 10 through the shift-out circuit, and the aging information memory is updated.

Since it is necessary to transfer the aging information in the pixel cell to the feedback signal line, the pixel cell circuit has a feedback channel output port and a control input port of the feedback channel, such as the third switching tube (Q3) of fig. 4, which forms the feedback channel connecting the pixel cell and the feedback signal line.

The Controller 10 includes an aging information memory, in addition to a function of controlling the source driver 30 and the line scan driver 20 to write the display signals in the time-sequence line-by-line gating pixel units by a time-sequence control module (Timing Controller) of the conventional display system, and each pixel unit can be subjected to various aging compensations according to the aging information, and a digital compensation value of each pixel unit is calculated by using a compensation algorithm. In addition, the controller 10 also receives the detection result of the pixel cell feedback voltage from the source driver 30.

The off-pixel compensated display system may perform two operations, a display operation and a corrective feedback detection operation. The display operation is generally the same as that of a conventional display system. The implementation details of the corrective feedback detection operation need to be matched to the design of the entire off-pixel compensated display system. The correction feedback detection operation may be performed when the display system is not performing the display operation. For example, after the display system is powered on, before the display screen starts displaying pictures, when the display screen is powered off and then power is supplied, or a blank period before frames or frames, or a period of time is specially scheduled for not performing display operation but performing correction feedback detection operation.

In the correction feedback detection operation, a display signal writing channel of a designated row pixel unit (or a part of pixel units of a certain row) is gated through a row scanning driver 20, and then a correction signal is written through a display signal line, wherein the correction signal can be from the controller 10 or a source driver 30 or generated in the source driver 30 of a local same channel, after the correction signal is written, the row scanning driver 20 gates the feedback channel of the row pixel unit, the aging information detection result detected by the detection module is latched in parallel, and then the aging information detection result is output to the controller 10 in series through a shift-out circuit, and then the aging information memory is updated.

In the present invention, the pixel unit 41 includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3 and a light emitting diode T1. The second switch tube Q2 in the pixel unit 41 in the nth row and the mth column is connected to the display address line 42 in the nth row and the display signal line 44 in the mth column; the second switching tube Q2, the driving tube Q1 and the third switching tube Q3 are connected in sequence; the light emitting diode T1 is connected between the driving tube Q1 and the third switching tube Q3; the third switching tube Q3 in the pixel unit 41 of the nth row and the mth column is connected to the feedback address line 43 of the nth row and the feedback signal line 45 of the mth column.

Specifically, as shown in fig. 4, an optional pixel unit 41 of the present invention includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3, and a light emitting diode T1; the second switching tube Q2, the driving tube Q1 and the third switching tube Q3 are N-shaped tubes. In the pixel unit 41 in the nth row and the mth column, the gate of the second switch Q2 is connected to the display address line 42 in the nth row, the first pole thereof is connected to the display signal line 44 in the mth column, and the second pole thereof is connected to the gate of the driving transistor Q1. A first pole of the driving transistor Q1 is connected to the operating voltage terminal VDD _ OLED thereof, and a second pole thereof is connected to the anode of the light emitting diode T1 and the first pole of the third switching transistor Q3; the operating voltage of the display panel may be different from the operating voltage of the source driver 30 or the row scan driver 20. The cathode of the led T1 is connected to its ground. The gate of the third switching transistor Q3 is connected to the feedback address line 43 of the nth row and the second pole thereof is connected to the feedback signal line 45 of the mth column.

Fig. 5 shows another optional pixel unit 41 of the present invention, which includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3 and a light emitting diode T1; the second switching tube Q2, the driving tube Q1 and the third switching tube Q3 are P-type tubes. The gate of the second switch Q2 in the pixel unit 41 of the nth row and the mth column is connected to the display address line 42 of the nth row, the first pole thereof is connected to the display signal line 44 of the mth column, and the second pole thereof is connected to the gate of the driving transistor Q1. The first pole of the driving transistor Q1 is connected to the cathode of the led T1 and the first pole of the third switching transistor Q3, and the second pole thereof is connected to the ground terminal thereof. The anode of the light emitting diode T1 is connected to the operating voltage terminal VDD _ OLED thereof. The gate of the third switching transistor Q3 is connected to the feedback address line 43 of the nth row and the second pole thereof is connected to the feedback signal line 45 of the mth column.

The driver Q1, the second switch Q2 and the third switch Q3 may be selected by those skilled in the art according to actual conditions, and the driver Q1, the second switch Q2 and the third switch Q3 may be transistors prepared by amorphous silicon, polysilicon, oxide semiconductor, organic semiconductor, thin film process, NMOS process, PMOS process or CMOS process, for example. When the specific types of the driving transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 are selected, the conventional circuit structure of the display panel can be formed by adaptively adjusting the connection relationship of the driving transistor Q1, the second switching transistor Q3832, and the third switching transistor Q3938, and the display panel can be designed by replacing the driving transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 with a certain type of transistor.

In the design process of a specific circuit structure, a person skilled in the art can use a source electrode of a transistor as a first pole and a drain electrode as a second pole; alternatively, the drain of the transistor may be a first electrode and the source may be a second electrode.

It should be understood by those skilled in the art that, in the present invention, the "feedback signal" may refer to "feedback voltage" hereinafter, and may also refer to "feedback information". In the following embodiments, the feedback information, the feedback signal and the feedback voltage may represent the aging information or the aging condition of the device.

The display system of the present invention is an out-of-pixel compensation dual DAC display system, alternatively referred to as an out-of-pixel compensation AMOLED display system.

The comparator of the detecting unit 32 in the present invention is a voltage comparator, and the detecting module 322 is a module for detecting aging information.

The Light Emitting device is a Light Emitting Diode, and may be an Organic Light Emitting Diode (OLED), or a quantum dot Light Emitting Diode (QLED), or a general type and other various types of LEDs (Light-Emitting Diode).

The aging information memory 13 can store various kinds of aging information.

The first embodiment is as follows:

fig. 6 is a schematic structural diagram of a conventional off-pixel compensation dual DAC display system, where M source driver modules 321 are provided inside a source driver, each source driver module 321 includes 2 DACs, i.e., a first DAC 61 and a second DAC 62, and the first DAC 61 and the second DAC 62 are respectively connected to the first shift-in circuit 34 and the second shift-in circuit 35. In a display operation of the conventional off-pixel compensation dual DAC display system, the first DAC 61 is used for converting the 8-bit digital display signal disp _ n _ m, and the second DAC 62 is used for converting the 8-bit digital compensation signal comp _ n _ m. disp _ n _ m represents a display signal of a pixel unit in the nth row and the mth column, and comp _ n _ m represents a compensation signal of a pixel unit in the nth row and the mth column. The 2 DACs convert the digital display signal and the digital compensation signal into an analog display signal (voltage) and an analog compensation signal (voltage), respectively, and the analog display signal and the analog compensation signal (voltage) are added by an analog adder 63 to form an analog compensated display signal, which is output to the display signal line of the mth column of pixel units. The analog compensated display signal is written into the pixel units of the nth row and the mth column which are gated by the scanning driver.

When the conventional off-pixel compensation dual DAC display system corrects the feedback detection operation, if the aging of the pixel cell driving transistor Q1 is to be detected, the compensated display signal 1 is written to the pixel cells of the target row through the display operation. Then, the feedback channel of the row of pixel units is turned on, the detection module 322 fixes the feedback signal line at a low voltage (e.g. 0.8V), which is lower than the threshold voltage of the OLED, so as to ensure that the OLED is turned off and turned on, and all the current of the driving transistor Q1 flows to the detection module 322 through the feedback signal line, so as to be compared with the reference current. The reference current is the current expected to be output by the driving transistor Q1 of the pixel cell 41 when the write compensated display signal is 1, and is also the current flowing to the OLED, assuming that the expected current is 10 nA. The digital signal with 1 bit of current comparison result is outputted to the controller through the shift-out circuit 33, and the aging data in the aging information memory of the controller is updated.

After the correction signal of the prior design is compensated, the driving tube Q1 feeds back the driving current of 10 nA. If not, the digital correction signal is adjusted according to the comparison result, and the current of 10nA is fed back by the driving tube Q1. The prior art design has a drawback in that the detection module 322 can only compare with one or a few (a limited number of) fixed reference signals (voltage or current), so that it is impossible to directly detect the threshold voltage of the OLED and the driving transistor Q1, because the threshold voltage of the OLED and the driving transistor Q1 is not fixed after aging, and the threshold voltage fed back to the detection module 322 cannot be changed to be close to the reference voltage by adjusting the compensation signal.

As shown in fig. 1 and fig. 7, the present embodiment is improved on the basis of the conventional external compensation display system shown in fig. 6, the display system of the feedback signal detection method of the present embodiment uses the pixel unit shown in fig. 4, the detection module 322 further includes a current source 73, and the current source 73 of the m-th column detection module 322 is respectively connected to each pixel unit 41 of the m-th column through the m-th column feedback signal line 45. In the mth column source driving module 321, the first dac 61 is connected to the analog adder 63, and the analog adder 63 is connected to the pixel unit 41 of the mth column driving channel through the display signal line 44. A display system designed according to fig. 7 can detect the OLED threshold voltage.

The positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45 and the current source 73, and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter 62 of the mth column source driving module 321.

When the aging phenomenon occurs after the light emitting diode T1 starts emitting light, the threshold voltage of the light emitting diode T1 shifts to a higher value. In order to detect the threshold voltage of the light emitting diode T1, in the detection method of this embodiment, first, 2 DACs are configured to be the same linear DAC, and one of the configuration methods is to disable all gamma voltages of the 2 resistor strings; or a selector is used to copy 256 output voltages from the compensation DAC (i.e., the second DAC, assuming the DAC is already linear) resistor string to the output of the display resistor string, and the output of the display resistor string needs to be disabled first, i.e., the command is sent

V_disp_0＝V_comp_0

V_disp_1＝V_comp_1

…

V_disp_255＝V_comp_255。

The feedback signal detection method of the embodiment is used for detecting the threshold voltage of the light emitting diode T1, and includes the following steps:

the first process is as follows: sequentially gating the writing channels of the pixel units in the 1 st row to the Nth row and carrying out detection operation when the writing channel of each row of pixel units is gated;

for the nth row of pixel units, as shown in fig. 9, the process of the detection operation specifically includes:

st1, the row scan driver 20 gates the write channel of the nth row of pixel cells.

St2, the pixel unit 41 is controlled to generate a feedback voltage and to control the second digital-to-analog converter 62 to output a comparison voltage.

Specifically, the first switch sw1 is closed, the second switch sw2 is opened, and the driving tube of the mth column is controlled to be turned off and turned on; the display signal line is disconnected from the output terminal of the analog adder, and 0V is input from the low power supply V1 to the display signal line, so that the driving transistor Q1 is turned off and on, and the analog adder 63, the first digital-to-analog converter 61, and the second digital-to-analog converter 62 are idle.

The result of detecting the threshold voltage of the light emitting diode obtained by the pixel unit 41 in the n-th row and the m-th column stored in the information memory 13 is output to the second digital-to-analog converter 62 in the m-th column, so that the second digital-to-analog converter 62 in the m-th column converts the result into a voltage signal.

The current source 73 outputs a preset small current, which may be 10nA, for example, to the light emitting diode T1 in the nth row and the mth column through the feedback channel. Since the current is small, after the feedback signal line is stabilized, the voltage on the feedback signal line can be considered to be equal to the threshold voltage of the light emitting diode.

The row scan driver 20 gates the feedback channels of the n-th row of pixel cells 41.

The obtained comparison voltage is the voltage obtained by the conversion of the second digital-to-analog converter 62 in the mth column, and the obtained feedback voltage of the pixel unit 41 in the nth row and the mth column is the voltage on the feedback signal line 45 in the mth column.

St3, comparator 72 compares the feedback voltage with the comparison voltage.

St4, the comparator 72 feeds back the detection result obtained by the comparison to the aging information memory 13 through the shift-out circuit 33, and the aging information memory 13 stores the detection result and updates the data.

And a second process: repeating the first process, as the first process is repeated, the input value of the dac 51 will steadily jump between K and K +1 in the following operation, and the final result of the comparison between the feedback voltage and the comparison voltage can be determined.

Those skilled in the art will appreciate that the first process may be repeated over and over again.

Example two:

as shown in fig. 1 and 8, the present embodiment is improved on the basis of the conventional external compensation display system shown in fig. 6, in which the first digital-to-analog converter 61 and the second digital-to-analog converter 62 originally connected to the analog adder 63 are respectively connected to the display signal line 44 and the comparator 72, and the display system of the feedback signal detection method of the present embodiment adopts the pixel unit shown in fig. 4; in the mth column source driving module 321, the first dac 61 is connected to the pixel unit 41 of the mth column driving channel through the display signal line 44. The analog adder 63 in the source driver module 321 is idle. (in addition, another design is to connect the left input port of the adder to the output of 61, and the right input port to 0V, so that the output voltage of the adder is the output voltage of 61. this effect is the same as connecting the output of 61 directly to the display signal line). The display system designed according to fig. 8 can detect the threshold voltage of the driving tube Q1.

The positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45, and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter 62 of the mth column detection unit 32.

In order to detect the threshold voltage of the driving transistor Q1, in the method of this embodiment, 2 DACs are configured as the same linear DAC, and one of the configuration methods is to disable all gamma voltages of the 2 resistor strings; or a selector is adopted to copy 256 output voltages of the compensation DAC (namely, the second digital-to-analog converter) resistor string to the output end of the display resistor string, and the output of the original display resistor string needs to be disabled firstly, namely, the command is transmitted

V_disp_0＝V_comp_0

V_disp_1＝V_comp_1

…

V_disp_255＝V_comp_255。

The feedback signal detection method of the embodiment is used for detecting the threshold voltage of the driving tube Q1, and comprises the following processes:

St2, the pixel cell is controlled to generate a feedback voltage and to control the second digital-to-analog converter to output a comparison voltage.

Specifically, the result of the driving tube source voltage Vs obtained by detecting the pixel unit 41 in the n-th row and the m-th column stored in the information memory 13 is output to the second digital-to-analog converter 62 in the m-th column through the second shift-in circuit 35; the second digital-to-analog converter 62 of the mth column is used to convert the result into a voltage signal.

And outputting a second preset display signal to the display signal line of the mth column, so as to turn on the driving tube Q1 and the light emitting diode T1 of the pixel unit 41 of the nth row and the mth column. The second predetermined display signal is a fixed value, such as 255.

The threshold voltage of the driving transistor Q1 is equal to the gate voltage Vg minus the source voltage Vs. The digital signal of the 8-bit DAC corresponding to the gate voltage Vg may be 255, and the digital signal of the 8-bit DAC corresponding to the source voltage Vs is one of the data stored in the aging memory.

The obtained feedback voltage of the pixel unit 41 in the nth row and the mth column is the voltage on the feedback signal line 45 in the mth column, i.e., the source voltage of the driving tube Q1, and the obtained comparison voltage is the voltage converted by the second digital-to-analog converter 62 in the mth column.

St3, comparator 72 compares the feedback voltage with the comparison voltage.

Fig. 9 is a schematic diagram of a feedback signal detection operation flow of the present invention, which is suitable for describing the detection operation of the display system in the first embodiment and the second embodiment, and the main difference of the method in the first embodiment and the second embodiment is the St2 process. For convenience of description and analysis, the detection operation herein is directed to the pixel units in the nth row and the mth column, and the pixel units in the nth row and the mth column are used as the target pixel units. The St1 process and the St2 process may be performed simultaneously.

The feedback signal detection method of the present invention includes the following processes:

for the nth row of pixel units, the detection operation process specifically includes:

st1, gating the write channel of the pixel cells of the nth row;

st2, controlling the pixel unit to generate a feedback voltage and controlling the reference dac to output a comparison voltage such that the first input terminal of the comparator receives the feedback voltage and the second input terminal of the comparator receives the comparison voltage;

st3, comparing the feedback voltage with the comparison voltage;

st4, controlling the comparator to feed back the detection result obtained by comparison to the aging information memory through the shift-out circuit;

and a second process: repeating process one, the input value of the dac 51 will steadily jump between K and K +1 in the following operation as process one is repeated. Those skilled in the art will appreciate that the first process may be repeated over and over again.

In the present invention, the positive input terminal of the comparator 72 may be set as the first input terminal, and the negative input terminal may be set as the second input terminal. St3 compares the feedback voltage with the comparison voltage by:

when the row scanning driver 20 performs the writing channel for gating each pixel unit in the nth row in the first scanning, the comparator 72 compares the comparison voltage with the feedback voltage;

if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 1, when the line scan driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to increase by the preset value k; if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 0, when the line scanning driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to be decreased by the preset value k;

after the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result that is inverted for the first time when the line scanning driver 20 performs a certain scanning round, if the result is inverted to 1 to 0 for the first time, when the nth line writing channel is gated next time, the comparison voltage is controlled to be reduced by 1; if the first inversion is 0 to 1, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

the row scanning driver 20 continues to repeatedly perform multiple scanning strobing on the pixel units in the 1 st row to the Nth row, and when the writing channel in the Nth row is strobed again, if the result of the last comparison is 1, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 0, the comparison voltage is controlled to be reduced by 1;

the line scan driver 20 continues to repeatedly perform multiple scanning strobes on the pixel units in the 1 st to nth rows until the writing channel in the nth row is subsequently strobed, and if the result output by comparing the feedback voltage with the comparison voltage with the value of K +1 is 0 and the result output by comparing the feedback voltage with the comparison voltage with the value of K is 1, a certain value between K and K +1 is taken as a final result. For example, an intermediate value between K and K +1, an average value, a value K, or a value K +1 may be used as the detection result, and the solution of the average value includes calculating an arithmetic scheme such as an arithmetic average value or a geometric average value. The operation "take a certain value between K and K +1 as the final result" can be performed by the timing control module 11, and can be determined by the skilled person.

For example, as shown in fig. 10, the display system uses the pixel cell shown in fig. 4, the comparison voltage is a DAC input value, first, a value is selected at the DAC input end, and after the value is assumed to start from 0, the DAC converts the DAC into an analog signal (voltage) corresponding to the value 0 and outputs the analog signal to the negative input end of the comparator 72, and the signal to be detected (i.e., the feedback voltage) is input to the positive input end of the comparator 72. If the result is 0, the selected voltage of the DAC is indicated to be higher, but the input of the DAC is already 0 and can not be lower any more, and the voltage which needs to be detected by the input is indicated to be beyond the detectable range. If 1, it means that the voltage selected by the DAC is not enough, k needs to be added to the input value of the DAC in the next comparison. Where k is an integer other than 0, e.g., 1. If the next round of comparison still yields a1, the DAC input value is again raised until the output of the comparator 72 is 0, indicating that the voltage corresponding to the input value selected by the DAC has exceeded the detected signal at the positive input of the comparator, which is the first flip.

As shown in fig. 10, the DAC value starts from 0 and the final achieved state should be: when the DAC value rises to K +1, the output result of the comparator 72 is 0, which indicates that the voltage selected by the DAC is larger than the compared voltage, and then the voltage selected by the DAC is reduced by 1 in the next comparison; when the DAC value is reduced to K, the output result of the comparator 72 is 1, which indicates that the voltage selected by the DAC is smaller than the compared voltage, and then the voltage selected by the DAC is added with 1 in the next comparison; the circulation is carried out in such a way to achieve the stability. Finally, the input value of the whole DAC is stabilized to jump between K and K +1, which shows that the compared voltage is between the voltages corresponding to K and K + 1.

Alternatively, the negative input of the comparator 72 may be set as the first input and the positive input may be set as the second input by those skilled in the art according to the actual requirements of the circuit design. Then, St3 compares the feedback voltage with the comparison voltage by:

if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 0, when the line scan driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to increase by the preset value k; if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 1, controlling the comparison voltage to decrease by a preset value k when the nth row writing channel is gated again in the second scanning by the row scanning driver 20;

after the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result that is inverted for the first time when the line scanning driver 20 performs a certain scanning round, if the result is inverted to 0 to 1 for the first time, when the nth line writing channel is gated next time, the comparison voltage is controlled to be reduced by 1; if the first inversion is 1 to 0, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

the row scanning driver 20 continues to repeatedly perform multiple scanning strobing on the pixel units in the 1 st row to the Nth row, and when the writing channel in the Nth row is strobed again, if the result of the last comparison is 0, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 1, the comparison voltage is controlled to be reduced by 1;

the line scan driver 20 continues to repeatedly perform multiple scanning strobes on the pixel units in the 1 st to nth rows until the writing channel in the nth row is subsequently strobed, and if the feedback voltage is compared with the comparison voltage with the value of K +1 to output a result of 1 and the feedback voltage is compared with the comparison voltage with the value of K to output a result of 0, then a certain value between K and K +1 is taken as a final result. For example, an intermediate value between K and K +1, an average value, a value K, or a value K +1 may be used as the detection result, and the solution of the average value includes calculating an arithmetic scheme such as an arithmetic average value or a geometric average value.

The invention provides a feedback signal detection method and an off-pixel analog domain compensation display system, wherein the system is an off-pixel compensation double-DAC display system, aging information fed back by a target pixel unit is detected by matching a digital-to-analog converter and a comparator of the off-pixel compensation display system, specifically, the threshold voltage of a light-emitting device and the threshold voltage of a driving tube in the pixel unit are detected, devices such as a TFT, an OLED, a QLED and the like can be detected, and further, the problems of device aging, uneven threshold voltage, uneven driving and the like are analyzed, so that the method is suitable for various products such as AMOLED, OLED-on-Silicon, QLED-on-Silicon, PMOLED, LCD driving chips, OLED lighting driving chips and the like.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. An off-pixel analog domain compensation display system of a feedback signal detection method is characterized in that,

comprises M rows of driving channels;

each column drive channel comprises a pixel unit (41) and a detection unit (32); the detection unit (32) comprises a source driving module (321) and a detection module (322); the detection module (322) comprises a comparator (72);

the system is an off-pixel compensation double-digital-to-analog converter display system, and a first digital-to-analog converter (61) and a second digital-to-analog converter (62) are arranged in the source driving module (321);

the source driving module (321) is connected to the pixel unit (41) through a display signal line (44);

a first input end of the comparator (72) is connected to the pixel unit (41) through a feedback signal line (45) and is used for receiving a feedback voltage corresponding to a feedback signal of the pixel unit (41); a second input terminal of the comparator is connected to the second digital-to-analog converter (62) for receiving the comparison voltage output by the second digital-to-analog converter (62); the output end of the comparator (72) is used for outputting a detection result obtained by comparing the feedback voltage with the comparison voltage;

wherein M is an integer of 1 or more.

2. The system of claim 1,

the display device also comprises a controller (10), a line scanning driver (20), a source driver (30) and a display panel (40);

the controller (10) is connected to the line scan driver (20) and the source driver (30);

the display panel (40) is provided with N rows and M columns of pixel units (41), and the row scanning driver (20) leads out N rows of display address lines (42) and feedback address lines (43); wherein, the display address line (42) and the feedback address line (43) of the nth row are respectively connected to each pixel unit (41) of the nth row; the row scanning driver (20) is used for receiving row control signals of the controller (10) and gating write-in channels of the pixel units in the 1 st row to the N th row through display address lines in the 1 st row to the N th row in sequence;

the source driver (30) comprises a first shift-in circuit (34), a second shift-in circuit (35), a shift-out circuit (33) and M detection units (32);

the controller (10), the first shift-in circuit (34) and a first digital-to-analog converter (61) in the mth column source driving module (321) are sequentially connected;

the controller (10), the second shift-in circuit (35) and a second digital-to-analog converter (62) in the m-th column source driving module (321) are sequentially connected;

the controller (10) is used for controlling a second digital-to-analog converter (62) in the mth column source driving module (321) to output a comparison voltage;

the output end of the m column comparator (72) is connected to the controller (10) through the shift-out circuit (33) and used for feeding back the detection result to the controller (10) through the shift-out circuit (33);

wherein N is an integer greater than or equal to 1, and N is an integer greater than or equal to 1 and less than or equal to N; m is an integer of 1 to M.

3. The system of claim 2,

the controller (10) comprises a time sequence control module (11), a compensation algorithm module (12) and an aging information memory (13) which are connected in sequence;

the time sequence control module (11), the first shift-in circuit (34) and a first digital-to-analog converter (61) in the mth column source driving module (321) are sequentially connected;

the compensation algorithm module (12), the second shift-in circuit (35) and a second digital-to-analog converter (62) in the m-th column source driving module (321) are connected in sequence;

the output end of the m-th row comparator (72), the shift-out circuit (33) and the aging information memory (13) are connected in sequence;

the pixel unit (41) comprises a second switching tube, a driving tube, a third switching tube and a light-emitting device;

in the pixel unit (41) of the nth row and the mth column, the second switch tube is connected to a display address wire (42) of the nth row and a display signal wire (44) of the mth column;

the second switching tube, the driving tube and the third switching tube are sequentially connected;

the light-emitting device is connected between the driving tube and the third switching tube;

the third switching tube is connected to a feedback address line (43) of the nth row and a feedback signal line (45) of the mth column.

4. The system of claim 2 or 3,

the first input end of the comparator (72) is a positive input end, and the second input end is a negative input end;

when the row scanning driver (20) gates a writing channel of the pixel units of the nth row, the comparator (72) is used for comparing the comparison voltage with the feedback voltage;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to increase by a preset value k; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to be reduced by a preset value k;

when the comparator (72) firstly inverts the comparison voltage and the feedback voltage to output a result, and if the result is inverted to 1 to 0 for the first time, the controller (10) controls the comparison voltage to be reduced by 1 when the nth row writing channel is next gated; if the first inversion is 0 to 1, when the nth row writing channel is gated next time, the controller (10) controls the comparison voltage to increase by 1;

when the nth row writing channel is gated again, if the last comparison result is 1, the controller (10) controls the comparison voltage to increase by 1; if the last comparison result is 0, the controller (10) controls the comparison voltage to be reduced by 1;

until the nth row of write channels is subsequently gated, comparing the feedback voltage with the comparison voltage with the value of K +1 to output a result of 0 and comparing the feedback voltage with the comparison voltage with the value of K to output a result of 1, and taking a certain value between K and K +1 as a final result;

or the first input end of the comparator (72) is a negative input end, and the second input end is a positive input end;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to increase by a preset value k; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to be reduced by a preset value k;

when the comparator (72) firstly inverts the comparison voltage and the feedback voltage to output a result, and if the result is inverted to 0 to 1 for the first time, the controller (10) controls the comparison voltage to be reduced by 1 when the nth row writing channel is gated next time; if the first inversion is 1 to 0, when the nth row writing channel is gated next time, the controller (10) controls the comparison voltage to increase by 1;

when the nth row writing channel is gated again, if the last comparison result is 0, the controller (10) controls the comparison voltage to increase by 1; if the result of the last comparison is 1, the controller (10) controls the comparison voltage to be reduced by 1;

until the nth row of write channels is subsequently gated, comparing the feedback voltage with the comparison voltage with the value of K +1 to output a result of 1 and comparing the feedback voltage with the comparison voltage with the value of K to output a result of 0, and taking a certain value between K and K +1 as a final result;

wherein K is a natural number greater than 0, and K is a natural number greater than 0.

5. The system of claim 3,

in the mth column of source driving modules (321), the first digital-to-analog converter (61) is connected to an analog adder (63), and the analog adder (63) is connected to the pixel units (41) of the mth column of driving channels through display signal lines (44);

the detection module (322) further comprises a current source (73), the current source (73) in the mth column is connected to each pixel unit (41) in the mth column through a feedback signal line (45) in the mth column;

the row scanning driver (20) is used for gating a writing channel of the pixel units (41) of the nth row;

the time sequence control module (11) is used for controlling the driving tubes in the mth row of driving channels to be switched on and off;

the compensation algorithm module (12) is used for outputting the result of the threshold voltage of the light-emitting device, which is stored in the information memory (13) and obtained by detecting the pixel units (41) of the nth row and the mth column, to a second digital-to-analog converter (62) of the mth column through the second shift-in circuit (35); a second digital-to-analog converter (62) of the mth column for converting the result into a voltage signal;

the current source (73) is used for outputting preset current to the light emitting device of the mth column;

the row scanning driver (20) is also used for gating a feedback channel of the pixel unit (41) of the nth row;

the m-th row comparator (72) is used for comparing a feedback voltage with a comparison voltage and feeding back a detection result to the information memory (13) through the shift-out circuit (33);

the feedback voltage of the pixel unit (41) in the nth row and the mth column is the voltage on the feedback signal line (45) in the mth column, and the comparison voltage is the voltage converted by the second digital-to-analog converter (62) in the mth column.

6. The system of claim 3,

in the mth column source driving module (321), the first digital-to-analog converter (61) is connected to the pixel unit (41) of the mth column driving channel through a display signal line (44);

the time sequence control module (11) is used for outputting a second preset display signal to an mth column display signal line so as to conduct a driving tube and a light-emitting device of the pixel unit (41) in the nth row and the mth column;

the compensation algorithm module (12) is used for outputting the result of the driving tube source voltage obtained by detecting the pixel units (41) in the nth row and the mth column stored in the information memory (13) to a second digital-to-analog converter (62) in the mth column through the second shift-in circuit (35); a second digital-to-analog converter (62) of the mth column for converting the result into a voltage signal;

7. A feedback signal detecting method applied to the display system according to claim 3, comprising:

the detection operation process comprises the following steps: when the writing channel of the pixel unit in the nth row is gated, controlling the pixel unit to generate a feedback voltage and controlling the second digital-to-analog converter to output a comparison voltage, so that the first input end of the comparator receives the feedback voltage corresponding to the feedback signal, and the second input end of the comparator receives the comparison voltage; comparing the feedback voltage with the comparison voltage; and controlling the comparator to feed back the detection result obtained by comparison to the aging information memory through the shift-out circuit.

8. The method of claim 7,

the process of comparing the feedback voltage and the comparison voltage is as follows:

when the row scanning driver (20) gates a writing channel of the pixel units of the nth row, controlling a comparator (72) to compare a comparison voltage with a feedback voltage;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, controlling the comparison voltage to increase by a preset value k when the nth row writing channel is gated again; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, controlling the comparison voltage to be reduced by a preset value k when the nth row writing channel is gated again;

when the comparator (72) firstly inverts the result output by comparing the comparison voltage with the feedback voltage, if the result is inverted to 1 to 0 for the first time, when the nth row writing channel is next gated, the comparison voltage is controlled to be reduced by 1; if the first inversion is 0 to 1, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

when the nth row writing channel is gated again, if the result of the last comparison is 1, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 0, the comparison voltage is controlled to be reduced by 1;

when the row scanning driver (20) gates the writing channel of each pixel unit in the nth row, the comparator (72) is controlled to compare the comparison voltage with the feedback voltage;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, controlling the comparison voltage to increase by a preset value k when the nth row writing channel is gated again; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, controlling the comparison voltage to reduce by a preset value k when the nth row writing channel is gated again;

when the comparator (72) firstly inverts the result output by comparing the comparison voltage with the feedback voltage, if the result is inverted to 0 to 1 for the first time, when the nth row writing channel is next gated, the comparison voltage is controlled to be reduced by 1; if the first inversion is 1 to 0, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

when the nth row writing channel is gated again, if the result of the last comparison is 0, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 1, the comparison voltage is controlled to be reduced by 1;

9. The method according to claim 7 or 8, for detecting a light emitting device threshold voltage,

the control pixel unit generates a feedback voltage and controls the second digital-to-analog converter to output a comparison voltage as follows:

controlling the driving tube of the mth column to be cut off and conducted;

outputting a result of previously detecting the threshold voltage of the light emitting device obtained by the pixel unit (41) of the nth row and the mth column stored in the information memory (13) to the second digital-to-analog converter (62) of the mth column, so that the second digital-to-analog converter (62) of the mth column converts the result into a voltage signal;

outputting a preset current to the light emitting device of the mth column;

gating a feedback channel of the pixel unit (41) of the nth row;

the obtained feedback voltage of the pixel unit (41) in the nth row and the mth column is the voltage on the feedback signal line (45) in the mth column, and the obtained comparison voltage is the voltage obtained by conversion of the second digital-to-analog converter (62) in the mth column.

10. The method of claim 7 or 8 for detecting a drive tube threshold voltage,

outputting the result of the driving tube source voltage obtained by detecting the pixel units (41) in the nth row and the mth column in the information memory (13) through the second shift-in circuit (35) to the second digital-to-analog converter (62) in the mth column, so that the second digital-to-analog converter (62) in the mth column converts the result into a voltage signal;

outputting a second preset display signal to an mth column display signal line so as to conduct a driving tube and a light-emitting device of the pixel unit (41) of the nth row and the mth column;

gating a feedback channel of the pixel unit (41) of the nth row;