CN112163386A - System-on-chip design and verification method based on remote FPGA experimental platform - Google Patents
System-on-chip design and verification method based on remote FPGA experimental platform Download PDFInfo
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- CN112163386A CN112163386A CN202011023030.6A CN202011023030A CN112163386A CN 112163386 A CN112163386 A CN 112163386A CN 202011023030 A CN202011023030 A CN 202011023030A CN 112163386 A CN112163386 A CN 112163386A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
Abstract
The invention discloses a system-on-chip design and verification method based on a remote FPGA experimental platform, which comprises the following steps: the method comprises the steps that a sampling chip is connected with FPGA equipment and is communicated with a user side through Websocket; the FPGA equipment is subjected to data sampling through the sampling chip, the data are transmitted to the user side, a bit stream file which is sent by the user side and used for carrying out system verification on the appointed FPGA equipment is received, the running result of the appointed FPGA equipment is fed back to the user side, and the system verification condition is determined by the user side according to the running result. The method can complete the design and verification of the system on chip without a complicated and tedious physical equipment connection process.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a system-on-chip design and verification method based on a remote FPGA experimental platform.
Background
An fpga (field Programmable Gate array), i.e. a field Programmable Gate array, is a product of further development on the basis of Programmable devices such as PAL, GAL, CPLD, etc. Due to the shortage of FPGA resources and the continuous development of the Internet, an FPGA remote experiment platform appears.
The existing RISC-v development based on the FPGA remote experimental platform can be operated only by directly and physically connecting an FPGA device. The problems exist that the physical connection is complicated and time-consuming, and the management and maintenance of resources are not easy when the FPGA needs to be applied in a large scale.
Disclosure of Invention
The invention aims to provide a system-on-chip design and verification method based on a remote FPGA experimental platform, which can complete the system-on-chip design and verification without a complicated and tedious physical equipment connection process.
The purpose of the invention is realized by the following technical scheme:
a system-on-chip design and verification method based on a remote FPGA experimental platform comprises the following steps: the system on chip is formed by a browser, a Web server, a raspberry group and an FPGA; the browser is in communication connection with the raspberry pi through the Web server, the raspberry pi is in one-to-one connection with the FPGA, and the input and output of the FPGA are directly connected with the GPIO interface of the corresponding raspberry pi;
the process of the system on chip comprises the following steps: the input of the FPGA is controlled through the browser, and the output of the FPGA is transmitted to the browser through the raspberry group;
the process of controlling the input of the FPGA through the browser comprises the following steps: the browser acquires an instruction triggered after a user clicks a corresponding button, sends a WebSocket data packet to a corresponding raspberry group according to the instruction requirement, informs the raspberry group to modify the corresponding GPIO interface level, and modifies the GPIO interface level according to information in the WebSocket data packet, so that the state of the FPGA is changed, and the output of the FPGA is further changed;
the process of transmitting the output of the FPGA to the browser by the raspberry group is as follows: after the output of the FPGA changes, the raspberry group detects the level change of the GPIO interface; and then, the raspberry sends a corresponding Websocket data packet to the browser, and the browser modifies the interface display according to the information in the Websocket data packet.
The technical scheme provided by the invention can solve the problem that RISC-v development based on an FPGA remote experimental platform in the prior art can be operated only by directly and physically connecting with FPGA equipment, and is convenient and time-saving; in addition, the running result of the FPGA can be obtained by directly uploading the bit stream file through an internet page, a complicated and tedious physical equipment connection process is not needed, and when a plurality of pieces of equipment are needed, the FPGA can run easily without pressure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flowchart of a system-on-chip design and verification method based on a remote FPGA experimental platform according to an embodiment of the present invention;
fig. 2 is a display interface of a browser according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a system-on-chip design and verification method based on a remote FPGA experimental platform, as shown in figure 1, the system-on-chip mainly comprises: the system comprises a browser, a Web server, a raspberry and an FPGA; the FPGA device can be regarded as a black box, and different outputs can be obtained only for different inputs;
the browser cannot directly communicate with the raspberry pie because the raspberry pie is only in the local area network, and the communication between the browser and the raspberry pie is in a Websocket connection mode, is similar to socket support two-way communication, is used for transmitting JSON information and is forwarded by a Web server.
Because websocket (ws) is based on the TCP protocol, TCP forwarding is used; for example, the WS sent to the 8080 port of the Web server is forwarded to the raspberry pi No. 1, and the WS sent to the 8081 port is forwarded to the raspberry pi No. 2, so that the WebSocket connection between the browser and the raspberry pi is indirectly realized.
Communication details of the system on chip: in WebSocket communication, two operations are involved: and the user controls the input of the FPGA through the browser and transmits the output of the FPGA to the browser, and the verification of the system on chip is finished after the two operations are finished. The input and the output of the FPGA are directly connected with a GPIO (general purpose IO interface) of the raspberry pi. The above two operations thus become: the user controls the GPIO interface of the raspberry group through the browser, and the raspberry group transmits the change of the GPIO interface to the browser. The former is simple, and the process is as follows: the browser acquires an instruction triggered after a user clicks a corresponding button, sends a WebSocket data packet to a corresponding raspberry group according to the instruction requirement, informs the raspberry group of modifying the level of a corresponding GPIO interface, and modifies the level of the GPIO interface according to information in the WebSocket data packet, so that the state of the FPGA is changed, and the output of the FPGA is further changed; the latter process is: after the output of the FPGA changes, the raspberry group detects the level change of the GPIO interface, then the raspberry group sends a corresponding WebSocket data packet to a browser, the browser modifies the interface display according to the information in the WebSocket data packet, and the difficulty in the process is to monitor the level change of the GPIO interface of the raspberry group; in the embodiment of the invention, the PiGPIO library is used for realizing the function, which is similar to edge triggering, the Web server only carries out TCP forwarding in the process, and the operation can be finished in a kernel with low cost, which is also the reason that the Web server can support hundreds of raspberry pies.
The main working flow is as follows:
firstly, a user selects equipment, different types of FPGA equipment can be selected in a machine room, and after the user selects the equipment in a browser, a corresponding engineering (constraint) file is created in a system background.
The content of the constraint file can be added by a user, different peripheral boards including an LED, a SWITCH, a BUTTON and the like are provided, when the user selects a peripheral, the corresponding executable code including the peripheral can be automatically generated, the executable code is put into an editable area on a browser of the user, and a basic code is automatically generated (assignment is carried out on assign a file interface to the peripheral). After freely editing the codes, a user clicks a 'comprehensive' button on the browser to produce a corresponding BIT stream file (the corresponding BIT stream file is a code which is generated by the corresponding code under Vivado and runs on a Xilinx FPGA development board, the purpose is that related codes are run on the FPGA development board, meanwhile, the constraint file is sent to a compiling server to be compiled, and whether the compiling is successful or not is prompted to return to the browser to be displayed. As shown in fig. 2, a display interface of a browser is provided, in which a plurality of display areas are provided, the top is an area for a user to input a BIT stream file, the middle area is an external status display and control area, and the bottom is a control area for generating a waveform diagram.
If the compiling is successful, the user can apply for an idle FPGA device through the browser and obtain a control page of a virtual peripheral on the browser, and the page has corresponding specific peripheral operations: the interface of the virtual peripheral is provided by an arm end, a raspberry pi is connected with an FPGA, the FPGA is sampled and then communicated with a browser through a Web server through the raspberry pi, and the communication detail part introduced in the description is obtained through the process.
The scheme solves the problem that RISC-v development based on an FPGA remote experimental platform in the prior art can be operated only by directly and physically connecting an FPGA device, and is convenient and time-saving; in addition, the running result of the FPGA can be obtained by directly uploading the bit stream file through an internet page, a complicated and tedious physical equipment connection process is not needed, and when a plurality of pieces of equipment are needed, the FPGA can run easily without pressure.
The scheme of the embodiment of the invention solves the problem that RISC-v development based on an FPGA remote experimental platform in the prior art can be operated only by directly and physically connecting with FPGA equipment, and is convenient and time-saving; in addition, the running result of the FPGA can be obtained by directly uploading the bit stream file through an internet page, a complicated and tedious physical equipment connection process is not needed, and when a plurality of pieces of equipment are needed, the FPGA can run easily without pressure.
Through the above description of the embodiments, it is clear to those skilled in the art that the above embodiments can be implemented by software, and can also be implemented by software plus a necessary general hardware platform. With this understanding, the technical solutions of the embodiments can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (3)
1. A system-on-chip design and verification method based on a remote FPGA experimental platform is characterized by comprising the following steps: the system on chip is formed by a browser, a Web server, a raspberry group and an FPGA; the browser is in communication connection with the raspberry pi through the Web server, the raspberry pi is in one-to-one connection with the FPGA, and the input and output of the FPGA are directly connected with the GPIO interface of the corresponding raspberry pi;
the process of the system on chip comprises the following steps: the input of the FPGA is controlled through the browser, and the output of the FPGA is transmitted to the browser through the raspberry group;
the process of controlling the input of the FPGA through the browser comprises the following steps: the browser acquires an instruction triggered after a user clicks a corresponding button, sends a WebSocket data packet to a corresponding raspberry group according to the instruction requirement, informs the raspberry group to modify the corresponding GPIO interface level, and modifies the GPIO interface level according to information in the WebSocket data packet, so that the state of the FPGA is changed, and the output of the FPGA is further changed;
the process of transmitting the output of the FPGA to the browser by the raspberry group is as follows: after the output of the FPGA changes, the raspberry group detects the level change of the GPIO interface; and then, the raspberry sends a corresponding Websocket data packet to the browser, and the browser modifies the interface display according to the information in the Websocket data packet.
2. The system-on-chip design and verification method based on the remote FPGA experimental platform is characterized in that the function of detecting the GPIO interface level by the raspberry pi is realized by a PiGPIO library.
3. The system-on-chip design and verification method based on the remote FPGA experimental platform is characterized in that the WebSocket data packet is realized based on a TCP protocol.
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| CN110166975A (en) * | 2019-06-20 | 2019-08-23 | 内蒙古大学 | Agriculture internet of things sensors communication means based on wireless network and raspberry pie node |
| CN111694309A (en) * | 2020-06-18 | 2020-09-22 | 中国科学技术大学 | Method for realizing FPGA (field programmable Gate array) online platform |
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| US20140028784A1 (en) * | 2012-07-26 | 2014-01-30 | Google Inc. | Method and Apparatus Providing Synchronization and Control for Server-Based Multi-Screen Videoconferencing |
| CN110166975A (en) * | 2019-06-20 | 2019-08-23 | 内蒙古大学 | Agriculture internet of things sensors communication means based on wireless network and raspberry pie node |
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