CN112162242B - Beam control equipment and beam control method of phased sparse array radar - Google Patents
Beam control equipment and beam control method of phased sparse array radar Download PDFInfo
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- CN112162242B CN112162242B CN202011129106.3A CN202011129106A CN112162242B CN 112162242 B CN112162242 B CN 112162242B CN 202011129106 A CN202011129106 A CN 202011129106A CN 112162242 B CN112162242 B CN 112162242B
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Abstract
The invention relates to a beam control device based on a phased array sparse array radar, and belongs to the field of phased array radar beam pointing control. According to the invention, the FPGA main control chip of the embedded control board is used for adjusting and programming the autonomous programming software, and the hardware adder and the multiplier of the FPGA main control chip are used for realizing the pipelined two-stage operation of the FPGA main control chip, so that the calculation rate is greatly improved, the control cost of the subsystem equipment on the sparse array wave beam is effectively reduced, the processing time is short, the overall performance of the system is improved, and the method is very suitable for carrying out wave beam control processing on a large-scale sparse array antenna array surface with irregularly circulated wave beam phase-shifting values; the manufacturing cost of the equipment is reduced. The problems that the prior art is long in calculation time, the system beam control efficiency is greatly reduced, the equipment is expensive, and the development and development of corresponding beam control equipment are not facilitated are perfectly solved.
Description
Technical Field
The invention relates to beam control equipment and a beam control method of a phased sparse array radar, and belongs to the field of phased array radar beam pointing control.
Background
The modern radar with two-dimensional phase scanning function and sparse array antenna array surface has the advantages that the antenna array of the sparse array antenna array surface is in random irregular installation state, so that the beam phase shift value among the antenna array is not corresponding to the law and can be circulated, the phase shift value of each antenna array must be calculated specifically one by one, the calculated array surface phase shift value is packed and issued through a specific communication interface, and finally, the beam calculation and external control communication functions are completed through a computer blade. However, under the conditions that the antenna array surface is large, the antenna array has more antenna elements, and the wave beam phase shift value is irregular and can circulate, the calculation time of the computer blade can be prolonged, thereby reducing the wave beam control efficiency of the system; meanwhile, the cost of the computer blade combination equipment is high, which is not beneficial to the development and development of corresponding beam control equipment. Therefore, for some subsystems or systems with larger array surfaces which need to control the cost, the beam control equipment and the beam control method which are adaptive to the large-scale sparse array antenna array surface beam control are designed and manufactured, the high-efficiency beam control requirement is met, the calculation processing function is improved, the subsystem control cost is effectively reduced, the structure is scientific and reasonable, and the phase control sparse array radar with high reliability is used.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the beam control equipment and the beam control method of the phased sparse array radar, which meet the requirement of high-efficiency beam control, improve the computing processing capacity, effectively reduce the subsystem control cost, have scientific and reasonable structure and strong use reliability, and are suitable for beam control processing of a large-scale sparse array antenna array surface; the overall wave control calculation efficiency of the system is greatly improved, and the cost is effectively reduced.
The invention realizes the aim through the following technical scheme:
the beam control device of the phased sparse array radar comprises a shell, a cover plate, an aviation plug connector, an embedded control board and a power module; the embedded control board mainly comprises an FPGA main control chip, an optical module combination, an RS422 driving transceiver chip combination, an on-board external electric connector, a program memory, a power chip combination, an on-board test port, a crystal oscillator combination, an on-board control switch, a status indicator lamp and an on-board debugging/programming interface;
the FPGA main control chip is connected with the optical module combination through a GXP high-speed serial IO port, respectively connected with the debugging/programming interface and the program memory through special programming and debugging IO interfaces, respectively connected with the RS422 drive transceiver chip combination, the on-board external electric connector, the on-board control switch, the on-board test port and the status indicator lamp through a common IO interface, and connected with the crystal oscillator combination through a special clock IO port, and correspondingly connected with the power input pins of each functional chip on the board;
The FPGA main control chip is connected with the RS422 through an on-chip common IO pin to drive the transceiver chip combination, the RS422 drives the transceiver chip combination to be connected with an on-board external electric connector, the on-board external electric connector is connected with RS422 communication signals, the power chip combination is connected with the on-board external electric connector, a +5V direct current power supply is connected with the on-board external electric connector, and various voltage power supplies required by the operation of all components on the board are generated according to the connected +5V direct current power supply; the FPGA main control chip is respectively connected with an on-board test port, an on-board control switch and a status indicator lamp through on-chip common IO pins; the FPGA main control chip is connected with the crystal oscillator combination through an on-chip special clock IO pin; the FPGA main control chip is used for debugging, burning and storing the autonomous programming software through the on-board debugging/burning interface and the program memory, and the FPGA main control chip is used for controlling the combined work of the state indicator lamp, the on-board test port, the optical module combination and the RS422 driving transceiver chip through the autonomous programming software and the on-board control switch; the power module is connected with an alternating current 220V power supply through the aviation plug connector, and generates a direct current power supply of +5V to be connected with an on-board external electric connector of the embedded control board; the aviation plug connector is connected with an electric connector on the embedded control board to transmit RS422 communication signals.
The program memory chip adopts an SPI serial bus mode, programs running on the FPGA main control chip are programmed into the program memory chip, and the programs running on the FPGA main control chip are loaded into the FPGA main control chip when the embedded control board is powered on each time.
The optical module combination is composed of three single-mode double-channel optical modules of the same type, and the embedded control board completes external high-speed optical communication through the optical module combination.
The power chip combination is composed of 5 power chips with three different types, and various voltage power supplies required by normal operation of the embedded control board are generated.
The crystal oscillator combination is a combination of a 125MHz differential output crystal oscillator and a 50MHz single-ended output crystal oscillator, wherein the 125MHz differential output crystal oscillator is used as a basic clock for high-speed serial communication transmission of an embedded control board, and the 50MHz single-ended output crystal oscillator is used as a basic clock for intelligent control, high-speed calculation and other partial communication functions of the embedded control board.
The on-board external electric connector completes external RS422 serial port communication transmission and reference power signal transmission.
The on-board control switch is matched with the corresponding circuit to output stable 0 and 1 digital signals, and the FPGA main control chip on the embedded control board is matched with the programs in the chip to realize different communication functions according to the digital signals.
The FPGA main control chip selects an FPGA chip of an Inter company, the FPGA has enough on-chip hardware resources, and the FPGA chip in the embedded control board jointly completes various intelligent control, communication and calculation functions through the resources on the chip. The power chip combination generates various voltage power supplies required by normal operation of the embedded control board, receives externally input direct current +5V voltage, generates direct current voltage required by +3.3V, +2.5V, +1.5V, +1.1V and +0.9V embedded control board, and is composed of 5 power chips of three different types to complete related power conversion operation, wherein +3.3V voltage power supplies are directly generated through a first power chip, +2.5V and +1.5V voltage power supplies are respectively generated through a second power chip, and +1.1V and +0.9V voltage power supplies are respectively generated through a third power chip. The power module is used for converting alternating current 220V power supply into +5V direct current power supply required by the embedded control board, and the +5V direct current power supply is used as a reference power supply of the embedded control board. The RS422 drives the transceiver chip to complete TTL and RS422 level conversion of the embedded control board and perform RS422 communication externally. The hardware part of the on-board debugging/programming interface mainly provides connection support for the software development stage of the embedded control board, and updates and debugs the program running on the FPGA main control chip through the on-board debugging/programming interface. The status indicator lamp displays different colors according to the working condition, and visually displays the working state of the embedded control panel, so that an operator can recognize the working state of the embedded control panel at the first time. The two aviation connectors are used for being linked with other external subsystems or devices to transmit RS422 communication signals and standard alternating current 220V power signals, and the two aviation connectors are used in the device, so that the two aviation connectors have good smoke resistance, moisture resistance, mildew resistance and sand and dust resistance.
The beam control method of the beam control device of the phased sparse array radar is characterized by comprising the following steps of: the method is mainly realized through the following steps:
step 1), an FPGA main control chip determines whether to drive a transceiver chip combination and an RS422 serial communication interface through an RS422 or to communicate with a main control subsystem through an optical module combination and a GXB high-speed serial communication interface according to an on-board control switch of an embedded control board; the FPGA main control chip is started to receive and decode the position coordinate values which are issued by the main control subsystem and are related to the centers of the sparse array antenna array relatively to the array surface, and receives and decodes the beam horizontal pointing value, the beam vertical pointing value and the array surface pointing control values which are issued by the main control subsystem and are related to the centers of the sparse array antenna array relatively to the centers of the sparse array antenna array in real time;
step 2), the FPGA main control chip stores coordinate values with the accuracy of 1mm of each sparse array antenna array element received and decoded into an on-chip RAM of a program controller of the FPGA main control chip through autonomous programming software burnt in by an on-board debugging/programming interface;
step 3), the FPGA main control chip builds a minimum unit increment calculation software module in the FPGA main control chip through adder and multiplier hardware according to an adjacent unit shift increment formula, and autonomous programming software of the program controller transmits a received decoded array wave beam pointing message to the minimum unit increment calculation software module to generate an adjacent horizontal minimum unit shift increment value and an adjacent vertical minimum unit shift increment value, and transmits the adjacent horizontal minimum unit shift increment value and the adjacent vertical minimum unit shift increment value to a calculation software module of the next stage;
And 4) constructing an array phase offset value calculation software module in the FPGA main control chip by an adder and multiplier hardware according to an array phase offset formula, and introducing each array coordinate value issued by the on-chip RAM in the step 2) and the horizontal and vertical increment values generated by the minimum unit increment calculation software module in the step 3) into the array phase offset value calculation software module to generate the beam phase displacement direction value of each sparse array antenna array.
Step 5), the embedded control board software packages the generated wave beam phase shift directional value, the current frequency point value, the component number and other control receiving and transmitting component control codes of each sparse array antenna array according to a certain communication protocol, and then transmits the wave beam phase shift directional value, the current frequency point value, the component number and other control receiving and transmitting component control codes to an antenna feed-through network through an RS422 serial communication interface or a high-speed optical communication interface switched by an on-board control switch, so that wave beam control of an antenna feed-through subsystem is completed.
Compared with the prior art, the invention has the beneficial effects that:
the beam control equipment and the beam control method of the phased sparse array radar are mainly constructed by taking the embedded control board with low cost, the whole length is 255mm, the width is 280mm, the height is 66mm, the structure is scientific and reasonable, the use reliability is strong, the automatic programming software is adjusted and programmed in the FPGA main control chip of the embedded control board is mainly realized through five steps of the invention, the pipelined two-stage operation of the FPGA main control chip is realized through the hardware adder and the multiplier of the FPGA main control chip, the calculation rate is greatly improved, the control cost of subsystem equipment on sparse array beams is effectively reduced, the system processing time is saved, the whole performance of the system is improved, and the method is very suitable for carrying out the beam control treatment on a large-scale sparse array antenna array surface with irregular beam phase shift values; the system has simple structure and greatly reduces the manufacturing cost of the system equipment. The problems that the prior art faces large array surface and large sparse array surface antennas with more antenna array elements and irregular and circulating beam phase shift values greatly reduce the beam control efficiency of the system due to the fact that the calculation time of a computer blade is prolonged, and the computer blade combination equipment is high in cost and is unfavorable for the development and development of corresponding beam control equipment are solved perfectly.
Drawings
Fig. 1 is a schematic diagram of the overall structure of a beam steering apparatus of the present invention;
FIG. 2 is a flow chart of the process of the autonomous programming software of the beam steering method of the present invention;
FIG. 3 is a schematic diagram of a system connection of the working scenario of the present invention;
fig. 4 is an assembled schematic view of the beam steering apparatus of the present invention;
fig. 5 is a schematic diagram of an assembly structure of the embedded control board.
In fig. 1: 1. an embedded control board, a power module, a 3 and an aviation plug connector; 100. the device comprises an FPGA main control chip, 101, an optical module combination, 102, an on-board debugging/programming interface, 103, a program memory, 104 and RS422, a transceiver chip combination, 105, an on-board external electric connector, 106, a power chip combination, 107, an on-board test port, 108, an on-board control switch, 109, a status indicator lamp, 110 and a crystal oscillator combination.
Detailed Description
Specific embodiments of the beam control apparatus and beam control method of the phased sparse array radar are set forth in further detail below (see fig. 1-5) in conjunction with the accompanying drawings:
(see fig. 1) the beam control device and the beam control method of the phased sparse array radar, wherein the beam control device of the phased sparse array radar comprises a shell, a cover plate, an embedded control board 1, a power module 2 and an aviation plug connector 3; the number of the aviation plug connectors 3 is two, and the embedded control board 1 mainly comprises an FPGA main control chip 100, an optical module combination 101, an on-board debugging/programming interface 102, a program memory 103, an RS422 driving transceiver chip combination 104, an on-board external electric connector 105, a power chip combination 106, an on-board test port 107, an on-board control switch 108, a status indicator lamp 109 and a crystal oscillator combination 110;
The FPGA main control chip 100 is connected with the optical module combination 101 through a GXP high-speed serial IO port, the FPGA main control chip 100 is respectively connected with the upper debugging/programming interface 102 and the program memory 103 through special programming and debugging IO interfaces, and the FPGA main control chip 100 is respectively connected with the RS422 drive transceiver chip combination 104, the on-board external electric connector 105, the on-board test port 107, the on-board control switch 108 and the status indicator lamp 109 through common IO interfaces; the FPGA main control chip 100 is connected with the crystal oscillator combination 110 through a special clock IO port, and the power chip combination 106 is correspondingly connected with power input pins of all functional chips on the board;
the FPGA main control chip 100 is connected with the RS422 through an on-chip common IO pin to drive the transceiver chip assembly 104, the RS422 drives the transceiver chip assembly 104 to be connected with the on-board external electric connector 105, the RS422 is accessed to a communication signal through the on-board external electric connector 105, the power chip assembly 106 is connected with the on-board external electric connector 105, a +5V direct current power supply is accessed through the on-board external electric connector 105, and various voltage power supplies required by the operation of all components on the embedded control board 1 are generated according to the accessed +5V direct current power supply; the FPGA main control chip 100 is respectively connected with an on-board test port 107, an on-board control switch 108 and a status indicator lamp 109 through on-chip common IO pins; the FPGA main control chip 100 is connected with the crystal oscillator combination 110 through an on-chip special clock IO pin; the FPGA main control chip 100 is used for debugging, burning and storing autonomous programming software through the on-board debugging/burning interface 102 and the program memory 103, and the FPGA main control chip 100 is used for controlling the state indicator lamp 109, the on-board test port 107, the optical module combination 101 and the RS422 to drive the transceiver chip combination 104 to work through the autonomous programming software and the on-board control switch 108; the power module 2 is connected with an alternating current 220V power supply through an aviation plug connector 3, and generates a direct current power supply of +5V to be connected with an on-board external electric connector 105 of the embedded control board 1; the other air plug connector 3 is connected with the on-board electrical connector 105 of the embedded control board 1 to transmit the RS422 communication signal.
The FPGA main control chip 100 is an FPGA chip of an Inter company, and the model of the FPGA main control chip 100 is as follows: the model chip has 644 common PIO pins, 16 high-speed GXB transceiving serial hardware cores, 16 pairs of high-speed differential special pins, 140600 logic basic components, 16 global clocks, 115 DSP modules and 11430kb of on-chip storage space, and the FPGA main control chip 100 in the embedded control board 1 jointly completes various intelligent control, communication and calculation functions through the resources on the chip.
The chip of the program memory 103 is selected from chips with model number M25P64VMF6 of ST company, the memory space of the chip is 64Mbit, serial bus transmission of SPI is adopted, the maximum clock rate of 50MHz is greater than 10 ten thousand times of data erasing times, the data retention time is greater than 20 years, and the embedded control board 1 loads the running program of the FPGA main control chip 100 into the FPGA main control chip 100 mainly when the running program is powered on through the memory chip.
The optical module combination 101 is an optical module of Wu Hanyong company, the optical module combination 101 is composed of three optical modules with the same model, and the model of the optical module is as follows: the optical wavelength of the TLP310M02G, the optical wavelength of the optical communication of the optical module is 1310nm, and the emitted optical power is: -5dBm to 0 dBm, the light receiving sensitivity is: -18dBm, a transmission communication rate as high as 2.5Gbps, and a working temperature of-40 ℃ to +85 ℃, wherein the embedded control board 1 mainly completes external high-speed optical communication through the optical module combination 101.
The power chip assembly 106 is used for generating various voltage power supplies required by normal operation of the embedded control board 1, the power chip assembly 106 receives externally input direct current +5V voltage to generate direct current voltage required by +3.3V, +2.5V, +1.5V, +1.1V, +0.9V embedded control board 1, the power chip assembly 106 uses a power chip of LINEAR company, the model is 'LT 1764 EQ-3.3', the model is 'TPS 75901 KTT', the model is 'PTH 05000W', and the model is 'PTH 05000W'; the corresponding power supply generating function is completed, wherein +3.3V voltage power supply is directly generated through a power supply chip 'LT 1764 EQ-3.3', +2.5V and +1.5V voltage power supply are respectively generated through two power supply chips 'TPS 75901 KTT' and peripheral configuration resistors thereof, and +1.1V and +0.9V voltage power supply are respectively generated through two power supply chips 'PTH 05000W' and peripheral configuration resistors thereof.
The RS422 driving transceiver chip combination 104 selects a chip with the model of MAX3077EESA of MAXIM company, the chip is a full-duplex RS422 differential driving transmission chip, the highest transmission rate is 16Mbps, the maximum signal driving transmission delay is 50ns, and the embedded control board 1 completes the communication function of the external RS422 through the RS422 driving chip.
The crystal oscillator combination 110 is a combination of a 125MHz differential output crystal oscillator and a 50MHz single-ended output crystal oscillator, the 125MHz differential output crystal oscillator in the embedded control board 1 is mainly used as a basic clock for high-speed serial communication transmission of the embedded control board 1, the 50MHz single-ended output crystal oscillator is mainly used as a basic clock for intelligent control, high-speed calculation and other partial communication functions of the embedded control board 1, the 125MHz crystal oscillator model is SiT9121AI-2D2-25E125.000MHz in the northeast of Hubei, and the 50MHz crystal oscillator model is ZPB-26-15-3.3-50 in 707 factories.
The on-board external electric connector 105 is selected from DB25SLS of 850 factories, the rated current of a contact element of the on-board external electric connector 105 is 5A, the withstand voltage is 1000V, the insulation resistance is more than or equal to 5000MΩ, the service life of 500 plugging cycles is prolonged, and the embedded control board 1 mainly completes the functions of communication and reference power signal transmission of an external RS422 serial port through the on-board external electric connector 105.
The on-board control switch 108 is a DM-08 of macro-electronic company, the switch is a finger-dialing switch, the rated current is 25mA, the rated voltage is 24V, the insulation resistance is 100MΩ, and the finger-dialing service life of 2000 times is used as the control switch on the embedded control board 1, the on-board control switch 108 outputs stable digital signals of 0 and 1 in cooperation with corresponding circuits, and the FPGA main control chip 100 on the embedded control board 1 realizes different communication functions in cooperation with programs in the chip according to the digital signals.
The status indicator lamp 109 is 'BT 315 HTJ' of the Ruipnorthc photoelectron company, the status indicator lamp 109 is a controllable 'red' and 'blue' double-color status indicator lamp, the embedded control board 1 controls the display state of the status indicator lamp 109 according to the working condition, and the display of the working state of the embedded control board 1 is intuitively displayed for an operator, so that the operator can identify the working state of the embedded control board 1 at the first time.
The hardware part of the on-board debugging/programming interface 102 mainly provides support for the embedded control board 1 in the software development stage, and the on-board debugging/programming interface 102 updates and debugs the running program of the FPGA main control chip 100, so that the interface is not used after the version of the running program is normal.
The power module 2 is mainly used for converting an alternating current 220V power supply into a +5V direct current power supply required by the embedded control board 1, the +5V direct current power supply is used as a reference power supply of the embedded control board 1, the power module 3 is a power module with the model of 4NIC-K15 (5V 3A) A of the Kogyo power company, and the power module 2 can output a path of constant voltage direct current 5V and a power supply with the maximum current 3A.
The aerial plug connector 3 is mainly used for linking other external subsystems or equipment and is used for transmitting RS422 communication signals and standard alternating current 220V power signals, two aerial plug connectors 3 are used in the equipment, namely an XCD30F35Z1D1 and an XCD18F4Z1D1 of a middle-aviation photoelectric 158 factory company, the two aerial plug connectors 3 are respectively an XCD30F35Z1D1 and an XCD18F4Z1D1 aerial plug connector 3, wherein the XCD30F35Z1D1 is used for transmitting the RS422 communication signals, the connector is a 35-core needle flange type tail unthreaded aerial plug connector 3, rated working current is 5A, rated working voltage is 500V, insulation resistance is equal to or more than 5000MΩ, mechanical life is 1000 times, the XCD18F4Z1D1 is used for transmitting alternating current 220V power signals, the connector is a 4-core needle flange type threaded type aerial plug connector 3, rated current 25A-300A, rated working voltage is 500V, resistance is equal to or more than 5000MΩ, and the connector has good dust and dust preventing performances and sand preventing performances.
(see fig. 2 and 3) the beam control device and the beam control method of the phased sparse array radar are characterized in that: the method is mainly realized through the following steps:
step 1) the embedded control board 1 provides two external data communication modes: RS422 communication mode and high-speed optical communication mode, the embedded control board 1 is connected with a superior master control subsystem and a next-stage antenna feed-through network by cables or optical fibers according to the specific communication mode (RS 422 communication or optical communication) of the current system, and meanwhile, the switch 108 is controlled on the board of the embedded control board 1: i.e. a dial switch, which switches the functional program module in the embedded control board 1 to perform different processes on the data to be received or transmitted, wherein the SA1-1 state of the on-board control switch 108 of the embedded control board 1 is "1": the mark on side is: 0, the other side is 1, the embedded control board 1 is externally connected with a main control subsystem through RS422 communication, processes and decodes a communication signal issued by a received main control through a general Uart serial receiving processing software module, when the SA1-1 state of the on-board control switch 108 is 0, the embedded control board 1 is externally connected with the main control subsystem through optical fiber communication, processes and decodes a communication signal issued by the received main control through a high-speed GXB serial receiving processing software module, wherein when the SA1-2 state of the on-board control switch 108 of the embedded control board 1 is 1, the embedded control board 1 is communicated with an external antenna feed-through RS422, processes and packages a communication signal to be transmitted to an antenna feed-through network control instruction through the general Uart serial transmitting processing software module, and when the SA1-2 state of the on-board control switch 108 is 0, the embedded control board 1 is externally connected with the main control subsystem through optical fiber communication, processes and packages a communication signal to be transmitted to an antenna feed-through network control instruction through the high-speed GXB serial transmitting processing software module; according to the determined communication receiving processing software module, the FPGA main control chip 100 of the embedded control board 1 decodes the position coordinate value of each sparse array antenna array relative to the array center and the array surface pointing control value such as the beam horizontal pointing value, the beam vertical pointing value, the frequency point value and the like required by each sparse array antenna array center according to the communication protocol section of the main control subsystem part of the radar full-machine communication protocol version 2.03, wherein the position coordinate value system of each sparse array antenna array relative to the array center is started and issued once, and other array surface pointing control values are issued once every radar period.
Step 2), the FPGA main control chip 100 stores coordinate values with the accuracy of 1mm of each sparse array antenna array which is received and decoded into an on-chip RAM module of the FPGA main control chip 100 through autonomous programming software burnt in by the on-board debugging/programming interface 102; the antenna array coordinate value is an x-axis distance value and a y-axis distance value of an array relative to the center of an array surface; the autonomous programming software program of the FPGA main control chip 100 takes the array number as a write address through a dual-port RAM control IP core module, takes the x-axis distance value and the y-axis distance value as storage data, and simultaneously stores the values into the defined RAM on the FPGA main control chip 100.
Step 3), the FPGA main control chip 100 builds a minimum unit increment calculation software module in the FPGA main control chip 100 through adder and multiplier hardware according to an adjacent unit shift increment formula, and the autonomous programming software of the program controller 103 transmits a received decoded relevant control message of an array wave beam pointing message, a frequency value and an antenna inclination angle value to the minimum unit increment calculation software module every radar period, generates an adjacent horizontal minimum unit shift increment value and an adjacent vertical minimum unit shift increment value, and transmits the adjacent horizontal minimum unit shift increment value and the adjacent vertical minimum unit shift increment value to a calculation software module of the next stage;
The minimum unit increment calculation formula is as follows:
wherein: x: elevation angle value of the sparse array surface when the main tower is unfolded and erected; for a determined sparse array, the value is a fixed value. dx: horizontal minimum cell distance; for a determined sparse array, the value is a fixed value. dy: vertical minimum cell distance; for a determined sparse array, the value is a fixed value. K: in order to ensure a calculated precision weighting value, the value is a fixed value for a determined sparse array surface. A: sparse array plane horizontal beam pointing. B: sparse array plane vertical beam pointing. Lambda: the wavelength value corresponding to the electromagnetic wave of the current frequency point. Alpha: horizontal minimum unit delta value. Beta: vertical minimum unit delta value.
Step 4) the FPGA main control chip 100 builds an array phase offset value calculation software module in the FPGA main control chip 100 through adder and multiplier hardware according to an array phase offset formula, reads the x-axis distance and y-axis distance coordinate values of each array stored in the on-chip RAM in step 2) in sequence by taking an array number as a reading address in each radar period, and brings the read coordinate values and the horizontal and vertical increment values issued by the minimum unit increment calculation software module calculated in step 3) into the array phase offset value calculation software module to generate beam phase displacement directional values of each antenna array of a sparse array surface;
The phase offset calculation formula of each sparse array antenna array is as follows:
Kfs=m*α+n*β
Kjs= m*α
alpha: a horizontal minimum unit increment value;
beta: a vertical minimum unit delta value;
m: horizontal coordinates corresponding to each sparse array antenna array;
n: vertical coordinates corresponding to each sparse array antenna array;
kfs: a value of a transmit wave control phase offset corresponding to each sparse array antenna element;
kjs: and receiving the value of the wave control phase offset corresponding to each sparse array antenna array.
Step 5) the embedded control board 1 software generates beam phase shift direction values, current working frequency point values, component numbers and other control transceiver component control codes of each generated sparse array surface antenna array, the beam control communication signals of the sparse array surface array are generated after processing by a general Uart serial transmission processing software module according to the switch state selection of SA1-2 of an on-board control switch 108 on the embedded control board 1, or the beam control communication signals of the sparse array surface array are generated after processing by a high-speed GXB serial transmission processing software module, and the high-speed optical communication interface is generated after processing by the RS422 serial communication interface. And the message package in the sending processing software module follows the content of the section of the communication protocol of the antenna feed subsystem of the radar full-machine communication protocol version 2.03. And finally, after the beam control communication signals of the sparse array area array are distributed by the antenna feed-through communication subsystem, the beam control communication signals are sent to the receiving and transmitting assemblies of each antenna feed-through path, so that the transmission and the reception of each path of channel radar beam of each path of receiving and transmitting assembly are controlled, and the beam control of the sparse array area radar is completed.
The following is a detailed statement of the beam control apparatus and beam control method of the phased sparse array radar:
the beam control device switches the mode of external decoding communication of the FPGA main control chip 100 of the embedded control board 1 through the 1 st bit and the 2 nd bit of the SA1 of the on-board control switch 108 of the embedded control board 1, and the application of the beam control device in a scene determines the communication mode through the SA1 of the on-board control switch 108 of the embedded control board 1, an external RS422 interface and an optical interface according to the communication characteristic of an actual system, and after a fixed communication mode is selected, the system is unchanged forever.
The conditions of the communication usage scenario corresponding to the different states of the on-board control switch 108 of the embedded control board 1 are as follows:
1) SA 1-2 of the on-board control switch 108 is '00', and an RS422 communication interface is used for communicating with an upper-level main control subsystem, and an RS422 communication interface is used for communicating with a lower-level antenna feed-through subsystem;
2) SA 1-2 of the on-board control switch 108 is '01', and uses an RS422 communication interface to communicate with an upper-level main control subsystem and uses an optical communication interface to communicate with a lower-level antenna feed-through subsystem;
3) SA 1-2 of the on-board control switch 108 is 10, and an optical communication interface is used for communicating with an upper-level main control subsystem and an RS422 communication interface is used for communicating with a lower-level antenna feed-through subsystem;
4) SA 1-2 of the on-board control switch 108 is "11", and uses the optical communication interface to communicate with the upper level master control subsystem and uses the optical communication interface to communicate with the lower level antenna feed-through subsystem.
The autonomous programming software program constructed by the software modules of the beam control device and the beam control method of the phased sparse array radar is matched with the FPGA main control chip 100.
The autonomous programming software program of the beam control device and the beam control method of the phased sparse array radar mainly carries out software development on the FPGA main control chip 100 through a "quick II" software development environment.
According to the characteristics of the FPGA main control chip 100, the beam control device of the invention enables software modules of all functional units in the embedded control board 1 to run in parallel.
(see fig. 2), fig. 2 is a related description of signal relationships among functional software unit modules in the beam control apparatus and the beam control method of the present invention.
The beam control device of the invention has four communication receiving and transmitting processing software modules:
a) General Uart serial receive processing software module: the software module is used for receiving serial-parallel software modules built according to the requirements of the Uart serial communication bus interface protocol, and simultaneously, the software module rearranges the data after serial-parallel decoding into each control message and each information message according to the whole machine communication protocol.
b) General Uart serial transmission processing software module: the software module transmits and deserializes various control messages and information messages which need to be issued according to the requirements of the Uart serial communication bus interface protocol, and the software module rearranges and deserializes the control messages and the information messages according to the whole machine communication protocol.
c) High-speed GXB serial receiving processing software module: the high-speed GXB serial receiving processing software module built by the special 'GXB high-speed serial bus decoder IP core' of the FPGA main control chip 100 is utilized, and meanwhile, the software module rearranges the received data into each control message and each information message according to the whole machine communication protocol.
d) High-speed GXB serial transmission processing software module: the high-speed GXB serial transmission processing software module built by utilizing the specific 'GXB high-speed serial bus encoder IP core' of the FPGA main control chip 100, and meanwhile, the software module rearranges various control messages and information messages required to be transmitted according to a whole machine communication protocol and then transmits the rearranged control messages and information messages to the module for high-speed serial transmission.
The beam control device of the invention comprises two communication switching processing software modules:
1) Control communication decoding software module: by receiving the switch control on the external board, the data issued by the general Uart serial receiving processing software module or the data issued by the high-speed GXB serial receiving processing software module are switched to the calculation software module and the data storage software module of the next stage.
2) The module wave control communication coding software module: the method comprises the steps of switching a transmitting and receiving beam control message generated by a computing software module and other forwarded component control messages by receiving external on-board switch control, transmitting the beam control message to a general Uart serial transmitting processing software module or a high-speed GXB serial transmitting processing software module, and finally transmitting a generated communication signal
The beam control device of the present invention has two computing software modules in a pipelined relationship:
a) The minimum unit increment calculation software module: the hardware adder and multiplier provided by the FPGA master chip 100 are used to move to a calculation software module built by an increment formula according to a standard adjacent unit, wherein the accuracy values of the horizontal minimum unit and the vertical minimum unit are 1mm, and the calculation software module is carried into calculation.
b) Each array phase offset value calculation software module: and a calculation software module built according to a standard array phase offset formula is used by using a hardware adder and a multiplier provided by the FPGA main control chip 100, wherein the calculation is performed according to the value traversal issuing in the communication trigger RAM.
The beam control device is provided with a data storage software module, and is mainly constructed by using a special dual-port RAM controller IP core of the FPGA main control chip 100 and an inherent RAM storage sheet of the FPGA main control chip 100, and is used for controlling and storing coordinate position data of each array of a sparse antenna array surface relative to the center of the array surface, and the beam control device has better universality by adopting a starting configuration mode; the beam control device is adapted to more types of radar systems through the change of starting-up data, and can be used on the corresponding radar systems.
(see fig. 4 and 5) are schematic diagrams of the hardware components of the beam steering apparatus of the present invention and the connection relationship between them.
The beam control device hardware composition of the invention comprises: the aerial plug connector 3, the power module 2 and the FPGA main control chip 100; a power chip assembly 106; a crystal oscillator assembly 110; program memory 103: model number EPCS64; optical module combination 101: maximum rate 3G, wavelength 1310nm; an on-board debug/write interface 102 for JTAG and AS; on-board external electrical connector 105: DB-25; an on-board control switch, status indicator lights, reset buttons, and an on-board test port 107 connector.
The beam control device of the invention has two communication interfaces outside:
common serial communication interface: the communication rate is 115200bps, the data is 10 bits per frame, and the data composition is as follows: 1-bit start bit, 1-bit stop bit, 8-bit valid bit.
Optical fiber high-speed communication interface: the optical module combination 101 is used for carrying out optical communication externally, after the optical module combination 101 mutually converts optical signals and high-speed electric signals, the optical signals are directly connected to a high-speed serial bus pin of the FPGA main control chip 100, and then encoding and decoding are carried out through a GXB high-speed serial core built by the FPGA main control chip 100, wherein the high-speed serial communication rate is as follows: 2.5Gbps, 16 bits of each frame of data are valid bits, and the serial transmission bottom layer adopts an 8b/10b coding mode.
Examples:
the on-board control switch 108 of the embedded control board 1 is used for switching the external communication interface of the equipment into high-speed optical communication, namely the equipment is used for communicating the upper-level main control subsystem and the lower-level communication subsystem only through high-speed optical signals.
All system equipment including the main control extension and the embedded control board 1 is powered on, the starting main control subsystem transmits coordinate information of each sparse array to the special-type bright wave beam control equipment through optical signals, the embedded control board 1 converts the received optical signals into high-speed electric signals through the optical module combination 101 on the board and transmits the high-speed electric signals to the FPGA main control chip 100 of the embedded control board 1 through a special high-speed serial channel, and the FPGA main control chip 100 stores the received coordinate information of the relevant sparse array in the on-chip RAM of the FPGA main control chip 100.
After the storage of the front-stage array coordinate information is completed, the embedded control board 1 receives the array plane central beam pointing signal and the frequency signal and other time sequence signals issued by the main control subsystem through the board light module combination 101 every radar period, and decodes according to a certain communication protocol.
The embedded control board 1 transmits the decoded array plane central beam pointing signal, the frequency signal and the array coordinate information stored in the RAM to a beam phase shift operation module of a two-stage pipeline stage built in the FPGA main control chip 100 for operation, and finally generates the transmitting and receiving phase shift vector values required by each antenna array.
Finally, the embedded control board 1 packages the calculated transmitting and receiving phase shift directional values of each array element of the array surface and control messages of other receiving and transmitting components according to a certain protocol, forwards the control messages through an optical fiber via an antenna feed-through network, and finally, the communication is controlled to transmit and receive the wave beams of the sparse array surface in the receiving and transmitting components of each path of the antenna feed-through array surface, so that the wave beam control of the sparse array radar is completed.
Claims (8)
1. A beam control device of a phased sparse array radar comprises a shell, a cover plate, an embedded control board (1), a power module (2) and an aviation plug connector (3); the embedded control board (1) mainly comprises an FPGA main control chip (100), an optical module combination (101), an on-board debugging/programming interface (102), a program memory (103), an RS422 driving transceiver chip combination (104), an on-board external electric connector (105), a power chip combination (106), an on-board test port (107), an on-board control switch (108), a status indicator lamp (109) and a crystal oscillator combination (110);
the method is characterized in that: the FPGA main control chip (100) is connected with the optical module combination (101) through a GXP high-speed serial IO port, the FPGA main control chip (100) is respectively connected with the debugging/programming interface (102) and the program memory (103) on the board through special programming and debugging IO interfaces, the FPGA main control chip (100) is respectively connected with the RS422 driving transceiver chip combination (104), the on-board external electric connector (105), the on-board test port (107), the on-board control switch (108) and the status indicator lamp (109) through common IO interfaces, the FPGA main control chip (100) is connected with the crystal oscillator combination (110) through a special clock IO port, and the power chip combination (106) is correspondingly connected with power input pins of all functional chips on the embedded control board (1);
The FPGA main control chip (100) is connected with the RS422 through an on-chip common IO pin to drive the transceiver chip assembly (104), the RS422 drives the transceiver chip assembly (104) to be connected with the on-board external electric connector (105), the RS422 communication signal is accessed through the on-board external electric connector (105), the power chip assembly (106) is connected with the on-board external electric connector (105), the +5V direct current power supply is accessed through the on-board external electric connector (105), and various voltage power supplies required by the operation of all components on the board are generated according to the accessed +5V direct current power supply; the FPGA main control chip (100) is respectively connected with an on-board test port (107), an on-board control switch (108) and a status indicator lamp (109) through on-chip common IO pins; the FPGA main control chip (100) is connected with the crystal oscillator combination (110) through an on-chip special clock IO pin; the FPGA main control chip (100) is used for debugging, burning and storing autonomous programming software through the on-board debugging/burning interface (102) and the program memory (103), and the FPGA main control chip (100) is used for controlling the state indicator lamp (109), the on-board test port (107), the optical module combination (101) and the RS422 to drive the transceiver chip combination (104) to work through the autonomous programming software and the on-board control switch (108); the power module (2) is connected with an alternating current 220V power supply through the aviation plug connector (3) and generates a direct current power supply of +5V to be connected with an external electrical connector (105) on the embedded control board (1); the aviation plug connector (3) is connected with an on-board external electric connector (105) on the embedded control board (1) to transmit RS422 communication signals.
2. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the program memory (103) chip adopts an SPI serial bus mode, programs running on the FPGA main control chip (100) are programmed into the SPI serial bus mode, and the programs running on the FPGA main control chip (100) are loaded into the FPGA main control chip (100) when the embedded control board (1) is powered on each time.
3. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the optical module combination (101) is composed of three single-mode double-channel optical modules of the same type, and the embedded control board (1) completes external high-speed optical communication through the optical module combination (101).
4. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the power chip combination (106) is composed of 5 power chips with three different types, and various voltage power supplies required by normal operation of the embedded control board (1) are generated.
5. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the crystal oscillator combination (110) is a combination of a 125MHz differential output crystal oscillator and a 50MHz single-ended output crystal oscillator, wherein the 125MHz differential output crystal oscillator is used as a basic clock for high-speed serial communication transmission of the embedded control board (1), and the 50MHz single-ended output crystal oscillator is used as a basic clock for intelligent control, high-speed calculation and other partial communication functions of the embedded control board (1).
6. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the on-board external electric connector (105) completes external RS422 serial port communication transmission and reference power signal transmission.
7. The beam control method of the beam control device of the phased sparse array radar according to claim 1, characterized by: the on-board control switch (108) is matched with the corresponding circuits to output stable digital signals of 0 and 1, and the main control FPGA chip (100) on the embedded control board (1) is matched with programs in the chip to realize different communication functions according to the digital signals.
8. A beam control method of a beam control device of a phased sparse array radar is characterized by comprising the following steps of: the beam control device of the phased sparse array radar comprises a shell, a cover plate, an embedded control board (1), a power module (2) and an aviation plug connector (3); the embedded control board (1) mainly comprises an FPGA main control chip (100), an optical module combination (101), an on-board debugging/programming interface (102), a program memory (103), an RS422 driving transceiver chip combination (104), an on-board external electric connector (105), a power chip combination (106), an on-board test port (107), an on-board control switch (108), a status indicator lamp (109) and a crystal oscillator combination (110); the FPGA main control chip (100) is connected with the optical module combination (101) through a GXP high-speed serial IO port, the FPGA main control chip (100) is respectively connected with the debugging/programming interface (102) and the program memory (103) on the board through special programming and debugging IO interfaces, the FPGA main control chip (100) is respectively connected with the RS422 driving transceiver chip combination (104), the on-board external electric connector (105), the on-board test port (107), the on-board control switch (108) and the status indicator lamp (109) through common IO interfaces, the FPGA main control chip (100) is connected with the crystal oscillator combination (110) through a special clock IO port, and the power chip combination (106) is correspondingly connected with power input pins of all functional chips on the embedded control board (1); the FPGA main control chip (100) is connected with the RS422 through an on-chip common IO pin to drive the transceiver chip assembly (104), the RS422 drives the transceiver chip assembly (104) to be connected with the on-board external electric connector (105), the RS422 communication signal is accessed through the on-board external electric connector (105), the power chip assembly (106) is connected with the on-board external electric connector (105), the +5V direct current power supply is accessed through the on-board external electric connector (105), and various voltage power supplies required by the operation of all components on the board are generated according to the accessed +5V direct current power supply; the FPGA main control chip (100) is respectively connected with an on-board test port (107), an on-board control switch (108) and a status indicator lamp (109) through on-chip common IO pins; the FPGA main control chip (100) is connected with the crystal oscillator combination (110) through an on-chip special clock IO pin; the FPGA main control chip (100) is used for debugging, burning and storing autonomous programming software through the on-board debugging/burning interface (102) and the program memory (103), and the FPGA main control chip (100) is used for controlling the state indicator lamp (109), the on-board test port (107), the optical module combination (101) and the RS422 to drive the transceiver chip combination (104) to work through the autonomous programming software and the on-board control switch (108); the power module (2) is connected with an alternating current 220V power supply through the aviation plug connector (3) and generates a direct current power supply of +5V to be connected with an external electrical connector (105) on the embedded control board (1); the aerial plug connector (3) is connected with an on-board external electric connector (105) on the embedded control board (1) to transmit RS422 communication signals;
The beam control method is mainly realized through the following steps:
step 1), an FPGA main control chip (100) of an embedded control board (1) determines whether to drive a transceiver chip combination (104) and an RS422 serial communication interface through an RS422 or to communicate with a main control subsystem through an optical module combination (101) and a GXB high-speed serial communication interface according to an on-board control switch (108); the FPGA main control chip (100) is started to receive and decode the position coordinate values which are issued by the main control subsystem and are related to the centers of the sparse array antenna array relative to the array surface, and receives and decodes the beam horizontal pointing value, the vertical pointing value and the frequency point value array surface pointing control value which are issued by the main control subsystem and are related to the centers of the sparse array antenna array in real time;
step 2), the FPGA main control chip (100) stores coordinate values with the accuracy of 1mm of each sparse array antenna array received and decoded into an on-chip RAM of a program controller (103) of the FPGA main control chip (100) through autonomous programming software burnt in by an on-board debugging/programming interface (102);
step 3), the FPGA main control chip (100) builds a minimum unit increment calculation software module in the FPGA main control chip (100) through adder and multiplier hardware according to an adjacent unit increment formula, autonomous programming software of the program controller (103) transmits a received decoded array wave beam pointing message to the minimum unit increment calculation software module, generates an adjacent horizontal minimum unit increment value and an adjacent vertical minimum unit increment value, and transmits the adjacent horizontal minimum unit increment value and the adjacent vertical minimum unit increment value to a calculation software module of the next stage;
Step 4), the FPGA main control chip (100) builds an array phase offset value calculation software module in the FPGA main control chip (100) through adder and multiplier hardware according to an array phase offset formula, and brings each array coordinate value issued by the on-chip RAM in the step 2) and a horizontal increment value and a vertical increment value generated by the minimum unit increment calculation software module in the step 3) into the array phase offset value calculation software module to generate a beam phase offset directional value of each sparse array antenna array;
step 5) the embedded control board (1) software packages the generated beam phase shift direction value, the current frequency point value, the component code number and other control transceiver component control codes of each sparse array antenna array according to a certain communication protocol, and then transmits the packaged beam phase shift direction value, the current frequency point value, the component code number and other control transceiver component control codes to an antenna feed-through network through an RS422 serial communication interface or a high-speed optical communication interface switched by an on-board control switch (108), so as to complete the beam control of the antenna feed-through subsystem.
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