CN112153481A - Video data processing method, computer device, and storage medium - Google Patents
Video data processing method, computer device, and storage medium Download PDFInfo
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- CN112153481A CN112153481A CN202010856228.6A CN202010856228A CN112153481A CN 112153481 A CN112153481 A CN 112153481A CN 202010856228 A CN202010856228 A CN 202010856228A CN 112153481 A CN112153481 A CN 112153481A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
- H04N21/64—Addressing
- H04N21/6405—Multicasting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/14—Systems for two-way working
- H04N7/15—Conference systems
Abstract
The present application relates to a video data processing method, a computer device, and a storage medium. The method comprises the following steps: a first processor in the at least two processors acquires video data and acquires a second processor identifier corresponding to the video data; the system bus assembly determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification; and the system bus assembly adds the second processor identification to a multicast group corresponding to the target multicast group identification, and the first processor sends the video data to the second processor which is added to the multicast group through the system bus assembly, so that the second processor processes the video data. The method can reduce the occupied performance of the processor when processing the video data.
Description
Technical Field
The present application relates to the field of multimedia communication technologies, and in particular, to a video data processing method, apparatus, computer device, and storage medium.
Background
With the development of multimedia technology and video processing technology, professional video conference systems have strong requirements in traditional applications and also have new requirements in industries such as distance education and digital courts. Professional video conference terminals also have higher requirements, and users want to provide more video processing capacity to meet various application scenes of the users. However, the conventional method for processing video data by a processor has the problem of high occupied performance.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a video data processing method, apparatus, computer device and storage medium, which can reduce the performance occupied by a processor when processing video data.
A video data processing method is applied to computer equipment comprising at least two processors and a system bus assembly, wherein the system bus assembly is respectively connected with each processor of the at least two processors; the method comprises the following steps:
a first processor in the at least two processors acquires video data and acquires a second processor identifier corresponding to the video data;
the system bus assembly determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification;
and the system bus assembly adds the second processor identification to a multicast group corresponding to the target multicast group identification, and the first processor sends the video data to the second processor which is added to the multicast group through the system bus assembly, so that the second processor processes the video data.
In one embodiment, the system bus component is a high speed serial computer expansion bus component;
the system bus component determines a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifiers, including:
the high-speed serial computer expansion bus component acquires a multicast group identifier corresponding to a second processor identifier from a mapping relation between the second processor identifier and the multicast group identifier;
and the high-speed serial computer expansion bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification.
In one embodiment, the high speed serial computer expansion bus component stores a mapping of multicast group address ranges to multicast group identifications;
the method for acquiring the multicast group identifier corresponding to the second processor identifier from the mapping relationship between the second processor identifier and the multicast group identifier stored by the high-speed serial computer expansion bus component comprises the following steps:
the high-speed serial computer expansion bus component determines a corresponding target multicast group address range according to the second processor identification;
and the high-speed serial computer expansion bus component determines the multicast group identification corresponding to the target multicast group address range according to the mapping relation.
In one embodiment, the second processor identification is an address identification in the high speed serial computer expansion bus tree.
In one embodiment, the first processor transmitting the video data to a second processor joining the multicast group via the system bus component comprises:
the first processor transmitting the video data to the high speed serial computer expansion bus component;
the high-speed serial computer expansion bus assembly receives video data sent by the first processor and encapsulates the video data into a transaction layer data packet by adopting a high-speed serial computer expansion bus protocol;
the high speed serial computer expansion bus component sends the transaction layer packet to the second processor joining the multicast group.
In one embodiment, the system bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification, including:
when the number of the second processor identifications is at least two, the system bus component determines a target processor identification according to the service type of the video data;
and the system bus component takes the multicast group identification corresponding to the target processor identification as the target multicast group identification.
A computer device comprising at least two processors and a system bus component, the system bus component being connected to each of the at least two processors, respectively;
a first processor of the at least two processors is used for acquiring video data and acquiring a second processor identifier corresponding to the video data;
the system bus component is used for determining a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifiers;
the system bus component adds the second processor identification to a multicast group corresponding to the target multicast group identification;
the first processor is configured to send the video data to a second processor joining the multicast group through the system bus component, and the second processor is configured to process the video data after receiving the video data.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
a first processor in the at least two processors acquires video data and acquires a second processor identifier corresponding to the video data;
the system bus assembly determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification;
and the system bus assembly adds the second processor identification to a multicast group corresponding to the target multicast group identification, and the first processor sends the video data to the second processor which is added to the multicast group through the system bus assembly, so that the second processor processes the video data.
In the video data processing method, the computer device and the storage medium, the first processor of the at least two processors acquires the video data and the second processor identifier corresponding to the video data, that is, the processor to be received is designated before the video data is sent, the system bus component selects the target multicast group identifier from the multicast group identifiers corresponding to the receiving processor identifier and adds the processor identifier to the multicast group corresponding to the target multicast group identifier, so that the video data can be sent to the second processor of the multicast group at the same time, the video data of one processor can be distributed to other processors for video processing, the problem that the system performance occupied by the single processor is too high can be solved, and the resource occupation can be reduced.
Drawings
FIG. 1 is a diagram of an exemplary video data processing system;
FIG. 2 is a flow diagram illustrating a method for video data processing according to one embodiment;
FIG. 3 is a flow diagram illustrating the transmission of video data in one embodiment;
FIG. 4 is a schematic diagram of a computer apparatus in one embodiment;
FIG. 5 is a diagram illustrating hardware processing of a video data processing method according to an embodiment;
FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The video data processing method provided by the application can be applied to the application environment shown in fig. 1. The computer device 100 includes a first processor 110, a second processor 120, and a system bus assembly 130. The system bus component 130 is a separate computer bus and is the primary component that connects the processors. For example, the number of the first processor 110 and the second processor 120 may be unlimited. The system bus assembly 130 is coupled to the first processor 110 and the second processor 120, respectively. And the system bus component 130 may be located in the first processor 110 or in the second processor 120. The processor containing the system bus components may act as the master processor. The computer device 100 may be a terminal device, and may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices.
In one embodiment, because the processor performance of the embedded system is limited, the video processing capabilities such as encoding and decoding are limited, and the processing of videos in the professional video conference system is relatively complex, when processing such as video encoding, video decoding, local multi-channel picture splicing, multi-channel far-end picture and local multi-channel picture splicing display or encoding and the like needs to be performed on more than 64 large-scale video data, the performance of a Central Processing Unit (CPU) is poor and cannot meet the requirements. And because the video conference belongs to strong interactive application, the processing capacity of multiple paths of videos directly influences the use experience of users, so that the current embedded high-definition video conference terminal has certain limitation.
In one embodiment, as shown in fig. 2, a video data processing method is provided, which is illustrated by applying the method to the computer device 100 in fig. 1, and includes the following steps:
in step 202, a first processor of the at least two processors acquires video data and acquires a second processor identifier corresponding to the video data.
Wherein the first processor is a processor that transmits video data. The first processor may be any one of the processors in the computer device, and may also be configured according to the service type. The video data may be a single video or multiple videos. The second processor is not the same processor as the first processor. And the second processor identification is an identification of the processor to be received. The second processor identification may be an identification of a processor in the computer device other than the first processor identification to which said first processor corresponds.
Specifically, a first processor of the at least two processors obtains video data and obtains a second processor identification corresponding to the video data. I.e. before the first processor sends the video data, it is specified to which processor the video data needs to be sent. For example, the first processor is an a processor, the second processor identifier may be B, C, and the corresponding to-be-received processors are a B processor and a C processor.
In step 204, the system bus component determines a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifier.
Wherein the second processor identification is for uniquely identifying the processor in the computer device. The second processor identification may be at least one of a number, a word, a letter, and a symbol. The number of second processor identifications is at least one. Each second processor identification has a corresponding multicast group identification. And each second processor identification is not the same as the corresponding multicast group identification. For example, the multicast group identifier corresponding to the processor a is multicast group 0; the multicast group identification for the B processor is not limited to multicast group 1 …. The multicast group identifier is an identifier corresponding to the multicast group joined by the second processor.
Specifically, when the number of second processor identifications is one, the system bus component takes the second processor identification as the target processor identification. When the number of the second processor identifications is at least two, the system bus component may use any one of the second processor identifications as a target processor identification, and use a multicast group identification corresponding to the target processor identification as a target multicast group identification.
In step 206, the system bus component adds the identifier of the second processor to the multicast group corresponding to the identifier of the multicast group, and the first processor sends the video data to the second processor joining the multicast group through the system bus component, so that the second processor processes the video data.
Multicast, also known as multicast, targeted broadcast, is a form of transmission used in networks that allows for the delivery of a message to a selected subset of all possible destinations, i.e., to deliver information to a variety of addresses as specified. Multicasting is a method of communicating between a sender and multiple receivers. The multicast group includes an identification of the second processor to receive the video data.
Specifically, the system bus component adds the second processor identification to the multicast group corresponding to the multicast group identification. I.e., the multicast group includes the second processor identification and the second processor has joined the multicast group. The first processor sends video data to a second processor that is joined in the multicast group via the system bus component to identify the corresponding second processor. And the second processor processes the video data after receiving the video data.
In this embodiment, the processing the video data by the second processor includes: the second processor performs at least one of splicing, encoding and scaling on the video. For example, the second processor includes a B processor, a C processor, and a D processor, and the B processor may perform a splicing process, the C processor may perform an encoding process, the D processor may perform a scaling process, and the like, but is not limited thereto.
In this embodiment, each processor may transmit video data in a DMA (Direct Memory Access) manner. Where a DMA transfer copies data from one address space to another. When the processor initiates this transfer, the transfer itself is performed and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Such operations do not stall the processor's work, but may instead be rescheduled to process other work. DMA transfers are important for high performance embedded system algorithms and networks.
According to the video data processing method, the first processor of the at least two processors acquires the video data and the second processor identification corresponding to the video data, namely the to-be-received processor is appointed before the video data is sent, the system bus assembly selects the target multicast group identification from the multicast group identifications corresponding to the to-be-received processor identification and adds the to-be-received processor identification into the multicast group corresponding to the target multicast group identification, so that the video data can be sent to the second processor in the multicast group at the same time, the video data of one processor can be distributed to other processors for video processing, the problem that the system performance occupied by the single processor is too high can be solved, the resource occupation is reduced, the video processing delay is reduced, the system stability is improved, and better use experience is presented to users.
In one embodiment, the video conference application includes a plurality of video processing scenes, such as a local single-path acquisition local display, a local multi-path acquisition splicing code sent to a far-end, a far-end picture and a local picture splicing display. In order to meet the use scenes, a single processor cannot process multiple paths of video data, a PCIe component is required to be used among multiple processors to transmit original video data, one path of video can distribute the data to different processors to be processed according to different service scenes, and PCIe communication among traditional processors adopts a one-to-one transmission mode and cannot simultaneously meet the video processing service with low delay and flexible switching. A way of implementing video data transmission via the system bus components is therefore proposed. The system bus component determines a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifier, including: the high-speed serial computer expansion bus component acquires a multicast group identifier corresponding to the second processor identifier from the stored mapping relation between the second processor identifier and the multicast group identifier; the high speed serial computer expansion bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification.
Among them, the high-speed serial computer expansion bus component, namely pcie (peripheral component interconnect Express), also called PCI-Express, is a high-speed serial computer expansion bus standard. The PCI bus uses a parallel bus structure, all the external devices on the same bus share the bus bandwidth, and the PCIe bus uses a high-speed differential bus and adopts an end-to-end connection mode, so that only two devices can be connected in each PCIe link. This makes the topology adopted by PCIe and PCI buses different.
Specifically, a mapping relationship between the second processor identification and the multicast group identification is stored in the high speed serial computer expansion bus component. And the high-speed serial computer expansion bus component acquires the multicast group identification corresponding to each second processor identification from the mapping relation between the second processor identification and the multicast group stored in the high-speed serial computer expansion bus component. The high speed serial computer expansion bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification. For example, if the second processor id is B, C, D, then B corresponds to the multicast group id 1, C corresponds to the multicast group id 2, D corresponds to the multicast group id 3, and the target multicast group id is determined from the multicast group id 1, the multicast group id 2, and the multicast group id 3.
According to the video data processing method, the high-speed serial computer expansion bus component obtains the multicast group identification corresponding to the second processor identification from the mapping relation between the stored second processing identification and the multicast group identification, and determines the target multicast group identification, so that the function of one PCIe component with more than one address can be realized, dozens of paths of video data can be processed, the performance requirement on a single processor is very low, the receiving and sending paths of multi-path videos can be flexibly configured, a large amount of cost is saved compared with an fpga (Field Programmable Gate Array) switching chip used for traditional video switching, low-delay video processing can be provided, and the requirement of an embedded video conference system is completely met.
In one embodiment, a high speed serial computer expansion bus component stores a mapping of multicast group address ranges to multicast group identifications.
The high-speed serial computer expansion bus component acquires the multicast group identification corresponding to each second processor identification in the second processor identifications from the mapping relation between the stored second processor identifications and the multicast group identifications, and the method comprises the following steps: the high-speed serial computer expansion bus component determines a corresponding target multicast group address range according to the second processor identification; and determining the multicast group identification corresponding to the target multicast group address range according to the mapping relation.
Wherein, the multicast works by using a concept of virtual group address, the destination addresses of the data packets are not one but one group, and the multicast group address is formed, therefore, a large amount of multicast address space is reserved for multicast communication. The second processor identification may be a multicast group address.
Specifically, the high speed serial computer expansion bus component stores a mapping relationship of a multicast group address range and a multicast group identification. Table 1 below is a table of mapping multicast group address ranges to multicast group identifications. The high speed serial computer bus component determines a corresponding target multicast group address range based on the second processor identification. And determining the multicast group identification corresponding to the target multicast group address range according to the mapping relation. For example, the second processor identifier is 0x20000000, the corresponding Multicast Group address range is 0x20000000 to 0x20799999, and the corresponding Multicast Group number is Multicast Group 0. Or, if the second processor identifier is the B processor, the multicast group address of the processor needs to be acquired, the target multicast group address range is determined according to the multicast group address, and the multicast group identifier corresponding to the target multicast group address range is determined according to the mapping relationship. The multicast group may be 8M (megabytes) in size, setting the multicast base address of all ports of a PCIe switch to an address in the PCIe space.
TABLE 1
| Multicast group address range | Multicast group number |
| 0x20000000～0x20799999 | Multicast Group 0 |
| 0x20800000～0x20999999 | Multicast Group 1 |
| 0x21000000～0x21799999 | Multicast Group 2 |
| 0x21800000～0x21999999 | Multicast Group 3 |
| 0x22000000～0x22799999 | |
| 0x22800000～0x22999999 | Multicast Group 5 |
| 0x23000000～0x23799999 | |
According to the video data processing method, the high-speed serial computer expansion bus component determines the corresponding target multicast group address range according to the second processor identifier, and determines the multicast group identifier corresponding to the target multicast group address range according to the mapping relation, so that which multicast group needs to be added can be determined, video data of one processor can be distributed to other processors for video processing, and the video processing efficiency is improved.
In one embodiment, the second processor identification is an address identification in a high speed serial computer expansion bus tree. Specifically, the second processor identification is 0x20000000 as shown in table 1, but not limited thereto. The second processor identifier is the address identifier in the high-speed serial computer expansion bus tree, and the high-speed serial computer expansion bus component can directly determine the multicast group address range without acquiring the address identifier of the second processor, thereby improving the video processing efficiency.
In one embodiment, as shown in fig. 3, a schematic flow chart of transmitting video data in one embodiment is shown. A first processor transmitting video data to a second processor joining a multicast group via a system bus component, comprising:
in step 302, the first processor sends video data to the high speed serial computer expansion bus assembly.
Specifically, the first processor sends video data to the high speed serial computer expansion bus component through the connected high speed serial computer expansion bus component port.
And step 304, the high-speed serial computer expansion bus component receives the video data sent by the first processor and encapsulates the video data into a transaction layer data packet by adopting a high-speed serial computer expansion bus protocol.
The high-speed serial computer expansion bus protocol is PCIe bus protocol. The Transaction Layer Packet (TLP) includes video data, a second processor identifier, and may further include first processor-related information such as, but not limited to, a first processor identifier.
Specifically, the high-speed serial computer expansion bus component receives video data sent by the first processor, and encapsulates the video data into a transaction layer data packet by adopting a high-speed serial computer expansion bus protocol.
At step 306, the high speed serial computer expansion bus component sends the transaction layer packet to the second processor joining the multicast group.
Specifically, the high speed serial computer expansion bus component sends a transaction layer packet to the second processor that joined the multicast group identifying the corresponding second processor.
According to the video data processing method, the PCIe component receives video data sent by the first processor, and the video data is encapsulated into the transaction layer data packet by adopting a PCIe bus protocol, so that the video data can be converted into a format capable of being transmitted in the PCIe component, and the transaction layer data packet is sent to the target processor added into the multicast group, so that the target processor can simultaneously receive and process the transaction layer data packet, the system performance consumed by a single processor is reduced, and the time delay of video data processing is reduced.
In one embodiment, the system bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification, comprising: when the number of the second processor identifications is at least two, the system bus assembly determines a target processor identification according to the service type of the video data; and the system bus component takes the multicast group identification corresponding to the target processor identification as the target multicast group identification.
In particular, the first processor may designate a plurality of second processor identifications as the to-be-received processor identifications. When the second processor identifications are at least two, the system bus component determines the target processor identification according to the service type of the video data. The system bus component uses the multicast group identification corresponding to the target processor identification as the target multicast group identification. For example, the service type may be a video conference type, etc., without being limited thereto. And if the service type is the video conference type and the corresponding target processor identifier is the processor A, the system bus component takes the multicast group 0 corresponding to the processor A as the target multicast group identifier.
According to the video data processing method, the service types corresponding to the processors can be different, when the number of the second processors is at least two, the system bus assembly determines the target processor identifier according to the service types of the video data, and the multicast group identifier corresponding to the target processor identifier is used as the target multicast group identifier, so that the video processing efficiency can be improved.
In one embodiment, as shown in FIG. 4, a schematic diagram of a computer device in one embodiment is shown. FIG. 4 includes processor A, processor B, processor C, processor D, processor E, processor F, processor G, and PCIe switch components, i.e., high speed serial computer expansion bus components, for multi-channel video processing. Wherein, the processor A, the processor B, the processor C, the processor D, the processor E, the processor F and the processor G are not the same processor but can be the same type of processor. For example, the model of the processor A is hi3536, the model of the processor B, the processor C, the processor D, the processor E, the processor F and the processor G are all hi3531D, which are all multi-channel high-definition soc system chips, and PCIe switch chip connections are used among 7 processors. The PCIe switch chip model is PES24NT24G 2. The processor A serves as a transmitting end of PCIe switch, and the processor B, the processor C, the processor D, the processor E, the processor F and the processor G serve as receiving ends.
In one embodiment, as shown in fig. 5, a hardware processing diagram of a video data processing method in one embodiment is shown. The A processor acts as a host processor and includes a PCIe component in the host processor. The B processor, the C processor, the D processor, the E processor, the F processor and the G processor are taken as slave processors. The addresses in FIG. 5 are the addresses of the processor in the high speed serial computer expansion bus tree. The multicast group in fig. 5 refers to a multicast group to which a processor is currently joined, rather than the multicast group in table 1.
The embodiment provides a PCIe-based video data send-multiple-processing implementation scheme, where the implementation scheme is composed of 1 master processor and 6 slave processors, one processor may send more than one path of video data, and multiple processors may be flexibly configured to receive data, and the specific description is as follows:
1. according to address allocation of a transmitting end and a receiving end of a PCIe component, a PCIe switch is configured to divide address ranges of 7 multicast groups, as shown in the above table 1.
2. The multicast group number of the processor is configured and determined according to the multicast group address bearing corresponding to the sending processor, as shown in table 1 above.
And 3, the G processor acquires the video data and formulates a second processor identifier for receiving the video data. For example, the second processors are identified as 0x20000000, 0x20800000, 0x21000000 and 0x21800000, i.e. the addresses corresponding to the a processor, the B processor, the C processor and the D processor, respectively. In the figure, the target multicast group id determined by the PCIe component is the multicast group 0 corresponding to the a processor as shown in table 1, and then the PCIe component adds 0x20000000, 0x20800000, 0x21000000, and 0x21800000 to the multicast group 0. The PCIe component copies the video data, encapsulates the video data into a transaction layer data packet by adopting a PCIe bus protocol, and sends the video data to the processor A, the processor B, the processor C and the processor D. The A processor, the B processor, the C processor and the D processor receive video data through corresponding ports.
And 4, after the processor A, the processor B, the processor C and the processor D receive the data, splicing, encoding, zooming and the like are carried out on the video data.
In the above video data processing method, one processor transmits video data to a plurality of processors, and the processor that is to receive the data is added to the multicast group corresponding to the processor that transmits the data, so that any one processor in the multicast group transmits data using dma, and the other processors in the multicast group can receive the data. Therefore, the video data is processed through the multicast group, the performance of the processor is fully utilized, the video processing delay is reduced, the system stability is improved, and better use experience is presented to users; through the scheme design, code compiling, function debugging and the like, the video data can be processed by a plurality of processors at the same time, the load of a single processor is reduced, the time delay is reduced, the requirement of the embedded high-definition terminal in complex video application is met, and the video conference effect is obviously improved.
It should be understood that although the various steps in the flow charts of fig. 2-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, a computer device is provided, the computer device comprising at least two processors and a system bus component;
the first processor of the at least two processors is used for acquiring the video data and acquiring a second processor identifier corresponding to the video data;
the system bus component is used for determining a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifiers;
the system bus assembly adds the second processor identification to a multicast group corresponding to the target multicast group identification;
the first processor is used for sending video data to a second processor which joins in the multicast group through the system bus assembly, and the second processor is used for processing the video data after receiving the video data.
In the computer device, the first processor of the at least two processors acquires the video data and the second processor identifier corresponding to the video data, that is, the to-be-received processor is designated before the video data is sent, the system bus component selects the target multicast group identifier from the multicast group identifiers corresponding to the to-be-received processor identifier and adds the to-be-received processor identifier to the multicast group corresponding to the target multicast group identifier, so that the video data can be sent to the second processor in the multicast group at the same time, the video data of one processor can be distributed to other processors for video processing, the problem that the system performance occupied by the single processor is too high can be solved, the resource occupation is reduced, the video processing delay is reduced, the system stability is improved, and better use experience is presented to users.
In one embodiment, the system bus component is a high speed serial computer expansion bus component;
the high-speed serial computer expansion bus assembly is used for acquiring a multicast group identifier corresponding to the second processor identifier from the stored mapping relation between the second processor identifier and the multicast group identifier;
the high-speed serial computer expansion bus component is used for determining the target multicast group identification from the multicast group identification corresponding to the second processor identification.
According to the computer device, the high-speed serial computer expansion bus component obtains the multicast group identification corresponding to the second processor identification from the mapping relation between the stored second processing identification and the multicast group identification, and determines the target multicast group identification, so that the function of one PCIe component with more than one address can be realized, dozens of paths of video data can be processed, the performance requirement on a single processor is very low, the receiving and sending paths of multiple paths of videos can be flexibly configured, a large amount of cost is saved compared with an fpga (Field Programmable Gate Array) switching chip used for traditional video switching, low-delay video processing can be provided, and the requirement of an embedded video conference system is completely met.
In one embodiment, a high speed serial computer expansion bus component stores a mapping relationship of a multicast group address range and a multicast group identification;
the high-speed serial computer expansion bus component is used for determining a corresponding target multicast group address range according to the second processor identification;
the high-speed serial computer expansion bus component is used for determining the multicast group identification corresponding to the target multicast group address range according to the mapping relation.
According to the computer device, the high-speed serial computer expansion bus component obtains the multicast group identification corresponding to the second processor identification from the mapping relation between the stored second processing identification and the multicast group identification, and determines the target multicast group identification, so that the function of one PCIe component with more than one address can be realized, dozens of paths of video data can be processed, the performance requirement on a single processor is very low, the receiving and sending paths of multiple paths of videos can be flexibly configured, a large amount of cost is saved compared with an fpga (Field Programmable Gate Array) switching chip used for traditional video switching, low-delay video processing can be provided, and the requirement of an embedded video conference system is completely met.
In one embodiment, the second processor identification is an address identification in a high speed serial computer expansion bus tree. The second processor identifier is the address identifier in the high-speed serial computer expansion bus tree, and the high-speed serial computer expansion bus component can directly determine the multicast group address range without acquiring the address identifier of the second processor, thereby improving the video processing efficiency.
In one embodiment, a first processor transmitting video data to a second processor joining a multicast group via a system bus component, comprising:
the first processor is used for sending video data to the high-speed serial computer expansion bus assembly;
the high-speed serial computer expansion bus component is used for receiving the video data sent by the first processor and packaging the video data into a transaction layer data packet by adopting a high-speed serial computer expansion bus protocol;
the high speed serial computer expansion bus component is for sending the transaction layer packet to the second processor joining the multicast group.
In the computer device, the PCIe component receives the video data sent by the first processor, and encapsulates the video data into the transaction layer packet by using the PCIe bus protocol, so that the video data can be converted into a format that can be transmitted in the PCIe component, and the transaction layer packet is sent to the target processor added to the multicast group, so that the target processor can receive and process the transaction layer packet at the same time, thereby reducing the system performance consumed by a single processor, and reducing the time delay of video data processing.
In one embodiment, the system bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification, comprising:
when the second processor identifications are at least two, the system bus component is used for determining a target processor identification according to the service type of the video data;
the system bus component is used for taking the multicast group identification corresponding to the target processor identification as the target multicast group identification.
In the computer device, the service types corresponding to each processor may be different, when the number of the second processor identifiers is at least two, the system bus component determines the target processor identifier according to the service type of the video data, and the multicast group identifier corresponding to the target processor identifier is used as the target multicast group identifier, so that the video processing efficiency can be improved.
For specific limitations of the video data processing apparatus, reference may be made to the above limitations of the video data processing method, which are not described herein again. The respective modules in the video data processing apparatus described above may be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal device, and its internal structure diagram may be as shown in fig. 6. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a video data processing method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.
In an embodiment, a computer-readable storage medium is provided, in which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
In one embodiment, a computer program product or computer program is provided that includes computer instructions stored in a computer-readable storage medium. The computer instructions are read by a processor of a computer device from a computer-readable storage medium, and the computer instructions are executed by the processor to cause the computer device to perform the steps in the above-mentioned method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A video data processing method is applied to computer equipment comprising at least two processors and a system bus assembly, wherein the system bus assembly is respectively connected with each processor of the at least two processors; the method comprises the following steps:
a first processor in the at least two processors acquires video data and acquires a second processor identifier corresponding to the video data;
the system bus assembly determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification;
and the system bus assembly adds the second processor identification to a multicast group corresponding to the target multicast group identification, and the first processor sends the video data to the second processor which is added to the multicast group through the system bus assembly, so that the second processor processes the video data.
2. The method of claim 1, wherein the system bus component is a high speed serial computer expansion bus component;
the system bus component determines a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifiers, including:
the high-speed serial computer expansion bus component acquires a multicast group identifier corresponding to a second processor identifier from a mapping relation between the second processor identifier and the multicast group identifier;
and the high-speed serial computer expansion bus component determines a target multicast group identification from the multicast group identifications corresponding to the second processor identification.
3. The method of claim 2 wherein the high speed serial computer expansion bus component stores a mapping of multicast group address ranges to multicast group identifications;
the method for acquiring the multicast group identifier corresponding to the second processor identifier from the mapping relationship between the second processor identifier and the multicast group identifier stored by the high-speed serial computer expansion bus component comprises the following steps:
the high-speed serial computer expansion bus component determines a corresponding target multicast group address range according to the second processor identification;
and the high-speed serial computer expansion bus component determines the multicast group identification corresponding to the target multicast group address range according to the mapping relation.
4. The method of any of claims 1 to 3, wherein the second processor identification is an address identification in the high speed serial computer expansion bus tree.
5. The method of any of claims 1 to 3, wherein the first processor transmitting the video data to a second processor joining the multicast group via the system bus component comprises:
the first processor transmitting the video data to the high speed serial computer expansion bus component;
the high-speed serial computer expansion bus assembly receives video data sent by the first processor and encapsulates the video data into a transaction layer data packet by adopting a high-speed serial computer expansion bus protocol;
the high speed serial computer expansion bus component sends the transaction layer packet to the second processor joining the multicast group.
6. The method of any of claims 1 to 3, wherein the determining, by the system bus component, a target multicast group identification from the multicast group identifications corresponding to the second processor identification comprises:
when the number of the second processor identifications is at least two, the system bus component determines a target processor identification according to the service type of the video data;
and the system bus component takes the multicast group identification corresponding to the target processor identification as the target multicast group identification.
7. A computer device comprising at least two processors and a system bus component, the system bus component being coupled to each of the at least two processors;
a first processor of the at least two processors is used for acquiring video data and acquiring a second processor identifier corresponding to the video data;
the system bus component is used for determining a target multicast group identifier from the multicast group identifiers corresponding to the second processor identifiers;
the system bus component adds the second processor identification to a multicast group corresponding to the target multicast group identification;
the first processor is configured to send the video data to a second processor joining the multicast group through the system bus component, and the second processor is configured to process the video data after receiving the video data.
8. The computer device of claim 7, wherein the system bus component is a high speed serial computer expansion bus component;
the high-speed serial computer expansion bus assembly is used for acquiring a multicast group identifier corresponding to a second processor identifier from a mapping relation between the second processor identifier and the multicast group identifier;
the high-speed serial computer expansion bus component is used for determining a target multicast group identification from the multicast group identifications corresponding to the second processor identifications.
9. The computer device of claim 8, wherein the high speed serial computer expansion bus component stores a mapping of multicast group address ranges to multicast group identifications;
the high-speed serial computer expansion bus component is used for determining a corresponding target multicast group address range according to the second processor identification;
and the high-speed serial computer expansion bus assembly is used for determining the multicast group identification corresponding to the target multicast group address range according to the mapping relation.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 6.
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