CN112149370A - Chip aging static time sequence analysis method and device and electronic equipment - Google Patents
Chip aging static time sequence analysis method and device and electronic equipment Download PDFInfo
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- CN112149370A CN112149370A CN202011054446.4A CN202011054446A CN112149370A CN 112149370 A CN112149370 A CN 112149370A CN 202011054446 A CN202011054446 A CN 202011054446A CN 112149370 A CN112149370 A CN 112149370A
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Abstract
The embodiment of the application provides a static time sequence analysis method and device for chip aging and electronic equipment, wherein the method comprises the following steps: calculating to obtain an aging standard unit library corresponding to the standard unit library based on an aging model and a standard unit library designed by a target chip; acquiring a parasitic parameter of the target chip design aging according to the aging model and the target chip design; calculating to obtain first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard unit library; and analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
Description
Technical Field
The application relates to the technical field of chip design, in particular to a static time sequence analysis method and device for chip aging and electronic equipment.
Background
The current chip design mainly aims at the required function to design and verify, and the aging condition of the product is generally that after the product is taped, the product aging test is carried out through a real aging acceleration experiment on the chip, and whether the product meets the condition under the corresponding aging requirement is tested. However, if the product burn-in test is performed only after the product is taped out, through a real burn-in acceleration test, the influence on the chip design or the chip itself is not large.
Disclosure of Invention
The application aims to provide a static time sequence analysis method and device for chip aging, electronic equipment and a computer readable storage medium, which can solve the problems related to aging detection of a chip.
In a first aspect, an embodiment of the present invention provides a method for analyzing a static timing sequence of chip aging, including:
calculating to obtain an aging standard unit library corresponding to the standard unit library based on an aging model and a standard unit library designed by a target chip;
acquiring a parasitic parameter of the target chip design aging according to the aging model and the target chip design;
calculating to obtain first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard unit library;
and analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
In an optional embodiment, the calculating, based on the standard cell library designed by the aging model and the target chip, an aging standard cell library corresponding to the standard cell library includes:
acquiring an aging parameter of the target chip design;
and calculating to obtain an aging standard unit library corresponding to the standard unit library according to the aging parameters, the aging model and the standard unit library designed by the target chip.
In the embodiment of the application, the aging parameters are determined, so that the current chip analysis requirement can be conveniently obtained, the analysis requirement can be more accurately positioned, and the analysis effect is improved.
In an optional embodiment, the analyzing the first timing information to obtain the predicted aging performance of the target chip design includes:
determining a predicted aging margin of the target chip design according to path information in the first time sequence information;
and determining whether the aging performance of the target chip design meets the requirement or not according to the predicted aging allowance, wherein when the predicted aging allowance is positive, the target chip design is characterized to be aged and meet the requirement, and when the predicted aging allowance is negative, the target chip design is characterized to not meet the aging requirement.
In the embodiment of the application, the predicted aging condition can be determined through the determined margin, and whether the predicted aging state can meet the aging requirement corresponding to the design of the target chip or not can be determined.
In an optional embodiment, the analyzing the first timing information to obtain the predicted aging performance of the target chip design includes:
calculating second time sequence information of the target chip design according to the standard cell library;
and comparing the first time sequence information with the second time sequence information to determine the predicted aging performance of the target chip design.
In the embodiment of the application, the first time sequence information and the second time sequence information are compared, so that the predicted aging performance can be determined, the comparison gap of the performance of the chip design relative to the current target chip can be realized, and a data basis can be provided for the chip design.
In an optional embodiment, the comparing the first timing information with the second timing information to determine the predicted aging performance of the target chip design includes:
comparing each piece of path information in the first time sequence information with the path information corresponding to the second time sequence information to determine the aging influence degree of each piece of path information in the first time sequence information on the target chip design;
and determining the predicted aging performance of the target chip design according to the influence degree of each path information in the first time sequence information.
In the embodiment of the application, through the comparison of the path information, the influence of each path on aging can be determined, so that the performance distribution condition of the target chip design can be determined more accurately, a data base can be provided for the improvement of the subsequent chip design, and the optimization effect of the chip design can be improved.
In an alternative embodiment, the method further comprises:
determining a target influence path according to the influence degree of each path information in the first time sequence information;
and determining a product adjustment strategy according to the target influence path.
In the embodiment of the application, based on the comparison between the first timing information and the second timing information, the path information having a large influence on the design of the target chip can be determined, so that a strategy for better adjusting the design of the target chip can be determined, and the effect of the chip design can be improved.
In an optional embodiment, the calculating, according to the parasitic parameter and the aging standard cell library, first timing information corresponding to predicted aging of the target chip design includes:
calculating the line delay in the first time sequence information according to the parasitic parameters and the aging standard unit library;
and calculating the unit delay in the first time sequence information according to the aging standard unit library.
In the embodiment of the application, the outlet delay is determined based on the parasitic parameters and the aging standard cell library, and the cell delay is determined based on the aging standard cell library, so that various predicted aging conditions of the target chip design are obtained, and the accuracy of aging analysis of the target chip design can be improved.
In a second aspect, an embodiment of the present invention provides an apparatus for analyzing a static timing sequence of chip aging, including:
the first calculation module is used for calculating an aging standard unit library corresponding to the standard unit library based on an aging model and a standard unit library designed by a target chip;
the obtaining module is used for obtaining the parasitic parameters of the target chip design aging according to the aging model and the target chip design;
the second calculation module is used for calculating and obtaining first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard cell library;
and the analysis module is used for analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
In a third aspect, an embodiment of the present invention provides an electronic device, including: a processor, a memory storing machine readable instructions executable by the processor, the machine readable instructions when executed by the processor perform the steps of the method of any of the preceding embodiments when the electronic device is run.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the method according to any one of the foregoing embodiments.
The beneficial effects of the embodiment of the application are that: the embodiment of the application jumps out of the inertial thinking, and the aging detection analysis of the chip is arranged at the design stage of the chip, so that a data base can be provided for the design or optimization of the chip. Further, at the design back end of the chip, the first time sequence information for predicting the aging is calculated through the aging model and the standard cell library, so that the aging analysis of the chip can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of a static timing analysis method for chip aging according to an embodiment of the present disclosure.
Fig. 3 is a detailed flowchart of step 204 of the method for analyzing the static timing of the chip aging according to the embodiment of the present application.
Fig. 4 is a detailed flowchart of step 204 of the method for analyzing the static timing of the chip aging according to the embodiment of the present application.
Fig. 5 is a functional block diagram of a static timing analysis apparatus for chip aging according to an embodiment of the present disclosure.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Current chip designs mainly include front-end designs and back-end designs. The front-end design is mainly a logic design and is used for completing the design and integration of the chip according to the chip specification and completing the design verification of the chip by using a simulation verification tool. The back-end design is mainly a physical design, and is used for performing layout and layout, physical verification and final generation of GDSII data for manufacturing on a gate-level netlist generated by the front-end design through an Electronic Design Automation (EDA) design tool.
Timing of the digital circuit can be calculated by static timing analysis in the back-end design to detect all possible paths to find out if there is a timing violation in the design. The current static timing analysis mainly aims at the current state of a designed chip to carry out detection and analysis.
The detection of the aging of the chip is generally based on that after the product is subjected to tape-out, an aging acceleration experiment is carried out on the real chip to carry out a chip aging test, so that whether the test chip meets the condition under the corresponding aging requirement is realized. Burn-in testing after tape-out, the test can only yield a successful or failed result, presenting problems with difficulty debugging (debug) the chip, and failing to produce useful feedback on the chip design.
Based on the above studies, if it is possible to realize both the burn-in detection and the detection in the back-end design of the chip design, the performance of the designed chip can be improved for the chip design. Based on the requirement, in combination with static timing analysis used in the front-end and back-end design, embodiments of the present application provide a method and an apparatus for static timing analysis of chip aging, an electronic device, and a computer-readable storage medium.
Example one
To facilitate understanding of the present embodiment, an electronic device for performing the static timing analysis method of chip aging disclosed in the embodiments of the present application will be described in detail first.
As shown in fig. 1, is a block schematic diagram of an electronic device. The electronic device 100 may include a memory 111, a memory controller 112, a processor 113, a peripheral interface 114, an input-output unit 115, and a display unit 116. It will be understood by those of ordinary skill in the art that the structure shown in fig. 1 is merely exemplary and is not intended to limit the structure of the electronic device 100. For example, electronic device 100 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The above-mentioned elements of the memory 111, the memory controller 112, the processor 113, the peripheral interface 114, the input/output unit 115 and the display unit 116 are electrically connected to each other directly or indirectly, so as to implement data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The processor 113 is used to execute the executable modules stored in the memory.
The Memory 111 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The memory 111 is configured to store a program, and the processor 113 executes the program after receiving an execution instruction, and the method executed by the electronic device 100 defined by the process disclosed in any embodiment of the present application may be applied to the processor 113, or implemented by the processor 113.
The processor 113 may be an integrated circuit chip having signal processing capability. The Processor 113 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The peripheral interface 114 couples various input/output devices to the processor 113 and memory 111. In some embodiments, the peripheral interface 114, the processor 113, and the memory controller 112 may be implemented in a single chip. In other examples, they may be implemented separately from the individual chips.
The input/output unit 115 is used to provide input data to the user. The input/output unit 115 may be, but is not limited to, a mouse, a keyboard, and the like.
The display unit 116 provides an interactive interface (e.g., a user operation interface) between the electronic device 100 and the user or is used for displaying image data to the user for reference. In this embodiment, the display unit may be a liquid crystal display or a touch display. In the case of a touch display, the display can be a capacitive touch screen or a resistive touch screen, which supports single-point and multi-point touch operations. The support of single-point and multi-point touch operations means that the touch display can sense touch operations simultaneously generated from one or more positions on the touch display, and the sensed touch operations are sent to the processor for calculation and processing.
In this embodiment, the memory 111 may store a computer program corresponding to the static timing analysis tool. Illustratively, the processor 113, when running the computer program of the static timing analysis tool, may be used to analyze timing information of a target chip design. Illustratively, the display unit 116 may display an operation interface of the static timing analysis tool.
The electronic device 100 in this embodiment may be configured to perform each step in each method provided in this embodiment. The implementation of the static timing analysis method of chip aging is described in detail below by several embodiments.
Example two
Please refer to fig. 2, which is a flowchart illustrating a static timing analysis method for chip aging according to an embodiment of the present disclosure. The specific process shown in fig. 2 will be described in detail below.
Illustratively, the aging model may include an aging formula for each element in the target chip design. Illustratively, the aging formula may characterize the aging rules, aging speed, etc. of the various components. Illustratively, the standard cell delay can be calculated by the aging formula.
Illustratively, the target chip design described above may include a distribution of elements of a chip of the desired design.
Illustratively, the standard cell library of the target chip design may include a gallery, a symbol library, a circuit logic library, and the like.
Illustratively, the standard cell library of the target chip design may include a plurality of standard cells. Alternatively, the standard cell may include a plurality of basic cells, such as an inverter, an and gate, a register, a selector, a full adder, etc., each of the standard cells corresponds to a plurality of cell circuits with different sizes and different driving capabilities, and the cell circuits with different driving capabilities may be integral multiples of the basic size or the minimum size.
In this embodiment, an aging standard cell library is calculated from the aging model and a standard cell library of a target chip design.
Illustratively, the aging standard cell library may include predicted aging delays corresponding to each standard cell in the target chip design. For example, the pre-configured aging period may be two years, and the aging standard cell library may include the predicted delay of each standard cell after two years.
Alternatively, the aging model may be a preset model. For example, the aging model may be data provided by a foundry (Feature, advance, Benefit, FAB for short).
Optionally, step 201 may include: acquiring an aging parameter of the target chip design; and calculating to obtain an aging standard unit library corresponding to the standard unit library according to the aging parameters, the aging model and the standard unit library designed by the target chip.
The aging parameter may be a preset default parameter, or may be a parameter that is provided by providing an operable interface through which user input is received.
Alternatively, the aging parameter may be the age that needs to be predicted. For example, if it is desired to predict the aging of a chip after two years, the aging parameter may be two years. For another example, if it is desired to predict the aging of a chip seven years later, then the aging parameter may be seven years. As another example, if it is desired to predict the aging of a chip ten years later, then the aging parameter may be ten years. Specifically, the value of the aging parameter may be set according to the test requirements.
Illustratively, the target chip design may include standard cells of a chip to be designed, and combinations of elements in each standard cell, and initial values corresponding to each element, connection relationships of each element, and the like.
Illustratively, the parasitic parameters may include values of various elements in the target chip design. For example, the target chip design may include elements such as capacitors, inductors, and resistors, and the parasitic parameters represent capacitance values of the capacitors, inductance values of the inductors, and resistance values of the resistors.
In this embodiment, for the research on the aging problem of the chip, since each element may cause a change in the value of each element during the use process, each element in the target chip design is calculated by the aging model, and the predicted parasitic parameter of the target chip design after aging can be obtained.
For example, different aging formulas may be provided for different element correspondences in the aging model.
Alternatively, the aging formula may be a formula determined from an accelerated stress model.
By way of example, the aging formula can calculate the change of the value of each element in a specified time period, so as to determine the predicted aged parasitic parameters.
Optionally, step 202 may include: acquiring an aging parameter of the target chip design; and acquiring the parasitic parameters of the target chip design aging according to the aging parameters, the aging model and the target chip design.
The aging parameter may be a preset default parameter, or may be a parameter that is provided by providing an operable interface through which user input is received.
Alternatively, the aging parameter may be the age that needs to be predicted. For example, if it is desired to predict the aging of a chip after two years, the aging parameter may be two years. For another example, if it is desired to predict the aging of a chip seven years later, then the aging parameter may be seven years. As another example, if it is desired to predict the aging of a chip ten years later, then the aging parameter may be ten years. Specifically, the value of the aging parameter may be set according to the test requirements.
In this embodiment, the aging parameters obtained in step 202 and step 201 may be the same value. Alternatively, in the calculation process of step 201 and step 202, the aging parameter may be acquired only once, and the aging parameter may be shared in both calculation processes.
And 203, calculating to obtain first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard cell library.
Optionally, the first timing information may include a line delay and a cell delay.
The static timing analysis after introducing the aging model in table 1 below corresponds to schematic timing information, that is, schematic information of one path information in the first timing information of the target chip design. I.e., timing information of the target chip design after processing according to the aging model.
TABLE 1
Wherein, Trans in table 1 represents propagation time (transition), and the value in the table represents the time required for propagating to the current node, and the rise/fall time of the signal; incr denotes the increment (incremental), whose values in the table represent the increment; path represents a path, with values in the table representing the delay of the path to proceed to the current node; r represents rise (rise), indicating that the path to the current node is a rise; f represents a descent (fall), which represents that the path is descending when the path is processed to the current node; slack represents the predicted aging margin.
For example, the rising edge of the clock CLK (rise edge), clock ideal line delay (ideal), clock input CLK (in), ffa/CLK (DTC10) in table 1 may be parameters of the inputs.
In the embodiment, the line delay is not only affected by the standard cell itself, but also affected by the parasitic parameters, and the cell delay is mainly determined by the effect of the standard cell. Thus, different calculations may be used based on different delays.
In one embodiment, the line delay in the first timing information may be calculated based on the parasitic parameters and the aging standard cell library.
In this embodiment, the newly added delay at the input end of each element can be calculated from the parasitic parameters and the aging standard cell library. The added delay at the input of each element can also be a line delay.
Table 1 below is an example in which the line delay (net delay) can be calculated based on parasitic parameters and a library of aging standard cells. The line delays required to be calculated by the parasitic parameters and aging standard cell library shown in table 1 include: input U1/A (BUF) of the buffer, input U2/A (NOR3) of the NOR gate, input U3/A (INV) of the frequency converter, input U4/A (ND2) of the NAND gate, and input U5/A (ND2) of the NAND gate.
In one embodiment, the cell delay in the first timing information may be calculated according to the aging standard cell library.
Table 1 below is an example in which the line delay (cell delay) can be calculated based on a library of aging standard cells. The cell delays shown in table 1 that need to be calculated by the parasitic parameters and the aging standard cell library include: the output end U1/B (BUF) of the buffer, the output end U2/B (NOR3) of the NOR gate, the output end U3/B (INV) of the frequency converter, the output end U4/B (ND2) of the NAND gate and the output end U5/B (ND2) of the NAND gate.
And 204, analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
In this embodiment, the aging analysis performed at the back-end design stage of the chip may be implemented based on static timing analysis. This static timing analysis can be understood as: using a specific Timing Model (Timing Model), the target chip design is analyzed to determine whether the target chip design violates a given Timing Constraint (Timing Constraint).
Alternatively, a static timing analysis tool may be used to perform performance analysis and timing signoff for aging of a target chip design.
In one embodiment, as shown in FIG. 3, step 204 may include the following steps.
In this implementation, when the predicted aging margin is positive, the target chip design is characterized to be aged to meet the requirement, and when the predicted aging margin is negative, the target chip design is characterized to not meet the aging requirement.
For example, when the predicted aging margin is characterized as negative, it may be characterized that the target chip design cannot meet the requirement corresponding to the set aging parameter.
Illustratively, in the example shown in Table 2, the predicted aging margin slack has a value equal to-61, indicating that in this example, the currently predicted aging timing information does not meet the aging requirements of the target chip design.
In one embodiment, as shown in FIG. 4, step 204 may include the following steps.
Illustratively, this step 2043 may include: and calculating unit delay in the second time sequence information according to the standard unit library, and calculating line delay according to the standard unit library and parasitic parameters designed by the target chip.
As shown in table 2 below, table 2 shows timing information corresponding to the normal static timing analysis in one example, that is, schematic information of one path information in the second timing information of the target chip design. I.e., the initial timing information of the latest design of the target chip design.
TABLE 2
In one embodiment, each piece of path information in the first timing information may be compared with the path information corresponding to the second timing information to determine an aging influence degree of each piece of path information in the first timing information on the target chip design; and determining the predicted aging performance of the target chip design according to the influence degree of each path information in the first time sequence information.
Illustratively, the degree of influence of each path on the aging of the chip designed by the target chip can be determined according to the margin.
For example, the more negative the predicted aging margin in one piece of path information is, the greater the aging influence degree corresponding to the path corresponding to the piece of path information is. For another example, if the predicted aging margin in one piece of path information is a positive value, the smaller the aging influence degree corresponding to the path corresponding to the piece of path information is, or the aging influence degree corresponding to the path corresponding to the piece of path information is zero.
For example, the greater the aging influence of the path corresponding to each piece of path information on the target chip design, the worse the predicted aging performance of the target chip design may be represented; the smaller the aging influence degree of the path corresponding to each piece of path information on the target chip design is, the better the predicted aging performance of the target chip design can be represented.
Optionally, based on the analysis, the influence of each path on the aging of the chip of the target chip design may be determined, so that the optimization strategy of the corresponding chip design may be determined based on the influence degrees of different paths. Illustratively, the static timing analysis method for chip aging in the present embodiment may further include: determining a target influence path according to the influence degree of each path information in the first time sequence information; and determining a product adjustment strategy according to the target influence path.
Optionally, the product adjustment strategy may include, but is not limited to, adjusting the layout of components, the values of components, etc. in the target chip design.
Optionally, the product adjustment strategy may also be a replacement for standard cells.
Alternatively, the product adjustment strategy may be redesigned, which may increase the frequency, e.g., from 2G to 2.5G, which may attenuate the aging by 80%.
Alternatively, the product adjustment strategy may also be a switching circuit design mode, a circuit wiring mode, or the like.
In the static time sequence analysis method for chip aging provided by the embodiment of the application, the embodiment of the application jumps out from the inertial thinking, and the aging detection analysis of the chip is arranged at the design stage of the chip, so that a data basis can be provided for the design or optimization of the chip. Further, at the design back end of the chip, the first time sequence information for predicting the aging is calculated through the aging model and the standard cell library, so that the aging analysis of the chip can be realized.
Furthermore, an aging model is introduced into the standard cell library and the parasitic parameters, static time sequence analysis is combined, the time sequence situation of the chip after aging is analyzed, aging performance is accurately evaluated, the aging situation of the chip can be considered in the rear end design stage of the chip, the aging problem can be found as early as possible, feedback is carried out in time, directional design and optimization are carried out in advance, and the performance of the designed chip is improved.
EXAMPLE III
Based on the same application concept, the embodiment of the present application further provides a static timing analysis apparatus for chip aging corresponding to the static timing analysis method for chip aging, and because the principle of the apparatus in the embodiment of the present application for solving the problem is similar to the embodiment of the static timing analysis method for chip aging provided in the second embodiment, the implementation of the static timing analysis apparatus for chip aging in the embodiment of the present application can refer to the description in the embodiment of the static timing analysis method for chip aging, and repeated parts are not repeated.
Fig. 5 is a schematic diagram of functional modules of a static timing analysis apparatus for chip aging according to an embodiment of the present disclosure. Each module in the static timing analysis apparatus for chip aging in the present embodiment is used to execute each step in the above method embodiments. The static time sequence analysis device for chip aging comprises: a first calculation module 301, an acquisition module 302, a second calculation module 303 and an analysis module 304; wherein the content of the first and second substances,
the first calculation module 301 is configured to calculate an aging standard cell library corresponding to a standard cell library based on an aging model and a standard cell library designed by a target chip;
an obtaining module 302, configured to obtain a parasitic parameter of the target chip design aging according to the aging model and the target chip design;
a second calculating module 303, configured to calculate, according to the parasitic parameter and the aging standard cell library, first timing information corresponding to predicted aging of the target chip design;
an analysis module 304, configured to analyze the first timing information to obtain a predicted aging performance of the target chip design.
In a possible implementation, the first computing module 301 is further configured to:
acquiring an aging parameter of the target chip design;
and calculating to obtain an aging standard unit library corresponding to the standard unit library according to the aging parameters, the aging model and the standard unit library designed by the target chip.
In one possible implementation, the analysis module 304 is configured to:
determining a predicted aging margin of the target chip design according to path information in the first time sequence information;
and determining whether the aging performance of the target chip design meets the requirement or not according to the predicted aging allowance, wherein when the predicted aging allowance is positive, the target chip design is characterized to be aged and meet the requirement, and when the predicted aging allowance is negative, the target chip design is characterized to not meet the aging requirement.
In one possible implementation, the analysis module 304 includes:
the calculation unit is used for calculating second time sequence information of the target chip design according to the standard cell library;
and the comparison unit is used for comparing the first time sequence information with the second time sequence information so as to determine the predicted aging performance of the target chip design.
In a possible embodiment, the comparison unit is configured to:
comparing each piece of path information in the first time sequence information with the path information corresponding to the second time sequence information to determine the aging influence degree of each piece of path information in the first time sequence information on the target chip design;
and determining the predicted aging performance of the target chip design according to the influence degree of each path information in the first time sequence information.
In a possible implementation manner, the static timing analysis apparatus for chip aging in this embodiment:
a first determining module 305, configured to determine a target affected path according to the degree of influence of each path information in the first timing information;
a second determining module 306, configured to determine a product adjustment policy according to the target influence path.
In a possible implementation, the second calculating module 303 is configured to:
calculating the line delay in the first time sequence information according to the parasitic parameters and the aging standard unit library;
and calculating the unit delay in the first time sequence information according to the aging standard unit library.
In addition, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the static timing analysis method for chip aging in the foregoing method embodiments are executed.
The computer program product of the static timing analysis method for chip aging provided in the embodiment of the present application includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the steps of the static timing analysis method for chip aging described in the above method embodiment, which may be specifically referred to in the above method embodiment and are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A static time sequence analysis method for chip aging is characterized by comprising the following steps:
calculating to obtain an aging standard unit library corresponding to the standard unit library based on an aging model and a standard unit library designed by a target chip;
acquiring a parasitic parameter of the target chip design aging according to the aging model and the target chip design;
calculating to obtain first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard unit library;
and analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
2. The method of claim 1, wherein calculating an aging standard cell library corresponding to the standard cell library based on the aging model and a standard cell library of a target chip design comprises:
acquiring an aging parameter of the target chip design;
and calculating to obtain an aging standard unit library corresponding to the standard unit library according to the aging parameters, the aging model and the standard unit library designed by the target chip.
3. The method of claim 1, wherein analyzing the first timing information to obtain the predicted aging performance of the target chip design comprises:
determining a predicted aging margin of the target chip design according to path information in the first time sequence information;
and determining whether the aging performance of the target chip design meets the requirement or not according to the predicted aging allowance, wherein when the predicted aging allowance is positive, the target chip design is characterized to be aged and meet the requirement, and when the predicted aging allowance is negative, the target chip design is characterized to not meet the aging requirement.
4. The method of claim 1, wherein analyzing the first timing information to obtain the predicted aging performance of the target chip design comprises:
calculating second time sequence information of the target chip design according to the standard cell library;
and comparing the first time sequence information with the second time sequence information to determine the predicted aging performance of the target chip design.
5. The method of claim 4, wherein comparing the first timing information to the second timing information to determine the predicted aging performance of the target chip design comprises:
comparing each piece of path information in the first time sequence information with the path information corresponding to the second time sequence information to determine the aging influence degree of each piece of path information in the first time sequence information on the target chip design;
and determining the predicted aging performance of the target chip design according to the influence degree of each path information in the first time sequence information.
6. The method of claim 5, further comprising:
determining a target influence path according to the influence degree of each path information in the first time sequence information;
and determining a product adjustment strategy according to the target influence path.
7. The method according to any one of claims 1 to 6, wherein the calculating the first timing information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard cell library comprises:
calculating the line delay in the first time sequence information according to the parasitic parameters and the aging standard unit library;
and calculating the unit delay in the first time sequence information according to the aging standard unit library.
8. A static time sequence analysis device for chip aging is characterized by comprising:
the first calculation module is used for calculating an aging standard unit library corresponding to the standard unit library based on an aging model and a standard unit library designed by a target chip;
the obtaining module is used for obtaining the parasitic parameters of the target chip design aging according to the aging model and the target chip design;
the second calculation module is used for calculating and obtaining first time sequence information corresponding to the predicted aging of the target chip design according to the parasitic parameters and the aging standard cell library;
and the analysis module is used for analyzing the first time sequence information to obtain the predicted aging performance of the target chip design.
9. An electronic device, comprising: a processor, a memory storing machine-readable instructions executable by the processor, the machine-readable instructions when executed by the processor performing the steps of the method of any of claims 1 to 7 when the electronic device is run.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
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