CN112148456A - FPGA high-level comprehensive scheduling method - Google Patents
FPGA high-level comprehensive scheduling method Download PDFInfo
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- CN112148456A CN112148456A CN202011062643.0A CN202011062643A CN112148456A CN 112148456 A CN112148456 A CN 112148456A CN 202011062643 A CN202011062643 A CN 202011062643A CN 112148456 A CN112148456 A CN 112148456A
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Abstract
An FPGA high-level comprehensive scheduling method relates to an integrated circuit technology. The invention comprises the following steps: 1) calculating to obtain the length of a time frame of each operation; 2) calculating the sum of the occurrence probability of each operation in each control step according to the time frame to obtain probability distribution; 3) judging whether operations which are not scheduled exist, if so, calculating direct force and indirect force of all operations to be scheduled to each control step in the time frame, and selecting (op) with minimum resultant forcei,csj) Scheduling, and setting the length of the current operation time frame as 1, otherwise ending the scheduling; the inter-relay force is calculated by adopting the following method:the invention has obvious improvement on reducing the operation amount of the scheduling algorithm.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
With the increase of logic scale and performance requirement of FPGA devices, optimization of a scheduling algorithm in a high-level integration process is of great importance. The quality of the scheduling algorithm directly affects the time characteristics such as the execution speed and the response delay of the device and the space characteristics such as the hardware resource cost.
Commonly used Scheduling algorithms mainly include ASAP (As Soon As Possible), ALAP (As Late As Possible), List Scheduling algorithm (LS, List Scheduling), and force-guided algorithm (FDS, F)race-Directed Scheduling). Paulin and Knight proposed in 1989 to apply force-guided algorithms to high-level synthesis, which is a construction algorithm for finding minimum resource scheduling based on time constraints. The algorithm simulates the state of the minimum stress of a spring to distribute a force to each movement according to the Hooke's law f-k x in mechanics, so that the resources are uniformly distributed to the maximum extent in each period. In the force guidance algorithm, k represents an initial pressure on a control step, x represents a probability variation amount of an operation occurring in the control step, f represents an acting force of the control step on the operation, and a larger f represents a larger repulsive force to the operation. f comprises direct forces and indirect forces, wherein direct forces characterize the operation opiScheduling to control step csjTime, to control step csjThe resulting influence, indirect force, characterizes the operation opiScheduling to control step csjThen, to opiThe effect of the predecessor and successor operations. FIG. 1 is a drawing of
The main flow of the traditional force guidance algorithm comprises the following steps:
1) running ASAP and ALAP scheduling algorithms to obtain a time frame of each operation;
2) calculating the sum of the occurrence probability of each operation in each control step according to the time frame to obtain a probability distribution map;
3) judging whether operations which are not scheduled exist, if so, calculating direct force and indirect force of all operations to be scheduled to each control step in the time frame, and selecting (op) with minimum resultant forcei,csj) Scheduling, and setting the length of the current operation time frame as 1, otherwise ending the scheduling;
4) updating the time frames of the direct predecessor and direct successor of the operation;
5) update the probability distribution map, go to 3).
Wherein, the operation opiMay be expressed as
ALAP(opi) Representing operations opiCan adjustThe latest control step of the degree is recorded asCan be obtained by an ALAP scheduling algorithm; ASAP (op)i) To operate oniThe earliest control step that can be scheduled is recorded asMay be derived from the ASAP scheduling algorithm.
Operation opiIn a control step csjProbability P (op)i,csj) Is composed of
The probability distribution over each control step is then obtained as follows
Where n is the total number of operations of that type, K (cs)j) Can be regarded as k in the mechanical formula f ═ k × x, and is used for representing control step csjThe initial pressure of (a). Let x (cs)k) Represents an operation opiScheduling to control step csjWhen, P (op)i,csj) In a control step csjThe generated variation can be regarded as x in the mechanical formula. And drawing a probability distribution diagram through the probability distribution condition.
Solving the direct force and the indirect force to obtain the resultant force, i.e. the operation opiScheduling to control step csjThe direct forces generated are:
when cs isk=csjX (cs) isk) 1-1/h; when cs isk≠csjX (cs) isk) -1/h. The above formula is modified to obtain:
the deformation formula avoids the pair x (cs)k) The direct acting force generated by the dispatching operation can be obtained by directly utilizing the initial pressure distribution condition. Considering operation opiScheduling to control step csjThe influence of the successor on the predecessor and successor is generated by the scheduling, and the indirect force formula is as follows
Wherein opwEither immediately preceding or succeeding the current operation,is opwThe time frame of (a) is,to operate oniPost-dispatch opwThe length of the time frame of the update,aiming at the indirect force, the algorithm time complexity can reach
Will opiScheduling to csjThe resultant force calculation formula is as follows
F(opi,csj)=Fdirect(opi,csj)+Findirect(opi,csj,opw) (7)
Disclosure of Invention
The invention aims to solve the technical problem of providing a rapid and efficient FPGA high-level comprehensive scheduling method in order to adapt to the continuous increase of the scale of FPGA devices.
The technical scheme adopted by the invention for solving the technical problems is that the FPGA high-level comprehensive scheduling method comprises the following steps:
1) the time frame length for each operation is calculated:
operation opiMay be expressed as
Wherein ALAP (op)i) Representing operations opiThe latest control step that can be scheduled is recorded asASAP(opi) To operate oniThe earliest control step that can be scheduled is recorded as
2) Calculating the sum of the probability of each operation in each control step according to the time frame to obtain probability distribution, namely operation opiIn a control step csjProbability P (op)i,csj) Comprises the following steps:
the probability distribution over each control step is as follows:
where n is the total number of operations of that type, K (cs)j) Indicating the control step csjAn initial pressure on;
3) judging whether operations which are not scheduled exist, if so, calculating direct force and indirect force of all operations to be scheduled to each control step in the time frame, and selecting (op) with minimum resultant forcei,csj) The scheduling is carried out, the length of the time frame of the current operation is set to be 1,otherwise, finishing the scheduling;
wherein the content of the first and second substances,
(3.a) calculating the direct force: let x (cs)k) Represents an operation opiScheduling to control step csjWhen, P (op)i,csj) In a control step csjThe generated variable is to be operated oniScheduling to control step csjThe direct forces generated are:
(3.b) calculating the inter-relay;
4) updating the time frames of the direct predecessor and direct successor of the operation;
5) updating the probability distribution, go to 3);
the method is characterized in that in the step (3.b), the inter-relay force is calculated by adopting the following method:
wherein opwEither immediately preceding or succeeding the current operation,is opwThe length of the time frame of (a),to operate oniPost-dispatch opwThe length of the time frame of the update,
the invention improves the existing scheduling algorithm, and simplifies the calculation of indirect force in the calculation of involution force. While solving for intermediate relay for any predecessor or successorThe algorithm needs to be calculated before improvementDirect force generated by secondary predecessor or successor implicit scheduling is not needed to be considered independently in the improved algorithm, indirect force is calculated directly, and the time complexity of the algorithm can be changed from the original timeIs reduced toFor a large-scale integrated circuit, the invention obviously improves the reduction of the operation amount of the scheduling algorithm, and can effectively improve the running speed of the system without reducing the scheduling effect.
Drawings
FIG. 1 is a flow chart of an FPGA high-level scheduling algorithm.
Fig. 2 is a data flow diagram of embodiment 1.
Fig. 3 is a schematic diagram of the distribution of the operation time frames.
Fig. 4 is a diagram illustrating a scheduling result according to an embodiment.
Detailed Description
The invention improves the existing force guidance algorithm based on time frame length priority division, simplifies the calculation mode of indirect force, and avoids the complex calculation process of the indirect force when the length of the time frame of the predecessor or successor of the current operation is larger. The problem of excessive calculation in the force guidance algorithm can be further solved.
The invention is characterized in that the intermediate relay formula of the original algorithm is improved, and the intermediate relay formula (6) in the prior art is replaced by the following formula:
wherein the content of the first and second substances,representing operations opiScheduling to control step csjThen at opwAn average value of the initial pressure within the schedulable time frame range;represents opwInitial pressure average value in the range of the original time frame. Differencing the two terms may characterize the operation opiScheduling to control step csjIndirect effects of time. The algorithm time complexity of the improved intermediate relay can be reduced to
Selecting (op) with the smallest resultant forcei,csj) For scheduling, when the resultant force is the same, sigma can be selectedAlltypeK(csi) The smaller control step is scheduled.
And after the current operation scheduling is finished, updating the preceding time frame and the following time frame, and implicitly scheduling and deleting the operation to be scheduled, which can be determined by the child node after the parent node is scheduled.
When the probability distribution map needs to be updated, only the operation type and the time frame which affect the current operation type and the time frame thereof and the implicit scheduling are considered for updating.
To further illustrate the present invention, an analysis is performed according to the dataflow diagram shown in FIG. 2, assuming that all numbered operations are of the same type.
For the data stream shown in fig. 2, the operation time frame representation obtained by using the ASAP and ALAP algorithms is shown in fig. 3.
Wherein cs is1-cs5To control the step, op1-op10To operate, it can be seen that op1、op2、op4、op5、op8、op10For critical path operations, the only op to be scheduled is3、op6、op7、op9. (Note: conventional force-guided algorithms need to calculate the resultant force of all the operations, this documentIn the embodiment, the time frame is sorted according to the sorting length) and all the operation to be scheduled are sorted according to the time frame length and then are op6、op9、op3、op7And 2, the initial pressure distribution on each control step can be obtained through calculation and is shown in the table 1.
TABLE 1 initial pressure distribution over control steps
Control step | Initial pressure (K (cs)i)) |
|
1 |
|
4/3 |
cs3 | 19/6 |
|
8/3 |
cs5 | 11/6 |
First op6And (3) scheduling to obtain the following resultant force calculation formula:
(Note: since the scheduling of op6 to cs3 has no effect on predecessor successors, it is sufficient to directly calculate predecessor forces)
Selecting the operation-control step pair (op) with the smallest resultant force6,cs4) Will op6Scheduling to cs4,4.op9For its immediate successor operation, it can only be implicitly scheduled to cs5。
After updating probability distribution, p pairs3Scheduling is carried out to obtain Will op3Scheduling to cs2. Subsequent op7Can be scheduled to cs3、cs4And cs5Updating the probability distribution map, F (op)7,cs3)=0,F(op7,cs4)=0,F(op7,cs5) And (4) performing scheduling in the optional control step, and performing scheduling for three times to obtain a final result as shown in fig. 4.
Claims (1)
- The FPGA high-level comprehensive scheduling method comprises the following steps:1) the time frame length for each operation is calculated:operation opiMay be expressed asWherein ALAP (op)i) Representing operations opiThe latest control step that can be scheduled is recorded asASAP(opi) To operate oniThe earliest control step that can be scheduled is recorded as2) Calculating the sum of the occurrence probability of each operation in each control step according to the time frame to obtain probability distribution:operation opiIn a control step csjProbability P (op)i,csj) Comprises the following steps:the probability distribution over each control step is as follows:where n is the total number of operations of that type, K (cs)j) Indicating the control step csjAn initial pressure on;3) judging whether operations which are not scheduled exist, if so, calculating direct force and indirect force of all operations to be scheduled to each control step in the time frame, and selecting (op) with minimum resultant forcei,csj) Scheduling, and setting the length of the current operation time frame as 1, otherwise ending the scheduling;wherein the content of the first and second substances,(3.a) calculating the direct force: let x (cs)k) Represents an operation opiScheduling to control step csjWhen, P (op)i,csj) In a control step csjThe generated variable is to be operated oniScheduling to control step csjThe direct forces generated are:(3.b) calculating the inter-relay;4) updating the time frames of the direct predecessor and direct successor of the operation;5) updating the probability distribution, go to 3);the method is characterized in that in the step (3.b), the inter-relay force is calculated by adopting the following method:
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL6505645A (en) * | 1964-05-04 | 1965-11-05 | ||
GB0002874D0 (en) * | 1999-06-03 | 2000-03-29 | Sharp Kk | Scheduling method for high-level synthesis and recording medium |
JP2000148808A (en) * | 1998-11-06 | 2000-05-30 | Nec Corp | Method for verifying correctness of structural rtl for scheduled motion description |
US20050193359A1 (en) * | 2004-02-13 | 2005-09-01 | The Regents Of The University Of California | Method and apparatus for designing circuits using high-level synthesis |
WO2007124048A2 (en) * | 2006-04-19 | 2007-11-01 | Trustees Of Princeton University | A hybrid nanotube/cmos dynamically reconfigurable architecture and an integrated design optimization method and system therefor |
US20120065956A1 (en) * | 2010-08-31 | 2012-03-15 | The Regents Of The University Of California | Digital processors |
CN104360906A (en) * | 2014-10-31 | 2015-02-18 | 中山大学 | High-level comprehensive scheduling method based on difference constraint system and iterative model |
CN106599366A (en) * | 2016-11-11 | 2017-04-26 | 中国人民解放军国防科学技术大学 | High-level integrated dispatching method based on motility |
CN110334436A (en) * | 2019-07-03 | 2019-10-15 | 腾讯科技(深圳)有限公司 | A kind of data processing method and equipment |
-
2020
- 2020-09-30 CN CN202011062643.0A patent/CN112148456B/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL6505645A (en) * | 1964-05-04 | 1965-11-05 | ||
JP2000148808A (en) * | 1998-11-06 | 2000-05-30 | Nec Corp | Method for verifying correctness of structural rtl for scheduled motion description |
GB0002874D0 (en) * | 1999-06-03 | 2000-03-29 | Sharp Kk | Scheduling method for high-level synthesis and recording medium |
US20050193359A1 (en) * | 2004-02-13 | 2005-09-01 | The Regents Of The University Of California | Method and apparatus for designing circuits using high-level synthesis |
WO2007124048A2 (en) * | 2006-04-19 | 2007-11-01 | Trustees Of Princeton University | A hybrid nanotube/cmos dynamically reconfigurable architecture and an integrated design optimization method and system therefor |
US20120065956A1 (en) * | 2010-08-31 | 2012-03-15 | The Regents Of The University Of California | Digital processors |
CN104360906A (en) * | 2014-10-31 | 2015-02-18 | 中山大学 | High-level comprehensive scheduling method based on difference constraint system and iterative model |
CN106599366A (en) * | 2016-11-11 | 2017-04-26 | 中国人民解放军国防科学技术大学 | High-level integrated dispatching method based on motility |
CN110334436A (en) * | 2019-07-03 | 2019-10-15 | 腾讯科技(深圳)有限公司 | A kind of data processing method and equipment |
Non-Patent Citations (3)
Title |
---|
SUN QIANG: "A peak power optimization scheduling algorithm for multi-cycle operation" * |
刘乙力等: "基于时间约束的高层次综合调度方法" * |
司巧梅等: "一种面向多周期操作的峰值功耗优化调度算法" * |
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