CN112134809B - Flow control method, device, equipment and readable storage medium - Google Patents
Flow control method, device, equipment and readable storage medium Download PDFInfo
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
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- H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
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Abstract
The invention discloses a flow control method, a flow control device, flow control equipment and a readable storage medium, wherein the flow control method comprises the following steps: the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation information; and adjusting the data transmission speed by using the speed regulation information. In the method, the data transmission speed can be adjusted according to the flow regulation packet transmitted by the opposite-end FPGA card without equipment such as a gateway and the like. And compared with the existing flow control mechanism which can only realize the stop-and-equation, the method can adjust the data transmission speed and can meet the requirements of more actual flow control conditions.
Description
Technical Field
The present invention relates to the field of computer application technologies, and in particular, to a flow control method, apparatus, device, and readable storage medium.
Background
FPGA (Field Programmable GATE ARRAY ) accelerator cards are used in large numbers in data centers. Such FPGA accelerator cards typically have a standard MAC (MEDIA ACCESS Control, ethernet) network port, and in engineering practice, there are a number of situations where two FPGA accelerator cards are interconnected through the MAC network port. How to control the network traffic between FPGA accelerator cards becomes an increasingly critical engineering practical problem.
Under the full duplex MAC control framework, the flow control mechanism is a simple stop-and-go flow control mechanism implemented by a PAUSE (ethernet frame formatted in accordance with the IEEE 802.3 protocol) function. This flow control mechanism only allows for simple stop-and-equal flow operation. In other schemes, the gateway and other devices are involved to realize flow control.
In summary, how to effectively solve the problems of flow control between FPGA cards is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a flow control method, a flow control device, flow control equipment and a readable storage medium, so as to realize more accurate flow control among FPGA cards.
In order to solve the technical problems, the invention provides the following technical scheme:
a flow control method, comprising:
the FPGA card sends data to the opposite-end FPGA card;
Receiving the flow regulation data packet sent by the opposite-end FPGA card;
analyzing the flow regulation data packet to obtain speed regulation information;
And adjusting the data transmission speed by using the speed regulation information.
Preferably, the parsing the flow adjustment data packet to obtain speed adjustment information includes:
analyzing the frame corresponding to the flow regulation data packet to obtain data content corresponding to the data and the filling field;
And extracting the speed regulation information from the data content.
Preferably, extracting the speed regulation information from the data content includes:
And extracting at least one speed regulation information of control stage information, regulation duration information and reference speed information from the data content.
Preferably, the parsing the frame corresponding to the flow adjustment data packet to obtain the data content corresponding to the data and the filling field includes:
sequentially reading values from the data and padding fields according to the corresponding specified byte lengths;
and analyzing the numerical value according to byte definition to obtain the data content.
Preferably, if the speed regulation information includes the regulation duration information and the reference speed information, correspondingly, using the speed regulation information, the data transmission speed is regulated, including:
In a time period corresponding to the regulation and control duration information, data transmission is carried out according to the data transmission speed corresponding to the reference speed information;
or smoothly transitioning the data transmission speed from the current data transmission speed to the reference speed information in a time period corresponding to the regulation duration information.
Preferably, the method further comprises:
receiving data sent by the opposite-end FPAG card, and acquiring a data receiving speed;
Determining whether the data transmission speed needs to be adjusted by utilizing the data receiving speed;
and if so, sending the flow regulation data packet to the opposite-end FPGA card.
Preferably, determining whether the data transmission speed needs to be adjusted using the data reception speed includes:
According to each regulation range, determining a target regulation stage corresponding to the data receiving speed from the corresponding regulation stages;
if the target regulation and control stage corresponds to regulation and control, determining that the data transmission speed needs to be regulated;
And if the target regulation and control stage corresponds to regulation and control not needed, determining that the data transmission speed does not need to be regulated.
A flow control device, comprising:
The data sending module is used for sending data to the opposite-end FPGA card by the FPGA card;
The flow regulation data packet receiving module is used for receiving the flow regulation data packet sent by the opposite-end FPGA card;
The speed regulation information acquisition module is used for analyzing the flow regulation data packet to obtain speed regulation information;
And the speed regulation and control module is used for regulating the data transmission speed by utilizing the speed regulation and control information.
A flow control device, comprising:
a memory for storing a computer program;
And the processor is used for realizing the steps of the flow control method when executing the computer program.
A readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the flow control method described above.
By applying the method provided by the embodiment of the invention, the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation information; and adjusting the data transmission speed by using the speed regulation information.
In the method, under the condition that the FPGA card sends data to the opposite-end FPGA card, if a flow regulation data packet sent by the opposite-end FPGA card is received, the flow regulation data packet can be analyzed to obtain speed regulation information. And then adjusting the data transmission speed based on the speed regulation information. That is, in the method, the data transmission speed can be adjusted according to the flow regulation packet transmitted by the opposite-end FPGA card without equipment such as a gateway. And compared with the existing flow control mechanism which can only realize stop-and-equation, the method can regulate the data transmission speed and can meet the requirements of more actual flow control conditions.
Correspondingly, the embodiment of the invention also provides a flow control device, a device and a readable storage medium corresponding to the flow control method, which have the technical effects described above and are not repeated here.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a flow control method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an application system corresponding to a flow control method according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating another flow control method according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating an embodiment of a flow control method according to the present invention;
FIG. 5 is a schematic diagram of a flow control device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a flow control device according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of a specific structure of a flow control device according to an embodiment of the present invention.
Detailed Description
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of a flow control method according to an embodiment of the invention, the method includes the following steps:
s101, the FPGA card sends data to the opposite-end FPGA card.
The FPGA card and the opposite-end FPGA card correspond to a source end and a terminal of data transmission. The model numbers between the FPGA card and the opposite-end FPGA card can be the same or different.
The FPGA card sends data to the opposite-end FPGA card, and the opposite-end FPGA card can determine whether to adjust the data sending speed according to the actual processing condition, and can send flow regulation data packets to the FPGA card if the data sending speed needs to be adjusted.
It should be further noted that, in the embodiment of the present invention, the FPGA card and the opposite-end FPGA card are only relatively speaking, and the FPGA card may also receive the data sent by the opposite-end FPGA card. Namely, the data transmission can be carried out in a simplex, half duplex or full duplex mode between the FPGA card and the opposite-end FPGA card.
S102, receiving a flow regulation data packet sent by the opposite-end FPGA card.
The opposite-end FPGA card determines that flow regulation is needed, and then sends a regulation data packet. The regulation data packet may carry specific information about speed regulation.
S103, analyzing the flow regulation data packet to obtain speed regulation information.
And analyzing the flow data packet according to a transmission protocol corresponding to the flow regulation data packet to obtain speed regulation information. Specifically, according to a specific frame format definition, a data frame corresponding to the flow regulation data packet is interpreted, so that speed regulation information carried by the flow regulation data packet is obtained.
The speed regulation information is regulation information for regulating the data transmission speed by reference. The speed regulation information may be specific speed parameters, such as one or more of specific reference speed for regulating the data transmission speed, duration of speed regulation, and speed regulation direction (such as acceleration or deceleration); the speed regulation information may be specific or may be a label of the regulation stage (e.g. a specific mode of the regulation stage corresponding to the transmission speed of the regulation data is predefined).
In an embodiment of the present invention, the step S103 may specifically include:
Analyzing the frame corresponding to the flow regulating data packet to obtain the data content corresponding to the data and the filling field.
Wherein, the flow control data packet frame format can adopt an IEEE802.3 Ethernet frame format. Referring to table 1, a data frame for regulating network traffic is predefined on the basis of the data frame, and is located in a DATA AND PAD (data and padding) field.
Table 1, flow control packet frame format
| Preamble | SFD | dst MAC | src MAC | Length | Type | IP head | UDP head | Data and Pad | FCS |
Wherein, preamble: a preamble, 7 bytes, used for synchronizing the sending and receiving rates of two parties in the data transmission process;
SFD: a frame start character, 1 byte, indicating that the next byte starts to be real data (destination MAC address);
dst MAC: destination MAC address, 6 bytes, indicating the recipient of the frame;
src MAC: a source MAC address, 6 bytes, indicating the sender of the frame;
length: a length of 2 bytes indicating the length of the frame data field;
type: type, 2 bytes, indicating the protocol type of the data in the frame;
IP head: IP, datagram header;
UDP head: a UDP datagram frame header;
DATA AND PAD: the custom data format is used for flow control;
FCS: a frame check sequence.
Specifically, the flow regulation data packet is analyzed according to a frame format corresponding to the flow regulation data packet, so as to obtain data content corresponding to the data and the filling field.
Specifically, the implementation process for reading the data content includes:
step 1, sequentially reading numerical values from the data and filling fields according to the corresponding appointed byte length;
And 2, analyzing the value according to the byte definition to obtain the data content.
For convenience of description, please refer to fig. 2, the following description will be given by combining the above 2 steps.
In fig. 2, a TX side flow monitoring module is used to monitor the data flow rate of the MAC TX. The RX side flow monitoring and TX control module is used for monitoring the receiving data flow speed of the MAC RX and controlling the data flow sending speed of the MAC TX. The opposite end module flow adjustment indicating module is used for sending a flow adjustment data packet to the opposite side through MAC TX to adjust and control the MAC TX flow sending of the opposite side. The MAC TX and the MAC RX are MAC transmitting ends and receiving ends in the FPGA. The FPGA a card may be an opposite-end FPGA card, and of course, the FPGA B card may also be an opposite-end FPGA card.
DATA AND PAD is a custom data frame for flow control in this embodiment. For specific format, refer to table 2.
TABLE 2 data and Pad definitions
| ctrl_flag | ctrl_action | ctrl_rate | ctrl_time | ctrl_stop | ctrl_warning | other_data |
Wherein, ctrl_flag: the 4 bytes, including but not limited to a characteristic codeword, such as 0x8808_593d, represent that the present packet is for an FPGA to regulate network traffic.
Ctrl_action:2 bits, wherein a value 1 indicates that the current MAC RX flow (data receiving speed) of the card (namely the FPGA card) is close to a threshold value in a network flow early warning stage of the opposite party; the value 2 represents the regulation stage of the network flow of the opposite side, and represents that the current MAC RX side flow (data transmission speed) of the FPGA card just jumps over the threshold value; the value 3 indicates that the opposite network traffic stopping stage is needed, and indicates that the current MAC RX side flow of the card severely crosses the threshold. The value 0 indicates that the other party does not need to react.
Ctrl_rate:2 bytes, indicating that when ctrl_action=1 or 2, the command peer needs to adjust the network traffic on its MAC TX side to the corresponding reference speed.
Ctrl_time:2 bytes, the duration of the current flow control, and a value of 0 indicates the end of the current flow control.
Ctrl_stop:1bit, 0 invalid, 1 indicates that the MAC TX end of the other party is required to stop sending packets.
Ctrl_warning: when ctrl_action=1 or 2, 2bit is 2, the value 1 indicates that the transmission speed of the MAC TX end of the opposite party needs to be reduced, and the value 2 indicates that the transmission speed of the MAC TX end of the opposite party needs to be increased. The value 0 indicates a default value, invalid.
Other_data: other message data.
I.e., data content, i.e., meaning the content corresponding to the value read in the DATA AND PAD field.
And step two, extracting speed regulation information from the data content.
And obtaining speed regulation information according to the data content. For example, if ctrl_stop is 1, it is determined that the speed regulation information includes stopping data transmission.
The second step may specifically include: at least one of control phase information, regulation duration information and reference speed information is extracted from the data content.
That is, information that at least one of control phase information, regulation duration information, and parameter speed information can be used to regulate the data transmission speed can be extracted.
S104, adjusting the data transmission speed by using the speed regulation information.
After the speed regulation information is obtained, the data transmission speed can be regulated based on the depth regulation information. Specifically, if the speed regulation information includes a specific speed parameter, the data sending speed can be directly regulated to be matched with the speed parameter; and if the speed regulation information is a label of the regulation stage, regulating the data transmission speed according to the specific mode of the corresponding regulation stage.
In a specific embodiment of the present invention, if the speed regulation information includes the regulation duration information and the reference speed information, the following two cases may be respectively referred to in step S104:
and 1, in a time period corresponding to the regulation and control duration information, carrying out data transmission according to the data transmission speed corresponding to the reference speed information.
That is, a period of time is defined in which the adjusted speed matches the reference speed information and the duration corresponds to the regulation duration information.
For example, if the current data transmission speed is V1 and the reference speed corresponding to the reference data information is V2, the data transmission speed is directly adjusted from V1 to V2, and is continuously maintained at V2 in the period T corresponding to the adjustment duration information.
And 2, smoothly transitioning the data transmission speed from the current data transmission speed to the reference speed information in a time period corresponding to the regulation and control duration information.
That is, a time period is defined in which the adjusted speed matches the reference speed information and the adjustment of the data transmission speed takes a time period corresponding to the adjustment duration information.
For example, if the current data transmission speed is V1 and the reference speed corresponding to the reference data information is V2, the data transmission speed is adjusted from V1 to V2 in the period T corresponding to the adjustment duration information.
It should be noted that, according to actual requirements, the adjustment mode corresponding to the case 1 or the case 2 may be selected to be executed.
By applying the method provided by the embodiment of the invention, the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation information; and adjusting the data transmission speed by using the speed regulation information.
In the method, under the condition that the FPGA card sends data to the opposite-end FPGA card, if a flow regulation data packet sent by the opposite-end FPGA card is received, the flow regulation data packet can be analyzed to obtain speed regulation information. And then adjusting the data transmission speed based on the speed regulation information. That is, in the method, the data transmission speed can be adjusted according to the flow regulation packet transmitted by the opposite-end FPGA card without equipment such as a gateway. And compared with the existing flow control mechanism which can only realize stop-and-equation, the method can regulate the data transmission speed and can meet the requirements of more actual flow control conditions.
It should be noted that, based on the above embodiments, the embodiments of the present invention further provide corresponding improvements. The preferred/improved embodiments relate to the same steps as those in the above embodiments or the steps corresponding to the steps may be referred to each other, and the corresponding advantages may also be referred to each other, so that detailed descriptions of the preferred/improved embodiments are omitted herein.
In a specific embodiment of the present invention, based on the above embodiment, the FPGA card may further send a flow regulation data packet corresponding to the regulation data sending speed to the opposite FPGA card. Of course, the specific implementation of sending the flow regulation data packet by the opposite-end FPGA card can also refer to this.
Referring to fig. 3, fig. 3 is a flowchart illustrating another implementation of a flow control method according to an embodiment of the present invention, where the implementation process includes:
S201, receiving data sent by the FPAG card at the opposite end, and acquiring a data receiving speed.
That is, when the FPGA card receives data sent by the opposite-end FPGA card, the FPGA card can monitor the data receiving speed, so as to obtain the data receiving speed.
S202, determining whether the data transmission speed needs to be adjusted or not by utilizing the data receiving speed.
After the data reception speed is obtained, it may be determined whether the transmission speed of the data needs to be adjusted based on the data reception speed. The data sending speed refers to the speed of sending data to the local card by the opposite-end FPGA card, and is not the speed of sending data outwards by the local card.
Specifically, the FPGA card may be configured to match the processing efficiency with the data receiving speed according to the current processing efficiency, so that no adjustment is required, and if the processing efficiency is not matched with the data receiving speed (for example, the processing efficiency is too low, the received data cannot be effectively processed, or the processing efficiency is high, and more data can be processed), the adjustment is required.
Of course, the adjustment threshold may be directly set, and the corresponding relationship between the data sending speed and the adjustment threshold may be determined, so as to determine whether adjustment is required. For example, an upper threshold and a lower threshold are set, and if the data receiving speed is greater than the upper threshold, it is determined that the data sending speed needs to be adjusted (such as speed reduction or stopping); if the data receiving speed is less than the lower threshold, it is determined that the data sending speed needs to be adjusted (e.g., accelerated).
In one embodiment of the present invention, the judging process specifically includes:
step one, determining a target regulation stage corresponding to the data receiving speed from the corresponding regulation stages according to each regulation range;
Step two, if the target regulation and control stage corresponds to regulation and control, determining the data transmission speed to be regulated;
And step three, if the target regulation and control stage corresponds to regulation and control not needed, determining that the data transmission speed is not needed to be regulated.
For convenience of description, the following description will be given by combining the above three steps.
Referring to the table 3 of the drawings, in this example,
TABLE 3 MAC RX side speed X and regulatory policy specification list
Wherein the MAC RX side flow has an upper threshold representing maximum speed and a lower threshold representing minimum speed.
That is, the regulation phase can be determined by the current data reception speed, and then it is clear whether the data transmission speed adjustment is currently to be performed.
If yes, executing step S203; if the judgment result is negative, executing the executable operation.
S203, sending a flow regulation data packet to the opposite-end FPGA card.
For specific frame formats of the traffic control packet, and how to carry the control information, reference is made to the above embodiments.
After receiving the flow regulation data packet, the opposite-end FPGA can process the flow regulation data packet with reference to the specific adjustment process of the data transmission speed described in the above embodiment.
For easy understanding, please refer to fig. 4, in which the flow control method is described in detail below with reference to a specific application flowchart.
Step 1, powering up and initializing an FPGA board card (namely a PPGA card), updating numerical values in an upper limit threshold value register and a lower limit threshold value register, and entering step 2.
Step 2, the MAC TX of the opposite-end FPGA card sends data, and the MAC RX of the opposite-end FPGA card receives the data and enters step 3.
Step 3, matching the data receiving speed of the FPGA card on the MAC RX side with the data receiving speed of the FPGA card on the table 3, and entering step 4.
And step 4, judging whether the flow needs to be regulated or not, if not, jumping to the step 2, and if so, judging the step 5.
And 5, the FPGA card sends a flow regulation data packet to the opposite-end FPGA card through the MAC TX end.
Step 6, the MAC RX of the opposite-end FPGA card receives and analyzes the data regulation data packet, timing is started, and step 7 is entered;
And 7, regulating the sending speed of the MAC TX end of the data packet according to the received data by the opposite side, wherein the regulating speed is gradually regulated to the reference speed of ctrl_rate from the current speed, sending data by the opposite side MAC TX, receiving data by the MAC RX of the FPGA card, and entering the step 8.
And 8, comparing the timer time with ctrl_time, judging whether the timer is up, if so, executing the step 2, and if not, executing the step 9.
And 9, adjusting whether the network flow speed meets the expectations, if so, entering the step 2, and if not, entering the step 7.
Therefore, the flow control method provided by the embodiment of the invention can realize the prevention of network congestion and the quantitative regulation and control of network flow among the FPGA boards. The method has a certain practical significance in meeting the actual engineering demands.
Corresponding to the above method embodiments, the embodiments of the present invention further provide a flow control device, where the flow control device described below and the flow control method described above may be referred to correspondingly.
Referring to fig. 5, the apparatus includes the following modules:
the data sending module 101 is used for sending data to the opposite-end FPGA card by the FPGA card;
The flow regulation data packet receiving module 102 is used for receiving a flow regulation data packet sent by the opposite-end FPGA card;
the speed regulation information acquisition module 103 is used for analyzing the flow regulation data packet to obtain speed regulation information;
The speed regulation module 104 is configured to regulate the data transmission speed according to the speed regulation information.
By applying the device provided by the embodiment of the invention, the FPGA card sends data to the opposite-end FPGA card; receiving a flow regulation data packet sent by an opposite-end FPGA card; analyzing the flow regulation data packet to obtain speed regulation information; and adjusting the data transmission speed by using the speed regulation information.
In the device, under the condition that the FPGA card sends data to the opposite-end FPGA card, if the flow regulation data packet sent by the opposite-end FPGA card is received, the flow regulation data packet can be analyzed to obtain speed regulation information. And then adjusting the data transmission speed based on the speed regulation information. That is, in the device, the data transmission speed can be adjusted according to the flow regulation packet transmitted by the opposite-end FPGA card without equipment such as a gateway. And compared with the existing flow control mechanism which can only realize stop-and-equation, the device can regulate the data transmission speed and can meet the requirements of more actual flow control conditions.
In a specific embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to parse a frame corresponding to a flow regulation data packet to obtain data content corresponding to data and a filling field; and extracting speed regulation information from the data content.
In one embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to extract at least one speed regulation information of the control phase information, the regulation duration information, and the reference speed information from the data content.
In one embodiment of the present invention, the speed regulation information obtaining module 103 is specifically configured to sequentially read values from the data and the padding fields according to the corresponding specified byte length; and analyzing the value according to the byte definition to obtain the data content.
In a specific embodiment of the present invention, if the speed regulation information includes regulation duration information and reference speed information, the speed regulation module 104 is specifically configured to perform data transmission according to a data transmission speed corresponding to the reference speed information in a period corresponding to the regulation duration information; or smoothly transitioning the data transmission speed from the current data transmission speed to the reference speed information in the time period corresponding to the regulation duration information.
In one embodiment of the present invention, the method further comprises:
The regulation and control initiating module is used for receiving data sent by the FPAG card at the opposite end and acquiring the data receiving speed; determining whether the data transmission speed needs to be adjusted by utilizing the data receiving speed; if yes, sending a flow regulation data packet to the opposite-end FPGA card.
In a specific embodiment of the present invention, the regulation initiating module is specifically configured to determine, according to each regulation range, a target regulation stage corresponding to the data receiving speed from the corresponding regulation stages; if the target regulation and control stage corresponds to regulation and control, determining the data transmission speed to be regulated; and if the target regulation and control stage corresponds to regulation and control not needed, determining that the data transmission speed is not needed to be regulated.
Corresponding to the above method embodiments, the present invention further provides a flow control device, and a flow control device described below and a flow control method described above may be referred to correspondingly.
Referring to fig. 6, the flow control apparatus includes:
A memory 332 for storing a computer program;
A processor 322 for implementing the steps of the flow control method of the method embodiment described above when executing a computer program.
Specifically, referring to fig. 7, fig. 7 is a schematic diagram of a specific structure of a flow control device according to the present embodiment, where the flow control device may have a relatively large difference due to different configurations or performances, and may include one or more processors (central processing units, CPU) 322 (e.g., one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Wherein the memory 332 may be transient storage or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a series of instruction operations in the data processing apparatus. Still further, the central processor 322 may be configured to communicate with the memory 332 and execute a series of instruction operations in the memory 332 on the flow control device 301.
The flow control device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input/output interfaces 358, and/or one or more operating systems 341.
The steps in the flow control method described above may be implemented by the structure of the flow control device.
Corresponding to the above method embodiments, the embodiments of the present invention further provide a readable storage medium, where a readable storage medium described below and a flow control method described above may be referred to correspondingly.
A readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the flow control method of the above method embodiments.
The readable storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, which may store various program codes.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not intended to be limiting.
Claims (7)
1. A flow control method, comprising:
the FPGA card sends data to the opposite-end FPGA card;
Receiving a flow regulation data packet sent by the opposite-end FPGA card;
Analyzing the flow regulation data packet to obtain speed regulation information;
Adjusting the data transmission speed by utilizing the speed regulation information;
The flow regulation data packet is analyzed to obtain speed regulation information, which comprises the following steps:
Analyzing the frame corresponding to the flow control data packet to obtain data content corresponding to the data and the filling field;
extracting the speed regulation information from the data content;
Wherein extracting the speed regulation information from the data content includes:
Extracting at least one speed regulation information of control stage information, regulation duration information and reference speed information from the data content;
If the speed regulation information includes the regulation duration information and the reference speed information, correspondingly, regulating the data sending speed by using the speed regulation information includes:
In a time period corresponding to the regulation and control duration information, data transmission is carried out according to the data transmission speed corresponding to the reference speed information;
or smoothly transitioning the data transmission speed from the current data transmission speed to the reference speed information in a time period corresponding to the regulation and control duration information;
The frame format of the flow control data packet sequentially comprises:
Preamble、SFD、dst MAC、src MAC、Length、Type、IP head、UDP head、Data and Pad、FCS；
Wherein, preamble: a preamble, 7 bytes, used for synchronizing the sending and receiving rates of two parties in the data transmission process;
SFD: a frame initiator, 1 byte, indicating that the next byte begins to be real data;
dst MAC: destination MAC address, 6 bytes, indicating the recipient of the frame;
src MAC: a source MAC address, 6 bytes, indicating the sender of the frame;
length: a length of 2 bytes indicating the length of the frame data field;
type: type, 2 bytes, indicating the protocol type of the data in the frame;
IP head: IP, datagram header;
UDP head: a UDP datagram frame header;
DATA AND PAD: the custom data format is used for flow control;
FCS: a frame check sequence;
Wherein DATA AND PAD is a custom data frame for flow control, and the frame format sequentially comprises: ctrl_flag, ctrl_action, ctrl_rate, ctrl_time, ctrl_stop, ctrl_ warning, other _data;
wherein, ctrl_flag:4 bytes including a characteristic codeword;
ctrl_action:2 bits, wherein the value 1 represents a phase for early warning of network traffic of the opposite party; the value 2 represents the regulation and control stage of the network flow of the opposite party; a value 3 indicates that the network flow of the other party is stopped, and a value 0 indicates that the other party does not need to react;
ctrl_rate:2 bytes, which means that when ctrl_action=1 or 2, the command peer needs to adjust the network traffic on its MAC TX side to the corresponding reference speed;
ctrl_time:2 bytes, the duration of the current flow regulation, and a value of 0 indicates the end of the current flow regulation;
ctrl_stop:1bit, 0 invalid, 1 represents that the MAC TX end of the opposite party is required to stop sending packets;
ctrl_warning:2 bits, when ctrl_action=1 or 2, the value 1 indicates that the transmission speed of the MAC TX end of the opposite party needs to be reduced, and the value 2 indicates that the transmission speed of the MAC TX end of the opposite party needs to be increased; a value of 0 represents a default value, invalid;
other_data: other message data.
2. The flow control method according to claim 1, wherein parsing the frame corresponding to the flow control packet to obtain data content corresponding to the data and the padding field, comprises:
sequentially reading values from the data and padding fields according to the corresponding specified byte lengths;
and analyzing the numerical value according to byte definition to obtain the data content.
3. The flow control method according to claim 1 or 2, characterized by further comprising:
Receiving data sent by the opposite-end FPGA card, and acquiring data receiving speed;
Determining whether the data transmission speed needs to be adjusted by utilizing the data receiving speed;
and if so, sending the flow regulation data packet to the opposite-end FPGA card.
4. The flow control method according to claim 3, wherein determining whether the data transmission speed needs to be adjusted using the data reception speed comprises:
According to each regulation range, determining a target regulation stage corresponding to the data receiving speed from the corresponding regulation stages;
if the target regulation and control stage corresponds to regulation and control, determining that the data transmission speed needs to be regulated;
And if the target regulation and control stage corresponds to regulation and control not needed, determining that the data transmission speed does not need to be regulated.
5. A flow control device, comprising:
The data sending module is used for sending data to the opposite-end FPGA card by the FPGA card;
the flow regulation data packet receiving module is used for receiving the flow regulation data packet sent by the opposite-end FPGA card;
The speed regulation information acquisition module is used for analyzing the flow regulation data packet to obtain speed regulation information;
the speed regulation and control module is used for regulating the data transmission speed by utilizing the speed regulation and control information;
The speed regulation information acquisition module is specifically configured to analyze a frame corresponding to the flow regulation data packet to obtain data content corresponding to data and a filling field; extracting the speed regulation information from the data content; wherein extracting the speed regulation information from the data content includes: extracting at least one speed regulation information of control stage information, regulation duration information and reference speed information from the data content;
If the speed regulation and control information comprises the regulation and control duration information and the reference speed information, correspondingly, the speed regulation and control module is specifically configured to perform data transmission according to the data transmission speed corresponding to the reference speed information in a time period corresponding to the regulation and control duration information; or smoothly transitioning the data transmission speed from the current data transmission speed to the reference speed information in a time period corresponding to the regulation and control duration information;
The frame format of the flow control data packet sequentially comprises:
Preamble、SFD、dst MAC、src MAC、Length、Type、IP head、UDP head、Data and Pad、FCS；
Wherein, preamble: a preamble, 7 bytes, used for synchronizing the sending and receiving rates of two parties in the data transmission process;
SFD: a frame initiator, 1 byte, indicating that the next byte begins to be real data;
dst MAC: destination MAC address, 6 bytes, indicating the recipient of the frame;
src MAC: a source MAC address, 6 bytes, indicating the sender of the frame;
length: a length of 2 bytes indicating the length of the frame data field;
type: type, 2 bytes, indicating the protocol type of the data in the frame;
IP head: IP, datagram header;
UDP head: a UDP datagram frame header;
DATA AND PAD: the custom data format is used for flow control;
FCS: a frame check sequence;
Wherein DATA AND PAD is a custom data frame for flow control, and the frame format sequentially comprises: ctrl_flag, ctrl_action, ctrl_rate, ctrl_time, ctrl_stop, ctrl_ warning, other _data;
wherein, ctrl_flag:4 bytes including a characteristic codeword;
ctrl_action:2 bits, wherein the value 1 represents a phase for early warning of network traffic of the opposite party; the value 2 represents the regulation and control stage of the network flow of the opposite party; a value 3 indicates that the network flow of the other party is stopped, and a value 0 indicates that the other party does not need to react;
ctrl_rate:2 bytes, which means that when ctrl_action=1 or 2, the command peer needs to adjust the network traffic on its MAC TX side to the corresponding reference speed;
ctrl_time:2 bytes, the duration of the current flow regulation, and a value of 0 indicates the end of the current flow regulation;
ctrl_stop:1bit, 0 invalid, 1 represents that the MAC TX end of the opposite party is required to stop sending packets;
ctrl_warning:2 bits, when ctrl_action=1 or 2, the value 1 indicates that the transmission speed of the MAC TX end of the opposite party needs to be reduced, and the value 2 indicates that the transmission speed of the MAC TX end of the opposite party needs to be increased; a value of 0 represents a default value, invalid;
other_data: other message data.
6. A flow control device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the flow control method according to any one of claims 1 to 4 when executing said computer program.
7. A readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the flow control method according to any of claims 1 to 4.
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