CN112134554B

CN112134554B - Equalization circuit

Info

Publication number: CN112134554B
Application number: CN201910493045.XA
Authority: CN
Inventors: 刘曜嘉; 陈柏羽
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-06-06
Filing date: 2019-06-06
Publication date: 2024-09-03
Anticipated expiration: 2039-06-06
Also published as: CN112134554A

Abstract

The equalization circuit comprises a first operation circuit, a second operation circuit, a data sampling circuit and a marginal sampling circuit. The first operation circuit is used for compensating an equalization sequence by a plurality of slave feedback sequences and outputting a first summation sequence. The second operation circuit is used for compensating the first summation sequence by a main feedback sequence and outputting a second summation sequence. The data sampling circuit samples the second summation sequence according to a data clock to output a main sequence, and gains the main sequence to output the main feedback sequence. The data sampling circuit sequentially samples the master sequence according to the data clock so as to output a plurality of slave sequences, and the data sampling circuit gains the corresponding slave sequences so as to output the slave feedback sequences. The marginal sampling circuit is used for sequentially sampling the first summation sequence according to a marginal clock so as to output a marginal sequence.

Description

Equalization circuit

Technical Field

The present disclosure relates to an equalization circuit, and more particularly, to an equalization circuit having a main sequence direction circuit.

Background

Referring to fig. 1, the decision feedback equalizer of the present invention has an input 90, a data sampling circuit 92, and a margin sampling circuit 94. The data sampling circuit 92 has an adder 920, first to third D-type flip-flops 921, 922, 923, and first to third amplifiers 924, 925, 926, which are serially connected in sequence. Adder 920 adds the equalized sequence received from input 90, the first feedback sequence fs1 received from first amplifier 924, the second feedback sequence fs2 received from second amplifier 925, and the third feedback sequence fs3 received from third amplifier 926, thereby outputting an added signal Sadd, wherein first D-flip-flop 921 samples the added signal Sadd according to the data clock to output a first data sequence ds1, and first amplifier 924 gains the first data sequence ds1 as the first feedback sequence fs1. The second D-type flip-flop 922 samples the first data sequence ds1 in clock to output a second data sequence ds2, and the second amplifier 925 gains the second data sequence ds2 to be a second feedback sequence fs2. The third D-type flip-flop 923 clocks the second data sequence ds2 to output a third data sequence ds3, and the third amplifier 925 gains the third data sequence ds3 to be a third feedback sequence fs3.

Referring to fig. 2A and 2B, fig. 2A is an eye diagram (EYE DIAGRAM) of the equalization sequence, and fig. 2B is an eye diagram of the addition signal Sadd (output on the right side of the adder). Compared to the eye diagram of the equalization sequence shown in fig. 2A, the amplitude of the added signal shown in fig. 2B produces a marginal amplitude shifted to the left on the data clock, i.e., the adder does not remove the marginal effect of the added signal, but only removes the marginal effect of the data.

Disclosure of Invention

In view of the above, an equalization circuit includes a first operation circuit, a second operation circuit, a data sampling circuit, and a marginal sampling circuit. The first operation circuit is used for compensating an equalization sequence by a plurality of slave feedback sequences to output a first summation sequence. The second operation circuit is used for compensating the first summation sequence by a main feedback sequence so as to output a second summation sequence. The data sampling circuit comprises a master sequence direction circuit and a plurality of slave sequence direction circuits. The main sequence direction circuit is used for sampling the second summation sequence according to a data clock to output a main sequence, and the main sequence direction circuit gains the main sequence to output the main feedback sequence. The slave sequence-to-circuit is used for sampling the master sequence in sequence according to the data clock so as to output the slave sequences, and the slave sequence-to-circuit gains corresponding slave sequences so as to output the slave feedback sequences. The marginal sampling circuit is used for sampling the first summation sequence according to a marginal clock so as to output a marginal sequence.

According to some embodiments, the data sampling circuit includes two slave sequence circuits, the two slave sequence circuits are a first slave sequence circuit and a second slave sequence circuit, the first slave sequence circuit is used for sampling the master sequence according to the data clock to output a first slave sequence, and the first slave sequence circuit gains the first slave sequence and outputs the first slave sequence as a first slave feedback sequence; the second slave sequence circuit is used for sampling the first slave sequence according to the data clock so as to output a second slave sequence, and the second slave sequence circuit gains the second slave sequence and outputs the second slave sequence as a second slave feedback sequence; and the first operation circuit is used for compensating the equalization sequence by the first secondary feedback sequence and the second secondary feedback sequence and outputting the first addition sequence.

According to some embodiments, the main sequence circuit includes a main trigger sampling circuit and a main gain circuit. The main trigger sampling circuit is used for sampling the second summation sequence according to the data clock so as to output the main sequence. The main gain circuit is used for gain the main sequence with a main multiplying power and outputting the main sequence as the main feedback sequence.

In some embodiments, the first slave sequence circuit includes a first slave trigger sampling circuit and a first slave gain circuit. The first slave trigger sampling circuit samples the master sequence according to a data clock so as to output the first slave sequence. The first slave gain circuit is used for gain the first slave sequence with a first multiplying power and outputting the first slave sequence as the first slave feedback sequence. The first multiplying power is a constant between-1 and 0.

In some embodiments, the second slave sequence circuit includes a second slave trigger sampling circuit and a second slave gain circuit. The second slave trigger sampling circuit samples the first slave sequence according to a data clock so as to output the second slave sequence. The first slave gain circuit is used for gain the second slave sequence with a second multiplying power and outputting the second slave sequence as the second slave feedback sequence. The second magnification is a constant between-1 and 0.

In some embodiments, the phase of the data clock is substantially 180 degrees out of phase with the phase of the marginal clock.

In some embodiments, the data sampling circuit includes a third slave sequence circuit for sampling the second slave sequence according to the data clock and outputting a sampling result, the third slave sequence circuit gains the sampling result and outputs a third slave feedback sequence, and the first operation circuit compensates the equalization sequence with the first slave feedback sequence, the second slave feedback sequence, and the third slave feedback sequence to output the first addition sequence.

In some embodiments, the rate of the equalization sequence is substantially twice the rate of the data clock, the rate of the equalization sequence is substantially twice the rate of the marginal clock, the main feedback sequence comprises a first sub-main feedback sequence and a second sub-main feedback sequence, and the second summation sequence comprises a first sub-summation sequence and a second sub-summation sequence.

The second operation circuit comprises a first sub operation circuit and a second sub operation circuit, wherein the first sub operation circuit is used for compensating the first summation sequence by the first sub main feedback sequence and outputting the first sub summation sequence, and the second sub operation circuit is used for compensating the first summation sequence by the second sub main feedback sequence and outputting the second sub summation sequence.

The main sequence direction circuit comprises a first sub-main sequence direction circuit and a second sub-main sequence direction circuit. The first sub-main sequence direction circuit is used for sampling the first sub-summation sequence according to the data clock to output a first sub-main sequence, and the first sub-main sequence direction circuit gains the first sub-main sequence to output the first sub-main feedback sequence. The second sub-main sequence direction circuit is used for sampling the second sub-summation sequence according to the inverted data clock (hereinafter referred to as the inverted data clock) to output a second sub-main sequence, and the second sub-main sequence direction circuit gains the second sub-main sequence to output the second sub-main feedback sequence.

The data sampling circuit comprises four slave sequence circuits, wherein the four slave sequence circuits are respectively a first sub-slave sequence circuit, a second sub-slave sequence circuit, a third sub-slave sequence circuit and a fourth sub-slave sequence circuit. The first sub-slave sequence direction circuit is used for sampling the first sub-master sequence according to the inverse data clock to output a first sub-slave sequence, and the first sub-slave sequence direction circuit gains the first sub-slave sequence to output a first sub-slave feedback sequence. The second sub-slave sequence-to-sequence circuit is used for sampling the second sub-master sequence according to the data clock to output a second sub-slave sequence, and the second sub-slave sequence-to-sequence circuit gains the second sub-slave sequence to output a second sub-slave feedback sequence. The third sub-slave sequence-to-sequence circuit is used for sampling the first sub-slave sequence according to the inverted inverse data clock to output a third sub-slave sequence, and the third sub-slave sequence-to-sequence circuit gains the third sub-slave sequence to output a third sub-slave feedback sequence. The fourth sub-slave sequence circuit is used for sampling the second sub-slave sequence according to the data clock to output a fourth sub-slave sequence, and the fourth sub-slave sequence circuit gains the fourth sub-slave sequence to output a fourth sub-slave feedback sequence. The first operation circuit is used for compensating the equalization sequence from the feedback sequence by the first, second, third and fourth sub-sequences and outputting the first summation sequence.

In summary, according to some embodiments, the decision feedback equalizer circuit removes marginal and marginal effects of the equalization sequence on the data, so as to reduce the error rate of the clock and data recovery circuit.

Drawings

Fig. 1 shows a circuit diagram of a decision feedback equalizer known to the inventors.

Fig. 2A-2B illustrate an analog run-time equalization sequence of the decision feedback equalizer of fig. 1, and an eye diagram (EYE DIAGRAM) of the summed signal.

Fig. 3 shows a circuit functional block diagram of a receiver of an embodiment of the present disclosure.

Fig. 4 illustrates a circuit functional block diagram of some embodiments of the decision feedback equalization circuit of fig. 3.

Fig. 5A-5C show eye diagrams of the equalization sequence, the first summation sequence, and the second summation sequence, respectively, when the decision feedback equalization circuit of fig. 4 is operated in analog.

Fig. 6 illustrates a circuit functional block diagram of some embodiments of the decision feedback equalization circuit of fig. 3.

Fig. 7 illustrates a circuit functional block diagram of some embodiments of the decision feedback equalization circuit of fig. 3.

Fig. 8 shows a timing diagram of the decision feedback equalization circuit of fig. 7.

Symbol description

10. Receiver with a receiver body

100. Linear equalizer

200. 200', 400 Decision feedback equalization circuit

210. First arithmetic circuit

230. Second arithmetic circuit

232. Relay operation circuit

250. 250' Data sampling circuit

251. Main sequence direction circuit

252. 255, 258 Trigger sampling circuit

253. 256, 259 Gain circuit

254. First slave sequence circuit

257. 260 Second, third order circuit

270. 270' Marginal sampling circuit

272. 274, 276, 278 Trigger sampling circuit

300. Clock and data recovery circuit

410. First arithmetic circuit

411. 412 First and second sub-operation circuits

415. 416 First and second relay operation circuit

421. First sub-main sequential circuit

431. Second sub-main sequential circuit

422. First sub-sequential circuit

432. Second sub-sequential circuit

423. Third sub-sequential circuit

433. Fourth sub sequential circuit

450. Data sampling circuit

470. Marginal sampling circuit

461. 462, 463, 471, 472, 473 Trigger sampling circuit

90. Input terminal

92. Data sampling circuit

920. Adder device

921. 922, 923D type trigger

924. 925 And 926 amplifier

94. Marginal sampling circuit

Clk1 data clock

Clk2 marginal clock

Ck1 data clock

Ck2 data clock/inverse data clock

Cq1 marginal clock

Cq2 marginal clock/anti-marginal clock

Ds1, ds2, ds3 data sequences

Fs1, fs2, fs3 feedback sequences

Ln1, ln2 time points

S1 first sub-Slave sequence

S2 second sub-Slave sequence

S3 third sub-Slave sequence

S4 fourth sub-Slave sequence

Sa1 first sub-addition sequence

Sa2 second sub-addition sequence

Sad1 first addition sequence

Sad2 second addition sequence

Sadd sum signal

Sp main sequence

Sampling results of Se1 and Se2

Sp1 first sub-Main sequence

Sp2 second sub-Main sequence

Sd1 first Slave sequence

Sd2 second Slave sequence

Sf1 first sub-slave feedback sequence

Sf2 second sub-slave feedback sequence

Sf3 third sub-slave feedback sequence

Sf4 fourth sub-slave feedback sequence

Sfs1 first slave feedback sequence

Sfs2 second slave feedback sequence

Sfs3 third slave feedback sequence

Pfs main feedback sequence

Pfs1 first sub-main feedback sequence

Pfs2 second sub-main feedback sequence

Detailed Description

Referring to fig. 3, fig. 3 shows a block diagram of a receiver 10 according to an embodiment of the present disclosure. The receiver 10 includes a Linear Equalizer (LEQ) 100, a decision feedback Equalizer circuit (Decision Feedback Equalizer, DFE) 200, and a clock and data recovery circuit (Clock and Data Recovery Circuit, CDR) 300. In a digital communication system, the receiver 10 receives a sequence in a wireless channel within a wide range of frequencies (e.g., frequencies above 10GHz, i.e., high frequencies). This sequence is subject to the Fu Ji effect (inter-symbol interference, inter-symbol interference, ISI) in the radio channel, resulting in the sequence received by the receiver 10 having been partially distorted (referred to as a "distorted sequence", distorted Sequence). The linear Equalizer 100 is, for example, but not limited to, a Continuous-Time Equalizer (CTLE). The linear equalizer 100 receives the distorted sequence (input arrow to the left of the linear equalizer 100) and amplifies the high frequency content (including noise) of the distorted sequence to generate and output an analog equalized sequence. Next, the decision feedback equalizer 200 receives the analog equalization sequence, converges the distorted amplitude in the analog equalization sequence to level 0 and level 1, and samples the converged analog equalization sequence into a less distorted digital equalization sequence (described in detail below). In some embodiments, the decision feedback equalizer 200 may update coefficients (described below) of the decision feedback equalizer 200 with an algorithm such as a minimum Square (LEAST MEAN Square, LMS) or Zero Forcing (Zero Forcing), thereby converging the amplitude of the distortion in the analog equalization sequence to level 0 and level 1. Subsequently, the clock and data recovery circuit 300 receives the signal output by the decision feedback equalizer 200 and provides a data clock Clk1 and a margin clock Clk2 (see fig. 4) to the decision feedback equalizer 200, wherein the data clock Clk1 and the margin clock Clk2 are used to lock the phase of the sampled digital equalizer sequence (described in detail later).

Referring now to fig. 4, and in conjunction with fig. 5A-5C, fig. 4 shows a circuit functional block diagram of some embodiments of the decision feedback equalizer circuit 200 of fig. 3, and fig. 5A shows an equalization sequence when the decision feedback equalizer circuit 200 of fig. 4 is operating in analog; FIG. 5B shows a first summed sequence Sad1 of the decision feedback equalizer circuit 200 of FIG. 4 when operating in analog; fig. 5C shows an eye diagram of the second summation sequence Sad2 when the decision feedback equalizer circuit 200 of fig. 4 is operated in analog. The equalization circuit of the embodiment of fig. 4 is a decision feedback equalization circuit 200. In some embodiments, the decision feedback equalizer 200 is a full rate decision feedback equalizer, the data timing, the marginal timing, the data clock Clk1, and the marginal clock Clk2 have substantially the same rate, and the phase of the data clock Clk1 and the phase of the marginal clock Clk2 are substantially 180 degrees different. The decision feedback equalizer 200 includes a first operation circuit 210, a second operation circuit 230, a data sampling circuit 250, and a margin sampling circuit 270.

The first operation circuit 210 is configured to compensate an equalization sequence (fig. 5A) from the linear equalizer 100 with a plurality of slave feedback sequences sfs, sfs to output a first summed sequence Sad1. The second operation circuit 230 is configured to compensate the first added sequence Sad1 with a main feedback sequence pfs to output a second added sequence Sad2. The data sampling circuit 250 includes a master sequence direction circuit 251 and a plurality of slave sequence direction circuits 254, 257. The main sequence direction circuit 251 is configured to sample the second summed sequence Sad2 according to a data clock Clk1 to output a main sequence Sp, and the main sequence direction circuit 251 gains the main sequence Sp to output the main feedback sequence pfs. The slave sequence circuits 254 and 257 are configured to sequentially sample the master sequence Sp according to the data clock Clk1 to output the slave sequences Sd1 and Sd2, and the slave sequence circuits 254 and 257 gain the corresponding slave sequences Sd1 and Sd2 to output the slave feedback sequences sfs and sfs. The marginal sampling circuit 270 is configured to sample the first summed sequence Sad1 according to a marginal clock Clk2 to output a marginal sequence.

In some embodiments, the slave feedback sequence includes a first slave feedback sequence sfs and a second slave feedback sequence sfs2, so that the first computing circuit 210 compensates the equalization sequence with the first slave feedback sequence sfs and the second slave feedback sequence sfs2 to output the first summed sequence Sad1. The first operation circuit 210 is, for example, but not limited to, an adder, or a multiplier. In some embodiments, the first operation circuit 210 is an adder for adding the equalization sequence, the first slave feedback sequence sfs and the second slave feedback sequence sfs2 to output a first added sequence Sad1. The first slave feedback sequence sfs and the second slave feedback sequence sfs2 are used to compensate for the equalization sequence.

Referring to fig. 5A and 5B, fig. 5B shows an eye diagram of the first sum sequence Sad1, and comparing fig. 5A and 5B, it can be seen that the amplitude of the first sum sequence Sad1 has four convergence points, respectively, and two convergence points converge to level 1 (i.e. the number "1", or "level" 1 "), and the two convergence points are located at the amplitudes of about 0.4 and 0.7 (at the time axis of the drawing about 3.6x10 ^-11), respectively. In addition, the amplitudes of the first summation sequence Sad1 have two convergence points converging to the level 0 (i.e., the number "0", or "0") at the amplitudes of-0.4 and-0.7 (about 3.6x10 ^-11 on the time axis of the drawing) in fig. 5B, respectively. The first eye height is formed between the convergence point of about-0.4 and about 0.4 (at about 3.6x10 ^-11 on the time axis of fig. 5B). In an embodiment where the signal is a differential signal (DIFFERENTIAL SIGNAL), the amplitude is at level 1 (digital "1") between 0 and 1, and the amplitude is at level 0 (digital "0") between 0 and-1. Further, it can be seen that the eye height of the equalization sequence (fig. 5A) is between about-0.25 and +0.25 (at the time axis of about 3.7x10 ^-11) by comparing the eye diagrams of the equalization sequence (fig. 5A) with the eye diagrams of the first summation sequence Sad1, i.e. the first eye height of the first summation sequence Sad1 is higher than the eye height of the equalization sequence, which means that the first calculation circuit 210 compensates the equalization sequence with the first feedback sequence sfs1 and the second feedback sequence sfs, and the obtained first summation sequence Sad1 can increase the eye height. The increase in eye height may reduce Bit error rate (Bit error rate), i.e., enable the subsequent clock and data recovery circuit 300 to recover clock and data more correctly.

Next, as can be seen by comparing fig. 5A and fig. 5B, the signal traces of the equalization sequence (fig. 5A) at the marginal edge (i.e., on the horizontal axis with the amplitude of zero, in the vicinity of the time axis of fig. 5A, about 2x10 ^-11 and about 5.2x10 ^-11) are dispersed (the offset of each signal at the time point with the amplitude of zero is large), and the center of the marginal edge of the first summation sequence Sad1 is similar to fig. 5A, about the time axis of about 2x10 ^-11 and about 5.2x10 ^-11, but the respective signals of the first summation sequence Sad1 are relatively reduced much at the time difference with the amplitude of zero, and it is apparent that the first summation sequence Sad1 has a convergence effect on the marginal edge. Therefore, the first sum sequence Sad1 is used as the input of the marginal sampling circuit 270, so as to effectively reduce the error rate of the marginal sampling circuit 270 for sampling the marginal.

With continued reference to fig. 4, the second operation circuit 230 is configured to compensate the first added sequence Sad1 with a main feedback sequence pfs to output a second added sequence Sad2. The second arithmetic circuit 230 is such as, but not limited to, an adder, or a multiplier. In some embodiments, the second operation circuit 230 is an adder for adding the first added sequence Sad1 and the main feedback sequence pfs, and outputting the second added sequence Sad2. Referring to the eye diagram of the second summed sequence Sad2 (see fig. 5C), the amplitude of the second summed sequence Sad2 has two convergence points, which converge to level 1 and level 0 (i.e., the positions where the amplitudes are about 0.5 and-0.5), respectively. That is, after the four convergence points of the first sum sequence Sad1 are compensated by the main feedback sequence pfs, the two convergence points are respectively converged to two convergence points, and the two convergence points are respectively converged to a second eye height, as can be seen from fig. 5B and fig. 5C, the second eye height (-between 0.5 and 0.5) is higher than the first eye height (-between 0.25 and 0.25) of the first sum sequence Sad1, so that it can be known that the second arithmetic circuit 230 compensates the first sum sequence Sad1 by the main feedback sequence pfs to obtain the second sum sequence Sad2, and the levels 0 and 1 of the second sum sequence Sad2 (the amplitudes of the digital signals 0 and 1 are respectively converged to the positions of about-0.5 and about 0.5), so as to have the equalizing effect, the effect of the first sum sequence Sad1 is removed to a considerable extent, and thus the sampling error rate of the data sampling circuit 250 receiving the second sum sequence Sad2 is effectively reduced. As can be seen from comparing fig. 5B and fig. 5C, the second summation sequence Sad2 of fig. 5C is significantly advanced in the center of the zero position (about 1.1x10 ^-11) compared to the zero position center of fig. 5A (about 2x10 ^-11), and the amplitude of each signal is significantly different in time at the zero position compared to the first summation sequence Sad1 of fig. 5B.

Referring back to fig. 4, in some embodiments, the data sampling circuit 250 includes a master sequential circuit 251, a first slave sequential circuit 254, and a second slave sequential circuit 257. The main sequence direction circuit 251 is configured to receive the second summed sequence Sad2 according to the data clock Clk1 and output a main sequence Sp accordingly, and the main sequence direction circuit 251 gains the main sequence Sp to output as the main feedback sequence pfs. The first slave sequence circuit 254 is configured to receive the master sequence Sp according to the data clock Clk1 and output a first slave sequence Sd1 according to the data clock Clk1, and the first slave sequence circuit 254 gains the first slave sequence Sd1 to output as the first slave feedback sequence sfs1. The second slave sequence-to-sequence circuit 257 is configured to receive the first slave sequence Sd1 according to the data clock Clk1 to output the second slave sequence Sd2 (the second slave sequence Sd2 is the data sequence of fig. 4), and the second slave sequence-to-sequence circuit 257 gains the second slave sequence Sd2 and outputs the second slave sequence Sd2 as the second slave feedback sequence sfs. Accordingly, the plurality of slave sequence circuits 254 and 257 "sequentially" sample the master sequence Sp according to the data clock Clk1 to output a plurality of slave sequences, which means that the first slave sequence circuit 254 samples the master sequence Sp to output the first slave sequence Sd1 and the second slave sequence circuit 257 samples the first slave sequence Sd1 to output the second slave sequence Sd2.

In some embodiments, the main sequence direction circuit 251 includes a trigger sampling circuit 252 (main trigger sampling circuit) and a gain circuit 253 (main gain circuit). The trigger sampling circuit 252 is a device that samples input data according to the triggering of a clock and outputs the sampling result until the next triggering. The trigger of the clock may be an upper edge trigger of the clock or a lower edge trigger of the clock. The sampling circuit 252 is triggered to sample the input data, so as to determine whether the level of the sampled data at the trigger point belongs to the level "0" or "1", and output the determined level "0" or "1" as the sampling result. In fig. 4, the trigger sampling circuit 252 samples the second sum sequence Sad2 according to the trigger of the data clock Clk1 (for example, but not limited to, the trigger at the rising edge of the data clock Clk 1), and outputs the sampling result as the main sequence Sp. In some embodiments, the trigger sampling circuit 252 is a Flip-Flop (Flip-Flop), such as, but not limited to, a D-type Flip-Flop having a sequence input, a clock input, and a sequence output. The D-type flip-flop receives the data clock Clk1 through the time sequence input end and judges the level of the second summation sequence Sad2 received by the sequence input end according to the triggering of the data clock Clk1, and outputs the data clock Clk1 from the sequence output end according to the level of the second summation sequence Sad2 at the triggering time point, and then the D-type flip-flop maintains the output level until the data clock Clk1 is triggered next time. Thus, the D-flip flop has the functions of storage and delay. The gain circuit 253, such as but not limited to an amplifying circuit, an inverting circuit, or an amplifying and inverting circuit, is configured to gain an input signal and output the gain signal. In some embodiments, the gain circuit 253 gains the input main sequence Sp by a main multiplying factor, and then outputs the main feedback sequence pfs. The gain is obtained by multiplying the voltage (or current) of the main sequence Sp by the main multiplying power, and the gain may have a buffering effect, and the main multiplying power may be a constant between-1 and-1, such as-0.5, -0.3, -0.1, 0.2, 0.4, etc., and is adjusted according to the characteristics of the first summation sequence Sad1, which will be described later.

In some embodiments, the first slave sequence circuit 254 includes a trigger sampling circuit 255 (first slave trigger sampling circuit) and a gain circuit 256 (first slave gain circuit). The trigger sampling circuit 255 samples the master sequence Sp according to the trigger of the data clock Clk1, and outputs the sampling result as the first slave sequence Sd1. In some embodiments, the trigger sampling circuit 256 is a D-type flip-flop. The gain circuit 256 gains the input master sequence Sp by a first multiplying factor and outputs the first slave feedback sequence sfs1. The first multiplying power may be a constant between-1 and-1, such as-0.5, -0.3, -0.1, 0.2, 0.4, etc., adjusted according to the characteristics of the equalization sequence and the main sequence Sp, as described below.

The second slave sequence circuit 257 includes a trigger sampling circuit 258 (second slave trigger sampling circuit) and a gain circuit 259 (second slave gain circuit). The trigger sampling circuit 258 samples the first slave sequence Sd1 according to the trigger of the data clock Clk1, and outputs the sampling result as the second slave sequence Sd2. In some embodiments, the trigger sampling circuit 258 is a D-type trigger. The gain circuit 259 gains the input first slave sequence Sd1 by a second multiplying factor, and outputs the second slave feedback sequence sfs2. The second rate may be a constant between-1 and-1, such as-0.5, -0.3, -0.1, 0.2, 0.4, etc., adjusted according to the characteristics of the equalization sequence, the master sequence Sp and the first slave sequence Sd1, as described later.

The marginal sampling circuit 270 is configured to sample the first summed sequence Sad1 according to a marginal clock Clk2 to output the marginal sequence. In some embodiments, the phase of the marginal clock Clk2 is about 180 degrees out of phase with the data clock Clk 1. The marginal sampling circuit 270 includes a plurality of trigger sampling circuits 272, 274, 276 (which may also be referred to as marginal trigger sampling circuits, for distinction from the trigger sampling circuits of the data sampling circuit 250) connected in series, and the plurality of trigger sampling circuits 272, 274, 276 connected in series sequentially sample the first sum sequence Sad1 according to the marginal clock Clk2 to output the marginal sequence. The "sequential sampling" refers to each of the trigger sampling circuits 272, 274, 276 sampling the output of the device in the previous stage and outputting the sampling result. In some embodiments, the trigger sampling circuits 272, 274, 276 are D-type flip-flops. When each flip-flop is triggered by the marginal clock Clk2 (which may be either an upper edge trigger or a lower edge trigger), a signal input to the flip-flop is sampled and the level of the sampled signal is taken as its output. For example, when the edge clock Clk2 triggers, the trigger sampling circuit 272 determines the level of the first sum sequence Sad1 and outputs the determined level as its output signal (also referred to as the sampling result). The trigger sampling circuit 272 maintains the output signal until the next trigger of the marginal clock Clk 2. Similarly, when the clock Clk2 triggers, the trigger sampling circuit 274 determines the level of the output signal of the trigger sampling circuit 272, and as the output signal of the trigger sampling circuit 274, the trigger sampling circuit 274 maintains the output signal until the clock Clk2 triggers next time. When the marginal clock Clk2 triggers, the trigger sampling circuit 276 determines the level of the output signal of the trigger sampling circuit 274, and as the output signal of the trigger sampling circuit 276, the trigger sampling circuit 276 maintains the output signal until the next trigger of the marginal clock Clk 2. The trigger sampling circuit 276 is the last stage of the trigger sampling circuit 276 in series, so the output (sampling result) of the trigger sampling circuit 276 is the marginal sequence. The number of marginal trigger sampling circuits 272, 274, 276 is equal to the number of sequential circuits 251, 254, 257.

In some embodiments, the equalizer 200 has a relay operation circuit (dummy arithmetic circuit, virtual operation circuit, such as the element numbered 232 in fig. 6) between the marginal sampling circuit 270 and the first operation circuit 210, the delay time of the relay operation circuit is substantially the same as the delay time of the second operation circuit 230, and the relay operation circuit receives the first summation sequence Sad1 and directly outputs the first summation sequence Sad1. With the configuration of the relay circuit, the time from the first sum sequence Sad1 passing through the data sampling circuit 250 to the data sequence output is substantially equal to the time from the first sum sequence Sad1 passing through the marginal sampling circuit 270 to the marginal sequence output.

The first computing circuit 210 and the second computing circuit 230 compensate the feedback sequences pfs, sfs1, sfs of the equalization sequence and the first summation sequence Sad1, respectively, as described below. In digital signal communications, the transmitted data are data with levels 0 and 1, for example, 10 bits (bit) are transmitted, the transmitted content is 0101101010 (hereinafter referred to as "prefix row") or 1000000010 (hereinafter referred to as "post sequence"), the last 1 of the prefix row is only 1 "0" in front of the last 1 of the post sequence, 7 "0" in front of the last 1 of the post sequence, assuming that the front and the post sequences are transmitted by the same transmitting end, based on the characteristics of the transmitting element and the transmission channel of the transmitting end, the rising time (RISING TIME) and the falling time (FALLING TIME) of the last 1 of the post sequence are longer than the rising time and the falling time of the last 1 of the prefix row, the amplitude of the last 1 of the post sequence is smaller than the amplitude of the last 1 of the prefix row, the content of the first bit in front of the last 1 is affected most by the rising time, the falling time and the amplitude, the content of the second bit in front of the last 1 is affected most, and so on. Taking the prefix row and the post sequence as an example, if the current bit is the 9 th bit, the first bit before the current bit is the 8 th bit, the second bit before the current bit is the 7 th bit, and so on, the 8 th bit, the 7 th bit, and so on, which have the greatest influence on the current bit (the 9 th bit). Thus, in some embodiments, when selecting to compensate the feedback signal of the current bit (bit 9), the weight (gain value) of bit 8 is higher than bit 7, and the weight of bit 7 compensation is higher than bit 6.

Referring to fig. 4 again, with the foregoing 10-bit sequence as an example, the data sampling circuit 250 samples the prefix row according to the triggering of the data clock Clk1, and the prefix row is 9 th bit (hereinafter referred to as the current bit) before the main sequential circuit 251, the output of the main sequential circuit 251 is 8 th bit, the output of the first sequential circuit 254 is 7 th bit, and the output of the second sequential circuit 257 is 6 th bit, so that the respective multiplying powers are different, i.e. the main multiplying power, the first multiplying power and the second multiplying power are different, because the influence of the 8 th, 7 th and 6 th bits on the current bit characteristics is different. In addition, in applications with the intersymbol effect, the 8, 7, 6 bit levels have an inverse effect on the current bit level, and therefore, in some embodiments, the first, second, and third magnifications are negative. The determination of the multiplying power can be obtained by converging additional circuits or algorithms, such as the minimum root mean square value algorithm described above, to obtain the first multiplying power, the second multiplying power, and the third multiplying power, wherein the multiplying power is a constant of-1 to 0.

Furthermore, as shown in comparison between the first sum sequence Sad1 of fig. 5B and the second sum sequence Sad2 of fig. 5C, the equalization effect of the amplitude of the second sum sequence Sad2 obtained after the main feedback sequence pfs compensates for the first sum sequence Sad1 is good, such that the data sampling error rate of the second sum sequence Sad2 is reduced (the sampling time point is about 3.5x10 ^-11), but the marginal sampling error rate of the output second sum signal Sad2 is still high (the sampling time is about the middle section between 0 and 3.5x10 ^-11). After the equalization sequences of the first and second slave feedback sequences sfs, sfs2 are compensated, the error rate of the marginal sampling can be effectively reduced, so that the first addition sequence Sad1 is used as the input of the marginal sampling circuit 270. As can be seen from the above description, in the embodiment of fig. 4, the error rate of sampling the data sequence and the margin sequence can be effectively reduced after the clock and data recovery circuit 300 receives the data sequence and the margin sequence. As can be seen from fig. 5A, 5B, and 5C, the feedback of the main feedback sequence pfs advances the margin (where the amplitude is zero) of the input sequence, which is undesirable on marginal sampling, but for data sampling, a better equalized and effectively low bit error rate for data sampling is obtained, so the second sum sequence Sad2 is used as the input of the data sampling circuit 250.

Referring to fig. 6, fig. 6 shows a circuit functional block diagram of an embodiment of the decision feedback equalizer circuit 200 of fig. 3. The equalizer circuit 200' includes a first operation circuit 210, a second operation circuit 230, a relay operation circuit 232, a data sampling circuit 250', and a boundary sampling circuit 270'. The data sampling circuit 250' includes a master sequence circuit 251, a first slave sequence circuit 254, a second slave sequence circuit 257, and a third slave sequence circuit 260. The third slave sequence direction circuit 260 receives the second slave sequence Sd2, and samples the second slave sequence Sd2 according to the data clock Clk1 to output the data sequence. The marginal sampling circuit 270' includes a plurality of trigger sampling circuits 272, 274, 276, 278 in series. The number of trigger sampling circuits 272, 274, 276, 278 of the marginal sampling circuit 270 'is the same as the number of master and slave sequential circuits 251, 254, 257, 260 of the data sampling circuit 250'.

In some embodiments, the data sampling circuit 250 includes a plurality of third slave sequential circuits 260, the third slave sequential circuits 260 are sequentially arranged in series between the second slave sequential circuits 257 and the data sequence, that is, the third slave sequential circuits 260 in series receive the second slave sequence Sd2, and sequentially sample the second slave sequence Sd2 according to the data clock Clk1 to output the data sequence. Each of the third slave sequencing circuits 260 samples (i.e. stores and delays) the sequence input from the previous stage according to the data clock Clk1 and outputs a sampling result accordingly. Each third slave sequence direction circuit 260 gains the corresponding sampling result and outputs a plurality of third slave feedback sequences sfs3 correspondingly, the first operation circuit 210 compensates the equalization sequences with the third slave feedback sequence sfs3 and the first and second slave feedback sequences sfs1 and sfs to output the first summation sequence Sad1, and the first summation sequence Sad1 is used as the input of the marginal sampling circuit 270 to reduce the error rate of marginal sampling. In this embodiment, the sampling result output from the last stage of the third slave serial circuit 260 is the data sequence.

The decision feedback equalizer 200 of the embodiments of fig. 4 and 6 is a Full Rate (Full Rate) decision feedback equalizer, i.e., the data clock Clk1 and the marginal clock Clk2 have substantially the same Rate as the data sequence, and in some embodiments, the decision feedback equalizer 200 may also employ Half Rate (Half Rate) decision feedback equalizer.

Referring to fig. 7, fig. 7 illustrates a circuit functional block diagram of some embodiments of the decision feedback equalization circuit of fig. 3. In this embodiment, the decision feedback equalizer 400 is a half-rate decision equalizer, i.e., the rate of the data clocks Ck1, ck2 that trigger the data sampling circuit 450 and the marginal clocks Cq1, cq2 that trigger the marginal sampling circuit 470 is half the rate of the equalization sequence. In some embodiments, the data clocks Ck1, ck2 and the marginal clocks Cq1, cq2 are output by the clock and data recovery circuit 300. The decision feedback equalizer 400 includes a first operation circuit 410, a second operation circuit, a data sampling circuit 450, and a boundary sampling circuit 470.

The first operation circuit 410 is configured to compensate the equalization sequences with a plurality of slave feedback sequences sf1, sf2, sf3, sf4 to output a first summed sequence Sad1. The second operation circuit is configured to compensate the first sum sequence Sad1 with a main feedback sequence to output a second sum sequence Sad2 (i.e. Sa1 and Sa2 in fig. 7). The data sampling circuit 450 includes a master sequence circuit and a plurality of slave sequence circuits. The main sequence direction circuit is used for sampling the second summation sequence Sad2 according to a data clock Ck1 to output a main sequence, and the main sequence direction circuit gains the main sequence to output the main feedback sequence. The slave sequence circuit is used for sampling the master sequence according to the data clock Clk1 in sequence to output a plurality of slave sequences, and the slave sequence corresponding to the slave sequence circuit gains to output the slave feedback sequences sf1, sf2, sf3 and sf4. The marginal sampling circuit 470 is configured to sequentially sample the first summed sequence Sad1 according to a marginal clock Cq2 to output a marginal sequence.

In some embodiments, the rate of the equalization sequence is substantially twice the rate of the data clock, the rate of the equalization sequence is substantially twice the rate of the marginal clock, the main feedback sequence includes a first sub-main feedback sequence pfs1 and a second sub-main feedback sequence pfs2, and the second summation sequence Sad2 includes a first sub-summation sequence Sa1 and a second sub-summation sequence Sa2.

The second operation circuit includes a first sub-operation circuit 411 and a second sub-operation circuit 412, wherein the first sub-operation circuit 411 is configured to compensate the first summation sequence Sad1 with the first sub-main feedback sequence pfs1 and output the first sub-summation sequence Sa1, and the second sub-operation circuit 412 is configured to compensate the first summation sequence Sad1 with the second sub-main feedback sequence pfs2 and output the second sub-summation sequence Sa2.

The main sequence direction circuit includes a first sub-main sequence direction circuit 421 and a second sub-main sequence direction circuit 431. The first sub-main sequence direction circuit 421 is configured to sample the first sub-sum sequence Sa1 according to the data clock Ck1 to output a first sub-main sequence Sp1, and the first sub-main sequence direction circuit 421 gains the first sub-main sequence Sp1 to output the first sub-main feedback sequence pfs1. The second sub-main sequence direction circuit 431 is configured to sample the second sub-sum sequence Sa2 according to the inverted data clock Ck1 (hereinafter referred to as inverted data clock Ck 2) to output a second sub-main sequence Sp2, and the second sub-main sequence direction 431 circuit gains the second sub-main sequence Sp2 to output the second sub-main feedback sequence pfs2.

The data sampling circuit includes four slave sequence circuits, which are a first sub-slave sequence circuit 422, a second sub-slave sequence circuit 432, a third sub-slave sequence circuit 423, and a fourth sub-slave sequence circuit 433, respectively.

The first sub-slave sequence direction circuit 422 is configured to sample the first sub-master sequence Sp1 according to the inverse data clock Ck2 to output a first sub-slave sequence S1, and the first sub-slave sequence direction circuit 422 gains the first sub-slave sequence S1 to output the first sub-slave feedback sequence sf1.

The second sub-slave sequence direction circuit 432 is configured to sample the second sub-master sequence Sp2 according to the data clock Ck1 to output a second sub-slave sequence S2, and the second sub-slave sequence direction circuit 432 gains the second sub-slave sequence S2 to output the second sub-slave feedback sequence sf2.

The third sub-slave sequence circuit 423 is configured to sample the first sub-slave sequence S1 according to the inverted inverse data clock Ck2 to output a third sub-slave sequence S3, and the third sub-slave sequence circuit 423 is configured to gain the third sub-slave sequence S3 to output the third sub-slave feedback sequence sf3.

The fourth sub-slave sequence 433 is configured to sample the second sub-slave sequence S2 according to the data clock Ck1 to output a fourth sub-slave sequence S4, and the fourth sub-slave sequence 433 gains the fourth sub-slave sequence S4 to output the fourth sub-slave feedback sequence sf4.

The first operation circuit is used for compensating the equalization sequences from the feedback sequences Sf1, sf2, sf3 and Sf4 by the first, second, third and fourth sub-sequences and outputting the first summation sequence Sad1.

In some embodiments, the detailed structure of the aforementioned sequential circuits 421, 422, 423, 431, 432, 433 can be seen in fig. 4, and each of the sequential circuits 421, 422, 423, 431, 432, 433 includes a trigger sampling circuit and a gain circuit, which are described below.

The first sub-main sequential circuit 421 includes a first sub-main trigger sampling circuit and a first sub-main gain circuit. The first sub-main trigger sampling circuit is configured to sample the first sub-sum sequence Sa1 according to the data clock Ck1 to output the first sub-main sequence Sp1. The first sub-main gain circuit is configured to gain the first sub-main sequence Sp1 with a first sub-main multiplying power and output the first sub-main feedback sequence pfs1.

The second sub-main sequential circuit 431 includes a second sub-main trigger sampling circuit and a second sub-main gain circuit. The second sub-main trigger sampling circuit is configured to sample the second sub-sum sequence Sa2 according to the inverse data clock Ck2 to output the second sub-main sequence Sp2. The second sub-main gain circuit is configured to gain the second sub-main sequence Sp2 with a second sub-main multiplying power and output as the second sub-main feedback sequence pfs2. The first sub-main multiplying power and the second sub-main multiplying power are constants between-1 and 0 respectively.

The first sub-slave sequence circuit 422 includes a first sub-slave trigger sampling circuit and a first sub-slave gain circuit. The first sub-slave trigger sampling circuit is configured to sample the first sub-master sequence Sp1 according to the inverse data clock Ck2 to output the first sub-slave sequence S1. The first sub-slave gain circuit is used for gain the first sub-slave sequence S1 with a first sub-slave multiplying power and outputting the first sub-slave sequence S1 as the first sub-slave feedback sequence sf1. The second sub-slave sequence circuit 432 includes a second sub-slave trigger sampling circuit and a second sub-slave gain circuit. The second sub-slave trigger sampling circuit is configured to sample the second sub-master sequence Sp2 according to the data clock Ck1 to output the second sub-slave sequence S2. The second sub-slave gain circuit is used for gain the second sub-slave sequence S2 with a second sub-slave multiplying power and outputting the second sub-slave sequence S2 as the second sub-slave feedback sequence sf2.

The third sub-slave sequence circuit 423 includes a third sub-slave trigger sampling circuit and a third sub-slave gain circuit. The third sub-slave trigger sampling circuit is configured to sample the first sub-slave sequence S1 according to the inverse data clock Ck2 to output the third sub-slave sequence S3. The third sub-slave gain circuit is configured to gain the third sub-slave sequence S3 with a third sub-slave multiplying power and output the third sub-slave sequence sf3 as the third sub-slave feedback sequence. The fourth sub-slave sequence circuit 433 includes a fourth sub-slave trigger sampling circuit and a fourth sub-slave gain circuit. The fourth sub-slave trigger sampling circuit is configured to sample the second sub-master sequence Sp2 according to the data clock Ck1 to output the fourth sub-slave sequence S4. The fourth sub-slave gain circuit is configured to gain the fourth sub-slave sequence S4 at a fourth sub-slave multiplying power and output the fourth sub-slave sequence sf4 as the fourth sub-slave feedback sequence. The first, second and third fourth seed from multiplying power respectively is a constant between-1 and 0.

The third sub-slave sequence S3 and the fourth sub-slave sequence S4 are data sequences outputted from the data sampling circuit 450 to the clock and data recovery circuit 300. The clock and data recovery circuit 300 may integrate and recover the third sub-slave sequence S3 and the fourth sub-slave sequence S4, or may down-convert, process, and then integrate and recover.

In some embodiments, the first sub-slave ratio is different from the first sub-slave ratio at a low level of the inverse data clock Ck 2. The second sub-slave multiplying power is different from the multiplying power value of the second sub-slave multiplying power at the data clock Ck1 at a low level when the multiplying power of the data clock Ck1 at a high level. The third sub-slave multiplying power is equal to the multiplying power value of the inverse data clock Ck2 at the high level different from the third sub-slave multiplying power at the multiplying power value of the inverse data clock Ck2 at the low level. The fourth sub-slave multiplying power is different from the multiplying power of the fourth sub-slave multiplying power at the low level of the data clock Ck1 when the data clock Ck1 is at the high level. That is, the sub-magnifications have two configurations of magnifications, respectively, which will be described later.

In some embodiments, each of the trigger sampling circuits is a D-type flip-flop, the phase of the data clock Ck1 is substantially 90 degrees different from the phase of the marginal clock Cq1, and each of the operation circuits is an adder.

Regarding the operation of the equalization circuit 400 of fig. 7, please read with fig. 8, fig. 8 shows a timing diagram of the decision feedback equalization circuit of fig. 7. The equalization sequence of fig. 8 is illustrated as 1 1010 1101, where labeled 1 (1) represents a first bit that is sent to the first arithmetic circuit 410, where the inner is a number "1", labeled 2 (0) represents a second bit that is sent to the first arithmetic circuit 410, where the inner is a number "0", and labeled 3 (1) represents a third bit that is sent to the first arithmetic circuit 410, where the inner is a number "1". That is, the horizontal line of fig. 8 is the time axis, the rightmost bit 1 (1) of the horizontal axis is the bit that is first transmitted to the data sampling circuit 450 and the marginal sampling circuit 470, and the leftmost bit 9 (1) of the horizontal axis is the bit that is last transmitted to the data sampling circuit 450 and the marginal sampling circuit 470. Based on the characteristics of the horizontal axis of fig. 8, the rising edge of the data clock Ck1 is located in the middle of bits 1, 3, 5, 7, and 9, and the rising edge of the inverted data clock Ck2 is located in the middle of bits 2,4, 6, and 8. The first sub-master sequential circuit 421, the second sub-slave sequential circuit 432, and the fourth sub-slave sequential circuit 433 are triggered by the rising edge of the data clock Ck 1. The second sub-master sequential circuit 431, the first sub-slave sequential circuit 422, and the third sub-slave sequential circuit 423 are triggered by the rising edge of the inverse data clock Ck 2.

As can be seen from the timing diagram, at the first trigger point T1 (Ck 1), the first sub-main sequence samples the circuit 421 to obtain and maintain 1 (1). At a second trigger time T2 (Ck 2), the first sub-sampling and holding 1 (1) from the sequential circuit 422 and the second sub-main sequential circuit 431 obtaining and holding 2 (0). At a third trigger time T3 (Ck 1), the first sub-master sequence circuit 421 samples and holds 3 (1), and the second sub-slave sequence circuit 432 samples and holds 2 (0). At a fourth trigger time T4 (Ck 2), the first sub-sampling and holding 3 (1) from the sequential circuit 422, the third sub-sampling and holding 1 (1) from the sequential circuit 423, and the second sub-main sequential circuit 431 sampling and holding 4 (1). Therefore, before the fifth trigger time T5 (i.e., the instant Ln 1), the first sub-master sequential circuit 421 maintains 3 (1), the second sub-master sequential circuit 431 maintains 4 (1), the first sub-slave sequential circuit 422 maintains 3 (1), the second sub-slave sequential circuit 432 maintains 2 (0), and the third sub-slave sequential circuit 423 maintains 1 (1), while the fourth sub-slave sequential circuit 433 has not sampled the data of the equalization sequence.

At a fifth trigger time T5 (Ck 1), the first sub-master sampling circuit 421 samples and maintains 5 (0), the second sub-slave sampling circuit 432 samples and maintains 4 (1), and the fourth sub-slave sampling circuit 433 samples and maintains 2 (0).

Before the sixth trigger time T6 (i.e., the instant Ln 2), the first sub-master sequential circuit 421 maintains 5 (0), the second sub-master sequential circuit 431 maintains 4 (1), the first sub-slave sequential circuit 422 maintains 3 (1), the second sub-slave sequential circuit 432 maintains 4 (1), the third sub-slave sequential circuit 423 maintains 1 (1), and the fourth sub-slave sequential circuit 433 maintains 2 (0). Therefore, at the sixth trigger time T6 (Ck 2), the first arithmetic circuit 410 compensates the equivalent sequences with the first sub-slave feedback sequence sf1 (3 (1)), the second sub-slave feedback sequence sf2 (4 (1)), the third sub-slave feedback sequence sf3 (1 (1)), and the fourth sub-slave feedback sequence sf4 (2 (0)), so as to obtain the first sum sequence Sad1; that is, the first operation circuit 410 compensates the 6 th bit (from the feedback sequence) sequentially through the 1 st, 2 nd, 3 rd and 4 th bits of the data sampling circuit 450 to obtain the first sum sequence Sad1. The second sub-operation circuit 412 compensates the first added sequence Sad1 with the first sub-main feedback sequence pfs1 to obtain the second sub-added sequence Sa2, that is, the second sub-operation circuit 412 compensates the 6 th bit (the first added sequence Sad 1) with the 5 th bit just passed through the data fetch circuit 450 to obtain the second sub-added sequence Sa2. Therefore, the compensation scheme of the embodiment of fig. 7 is similar to that of the embodiment of fig. 4, and the Fu Ji effect of the equalization sequence can be properly removed, so that the error rates of the data samples and the marginal samples are reduced.

Further, as can be seen from the description, at the sixth trigger point T6, the 6 th bit (6 (1), hereinafter referred to as the current bit) is to be sampled, and the second sub-slave feedback sequence sf2 outputted from the second sub-slave sequence circuit 432 is the 4 th bit (4 (1)), and the second sub-slave feedback sequence sf2 is the second past bit with respect to the current bit. At the seventh trigger point T7, however, the 7 th bit (7 (0), hereinafter referred to as the current bit) to be sampled is the 7 th bit, which is sampled by the first sub-main sequential circuit 421, the second sub-slave feedback sequence sf2 outputted from the second sub-slave sequence circuit 432 is still the 4 th bit (4 (1)), i.e. the second sub-slave feedback sequence sf2 is the third bit that has passed with respect to the current bit. As can be seen from the description of the embodiment of fig. 4, in some embodiments, the gain value of each slave feedback sequence (e.g., sf1, sf 2) is different from that of the slave sequence (e.g., S1, S2), the gain value is related to the number of bits from the current bit (hereinafter referred to as the number of bits apart), and in some embodiments, the more the number of bits apart, the greater the effect of the feedback sequence on the current bit. Therefore, since the number of bits apart from the current bit in the same sub-slave feedback sequences sf1, sf2, sf3, sf4 varies (varies based on the data clock Ck1 or the inverse data clock Ck 2), the sub-slave ratio of each of the sub-slave sequence circuits 422, 232, 423, 433 varies based on the data clock Ck1 or the inverse data clock Ck 2. For example, the first sub-slave multiplying power is different from the first sub-slave multiplying power at the high level of the inverse data clock Ck2 from the first sub-slave multiplying power at the low level of the inverse data clock Ck 2.

With continued reference to fig. 7, the marginal sampling circuit 470 is configured to sample the first summed sequence Sad1 according to a marginal clock Cq1 to output the marginal sequence. In some embodiments, the phase of the marginal clock Cq1 is about 90 degrees out of phase with the phase of the data clock Ck 1. The marginal sampling circuit 470 includes a plurality of trigger sampling circuits 471, 472, 473, 461, 462, 463 (which may also be referred to as marginal trigger sampling circuits to distinguish from the trigger sampling circuits of the data sampling circuit 450), and the marginal trigger sampling circuits 471, 472, 473, 461, 462, 463 sequentially sample the first summation sequence Sad1 according to the marginal clock Cq1 to output the marginal sequence.

For convenience of description, the marginal trigger sampling circuits 471, 472, 473, 461, 462, 463 are respectively named as a first trigger sampling circuit 471, a second trigger sampling circuit 461, a third trigger sampling circuit 472, a fourth trigger sampling circuit 462, a fifth trigger sampling circuit 473, and a sixth trigger sampling circuit 463. The first trigger sampling circuit 471, the third trigger sampling circuit 472, and the fifth trigger sampling circuit 473 are triggered by the marginal clock Cq1, and the second trigger sampling circuit 461, the fourth trigger sampling circuit 462, and the sixth trigger sampling circuit 463 are triggered by the inverted marginal clock Cq1 (hereinafter referred to as an inverted marginal clock "as an inverted marginal clock Cq 2). Since the connection between the trigger sampling circuits 471, 472, 473, 461, 462, 463 of the marginal sampling circuit 470 is similar to the connection between the sequential circuits 421, 422, 423, 431, 432, 433 (or the trigger sampling circuits thereof) of the data sampling circuit 450, the operation thereof is also similar. The first trigger sampling circuit 471, the third trigger sampling circuit 472 and the fifth trigger sampling circuit 473 are serially connected in sequence, and the second trigger sampling circuit 461, the fourth trigger sampling circuit 462 and the sixth trigger sampling circuit 463 are serially connected in sequence. The last stage of the two serially connected trigger sampling circuits is a fifth trigger sampling circuit 473 and a sixth trigger sampling circuit 463, respectively. The fifth trigger sampling circuit 473 and the sixth trigger sampling circuit 463 output sampling results Se1 and Se2, respectively. The sampling results Se1 and Se2 are the marginal sequences outputted to the clock and data recovery circuit 300.

Referring to fig. 8, the upper edge of the marginal clock Cq1 is about the 1 st and 2 nd bit margins (hereinafter referred to as 1 st bit margin), the 3 rd and 4 th bit margins (hereinafter referred to as 3 rd bit margin), the 5 th and 6 th bit margins (hereinafter referred to as 5 th bit margin), and the 7 th and 8 th bit margins (hereinafter referred to as 7 th bit margin), so that the first trigger sampling circuit 471 sequentially samples the 1 st, 3 rd, 5 th and 7 th bit margins, and the third trigger sampling circuit 472 and the fifth trigger sampling circuit 473 sequentially samples the sampling result of the first trigger sampling circuit 471. Similarly, the second trigger sampling circuit 461 sequentially samples the 2 nd, 4 th, 6 th, and 8 th bit edges, and the fourth trigger sampling circuit 462 and the sixth trigger sampling circuit 463 sequentially sample the sampling result of the second trigger sampling circuit 461.

Referring to fig. 7 again, in some embodiments, the equalization circuit 400 includes first and second relay operation circuits 415 and 416, the first relay operation circuit 415 is located between the first operation circuit 410 and the first trigger sampling circuit 471 for transmitting the first summed sequence Sad1 to the first trigger sampling circuit 471. The second relay operation circuit 416 is located between the first operation circuit 410 and the second trigger sampling circuit 461, and is used for transmitting the first sum sequence Sad1 to the second trigger sampling circuit 461. By the first and second relay circuits 415, 416, the elements through which the equalization sequence enters the data sampling circuit 450 to the clock and data recovery circuit 300 are identical to the elements through which the equalization sequence enters the marginal sampling circuit 470 to the clock and data recovery circuit 300, and thus the data sequence and the marginal sequence are substantially synchronized.

Furthermore, referring to fig. 6 and 7 in combination, the equalization circuit of fig. 7 may be similar to the equalization circuit of fig. 6, with the addition of a slave-to-sequence circuit and a marginal trigger sampling circuit. In some embodiments, the data sampling circuit 450 of fig. 7 includes fifth and sixth sub-slave sequential circuits, the fifth sub-slave sequential circuit is connected between the third sub-slave sequential circuit 423 and the clock and data recovery circuit 300, the fifth sub-slave sequential circuit is used for sampling the third sub-slave sequence S3 according to the inverted data clock Ck2 to output a fifth sub-slave sequence, the fifth sub-slave sequential circuit gains the fifth sub-slave sequence to output a fifth sub-slave feedback sequence, and the fifth sub-slave feedback sequence is used for compensating the equalization sequence. The sixth sub-slave sequence is connected between the fourth sub-slave sequence 423 and the clock and data recovery circuit 300, and is configured to sample the fourth sub-slave sequence S4 according to the data clock Ck1 to output a sixth sub-slave sequence, and the sixth sub-slave sequence is further configured to gain the sixth sub-slave sequence to output a sixth sub-slave feedback sequence, and the sixth sub-slave feedback sequence is configured to compensate the equalization sequence. The fifth and sixth sub-sequences are the data sequences and are output to the clock and data recovery circuit 300.

The marginal sampling circuit 470 includes seventh and eighth trigger sampling circuits. The seventh trigger sampling circuit is connected between the fifth trigger sampling circuit 473 and the clock and data recovery circuit 300, and the eighth trigger sampling circuit is connected between the sixth trigger sampling circuit 463 and the clock and data recovery circuit 300. The operation is similar to the fifth trigger sampling circuit 473 and the sixth trigger sampling circuit 463, and will not be described again.

Similarly, in some embodiments, the data sampling circuit 450 includes seventh and eighth sub-sequential circuits, and the marginal sampling circuit 470 includes ninth and tenth trigger sampling circuits, which are not described again.

In summary, according to some embodiments, the decision feedback equalizer circuit removes marginal and marginal effects of the equalization sequence on the data, so as to reduce the error rate of the clock and data recovery circuit 300.

Claims

1. An equalization circuit, comprising:

a first operation circuit for compensating an equalization sequence with a plurality of slave feedback sequences to output a first sum sequence;

A second operation circuit for compensating the first summation sequence with a main feedback sequence to output a second summation sequence;

A data sampling circuit, comprising:

A main sequence direction circuit for sampling the second summation sequence according to a data clock to output a main sequence, the main sequence direction circuit gaining the main sequence to output the main feedback sequence; and

A plurality of slave sequence circuits, which are used for sampling the master sequence in sequence according to the data clock so as to output a plurality of slave sequences, wherein the slave sequences corresponding to the gains of the slave sequence circuits are used for outputting a plurality of slave feedback sequences; and

And the marginal sampling circuit is used for sampling the first summation sequence according to a marginal clock so as to output a marginal sequence.

2. The equalization circuit of claim 1, wherein the data sampling circuit comprises two slave sequence circuits, the two slave sequence circuits being a first slave sequence circuit and a second slave sequence circuit, respectively,

The first slave sequence circuit is used for sampling the master sequence according to the data clock so as to output a first slave sequence, and the first slave sequence circuit gains the first slave sequence and outputs the first slave sequence as a first slave feedback sequence;

The second slave sequence circuit is used for sampling the first slave sequence according to the data clock so as to output a second slave sequence, and the second slave sequence circuit gains the second slave sequence and outputs the second slave sequence as a second slave feedback sequence; and

The first operation circuit is used for compensating the equalization sequence by the first slave feedback sequence and the second slave feedback sequence and outputting the first summation sequence.

3. The equalization circuit of claim 2, wherein:

The main sequence direction circuit comprises:

a main trigger sampling circuit for sampling the second summation sequence according to the data clock to output the main sequence; and

A main gain circuit for gain the main sequence with a main multiplying power and outputting as the main feedback sequence;

the first slave sequence circuit comprises:

a first slave trigger sampling circuit for sampling the master sequence according to the data clock to output the first slave sequence; and

A first slave gain circuit for gain the first slave sequence with a first multiplying power and outputting the first slave sequence as the first slave feedback sequence; and

The second slave sequence circuit comprises:

a second slave trigger sampling circuit for sampling the first slave sequence according to the data clock to output the second slave sequence; and

And the second slave gain circuit is used for gain the second slave sequence with a second multiplying power and outputting the second slave sequence as the second slave feedback sequence.

4. The equalizer of claim 3, wherein each of the trigger sampling circuits is a D-type trigger, the phase of the data clock is substantially 180 degrees different from the phase of the margin clock, the first operation circuit is an adder, the second operation circuit is an adder, and the main multiplying power, the first multiplying power, and the second multiplying power are constants between-1 and 0, respectively.

5. The equalization circuit of claim 2, wherein the data sampling circuit comprises a third slave sequence circuit for sampling the second slave sequence according to the data clock and outputting a sampling result therefrom, the third slave sequence circuit being configured to gain the sampling result and output a third slave feedback sequence, the first arithmetic circuit being configured to compensate the equalization sequence with the first slave feedback sequence, the second slave feedback sequence, and the third slave feedback sequence to output the first summed sequence.

6. The equalization circuit of any of claims 1-5, wherein the marginal sampling circuit comprises a plurality of marginal trigger sampling circuits connected in series in sequence, the plurality of marginal trigger sampling circuits connected in series sequentially sampling the first summed sequence according to the marginal clock to output the marginal sequence, the number of marginal trigger sampling circuits being equal to the number of sequential circuits.

7. The equalization circuit of claim 1, wherein:

the rate of the equalization sequence is twice the rate of the data clock, the rate of the equalization sequence is twice the rate of the marginal clock, the main feedback sequence comprises a first sub-main feedback sequence and a second sub-main feedback sequence, and the second summation sequence comprises a first sub-summation sequence and a second sub-summation sequence;

The second operation circuit comprises a first sub operation circuit and a second sub operation circuit, wherein the first sub operation circuit is used for compensating the first addition sequence by the first sub main feedback sequence and outputting the first sub addition sequence, and the second sub operation circuit is used for compensating the first addition sequence by the second sub main feedback sequence and outputting the second sub addition sequence;

The main sequence direction circuit comprises:

a first sub-main sequence direction circuit for sampling the first sub-summation sequence according to the data clock to output a first sub-main sequence, the first sub-main sequence direction circuit being configured to gain the first sub-main sequence to output the first sub-main feedback sequence; and

A second sub-main sequence direction circuit for sampling the second sub-summation sequence according to the inverted data clock to output a second sub-main sequence, the second sub-main sequence direction circuit gaining the second sub-main sequence to output the second sub-main feedback sequence;

The data sampling circuit comprises four slave sequence circuits, wherein the four slave sequence circuits are a first sub-slave sequence circuit, a second sub-slave sequence circuit, a third sub-slave sequence circuit and a fourth sub-slave sequence circuit respectively;

The first sub-slave sequence-to-sequence circuit is used for sampling the first sub-master sequence according to the inverted data clock to output a first sub-slave sequence, and the first sub-slave sequence-to-sequence circuit gains the first sub-slave sequence to output a first sub-slave feedback sequence;

The second sub-slave sequence-to-sequence circuit is used for sampling the second sub-master sequence according to the data clock to output a second sub-slave sequence, and the second sub-slave sequence-to-sequence circuit gains the second sub-slave sequence to output a second sub-slave feedback sequence;

the third sub-slave sequence-to-sequence circuit is used for sampling the first sub-slave sequence according to the inverted data clock to output a third sub-slave sequence, and the third sub-slave sequence-to-sequence circuit gains the third sub-slave sequence to output a third sub-slave feedback sequence; and

The fourth sub-slave sequence circuit is used for sampling the second sub-slave sequence according to the data clock to output a fourth sub-slave sequence, and the fourth sub-slave sequence circuit gains the fourth sub-slave sequence to output a fourth sub-slave feedback sequence; and

The first operation circuit is used for compensating the equalization sequence by the first sub-feedback sequence, the second sub-feedback sequence, the third sub-feedback sequence and the fourth sub-feedback sequence and outputting the first summation sequence.

8. The equalization circuit of claim 7, wherein:

the first sub-main sequential circuit includes:

A first sub-main trigger sampling circuit for sampling the first sub-summation sequence according to the data clock to output the first sub-main sequence; and

A first sub-main gain circuit for gain the first sub-main sequence with a first sub-main multiplying power and outputting as the first sub-main feedback sequence;

The second sub-main sequential circuit includes:

A second sub-master trigger sampling circuit for sampling the second sub-sum sequence according to the inverted data clock to output the second sub-master sequence; and

A second sub-main gain circuit for gain the second sub-main sequence with a second sub-main multiplying power and outputting as the second sub-main feedback sequence; and

The first sub-main multiplying power and the second sub-main multiplying power are constants between-1 and 0 respectively.

9. The equalization circuit of claim 8, wherein:

The first sub-slave sequential circuit includes:

a first sub-slave trigger sampling circuit for sampling the first sub-master sequence according to the inverted data clock to output the first sub-slave sequence; and

A first sub-slave gain circuit for gain the first sub-slave sequence with a first sub-slave multiplying power and outputting the first sub-slave sequence as the first sub-slave feedback sequence;

the second sub-slave sequential circuit includes:

A second sub-slave trigger sampling circuit for sampling the second sub-master sequence according to the data clock to output the second sub-slave sequence; and

A second sub-slave gain circuit for gain the second sub-slave sequence with a second sub-slave multiplying power and outputting the second sub-slave sequence as the second sub-slave feedback sequence;

The third sub-slave sequential circuit includes:

a third sub-slave trigger sampling circuit for sampling the first sub-slave sequence according to the inverted data clock to output the third sub-slave sequence; and

A third sub-slave gain circuit for gain the third sub-slave sequence with a third sub-slave multiplying power and outputting the third sub-slave sequence as the third sub-slave feedback sequence;

The fourth sub-slave sequential circuit includes:

A fourth sub-slave trigger sampling circuit for sampling the second sub-master sequence according to the data clock to output the fourth sub-slave sequence; and

A fourth sub-slave gain circuit for gain the fourth sub-slave sequence with a fourth sub-slave multiplying power and outputting the fourth sub-slave sequence as the fourth sub-slave feedback sequence; and

The first sub-slave magnification, the second sub-slave magnification, the third sub-slave magnification, and the fourth sub-slave magnification are constants between-1 and 0, respectively.

10. The equalization circuit of claim 9, wherein:

The multiplying power value of the data clock in the reverse direction of the first sub-multiplying power at a high level is different from the multiplying power value of the data clock in the reverse direction of the first sub-multiplying power at a low level;

the multiplying power value of the second sub-multiplying power when the data clock is at a high level is different from the multiplying power value of the second sub-multiplying power when the data clock is at a low level;

The multiplying power value of the data clock with the third sub-multiplying power in the reverse direction at the high level is different from the multiplying power value of the data clock with the third sub-multiplying power in the reverse direction at the low level; and

The fourth sub-slave multiplying power is different from the multiplying power value of the fourth sub-slave multiplying power when the data clock is at the high level from the multiplying power value of the fourth sub-slave multiplying power when the data clock is at the low level.