CN112133674A - Metal diffusion barrier layer structure and forming method thereof - Google Patents
Metal diffusion barrier layer structure and forming method thereof Download PDFInfo
- Publication number
- CN112133674A CN112133674A CN202010863932.4A CN202010863932A CN112133674A CN 112133674 A CN112133674 A CN 112133674A CN 202010863932 A CN202010863932 A CN 202010863932A CN 112133674 A CN112133674 A CN 112133674A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- graphene
- diffusion barrier
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 121
- 239000002184 metal Substances 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 42
- 230000004888 barrier function Effects 0.000 title claims abstract description 39
- 238000009792 diffusion process Methods 0.000 title claims abstract description 34
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 52
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 198
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 35
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 229910052715 tantalum Inorganic materials 0.000 claims description 14
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 125000004432 carbon atom Chemical group C* 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- -1 graphite alkene Chemical class 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 abstract description 3
- 229910002804 graphite Inorganic materials 0.000 abstract 2
- 239000010439 graphite Substances 0.000 abstract 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 239000010949 copper Substances 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The invention discloses a metal diffusion barrier layer structure, which sequentially comprises a first metal layer, a first graphene layer, a second metal layer and a second graphene layer, wherein the first metal layer, the first graphene layer, the second metal layer and the second graphene layer cover the inner wall surface of a groove or a hole; wherein, first graphite alkene layer and second graphite alkene layer carry out the doping through pouring into carbon in to the second metal level, and carry out thermal treatment and form respectively on the interface of first metal level and second metal level, second metal level and third metal level, with replace traditional tantalum nitride as preventing the metal diffusion layer, can reduce barrier layer thickness by a wide margin, increase the proportion on the metal wire layer on the conducting cross-section, and can reduce metal interconnection resistance on the whole by a wide margin, improve the electromigration resistance of wire, and the technology integration is simple and easy, compatible with CMOS technology. The invention also discloses a method for forming the metal diffusion barrier layer structure.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a metal diffusion barrier layer structure for a subsequent interconnection technology and a forming method thereof.
Background
In the very large scale integrated circuit technology, with the miniaturization and the improvement of integration of devices, the number of conductor connecting lines in the circuit is also increased, so that the parasitic effect generated by the resistor (R) and the capacitor (C) in the conductor connecting line structure is enlarged, and a serious problem of transmission delay (RC delay) is caused.
In reducing the resistance of the wire, copper has been widely used in the wire structure to replace aluminum as the material of the conductor wire due to its high melting point, low resistivity and high electromigration resistance.
However, since copper is easily diffused in the dielectric layer, which causes deterioration of device performance, it is necessary to deposit a barrier layer for preventing copper diffusion in the metal line trench and the via hole in advance. At present, TaN/Ta is mainly used as a barrier layer, so that a copper wire is wrapped in the barrier layer, and the copper wire has the function of preventing copper diffusion.
However, as CMOS processes have progressed to 5nm and beyond, the size of the conductive lines has been reduced, so that the thickness of the barrier layer has increased dramatically in proportion to the total cross-section of the conductive lines, and the resistance of the barrier layer is much greater than that of copper, which has led to a dramatic increase in the resistance of copper interconnects. This puts higher demands on the structure and material properties of the barrier layer.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a metal diffusion barrier structure and a method for forming the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a metal diffusion barrier layer structure sequentially comprises a first metal layer, a first graphene layer, a second metal layer and a second graphene layer, wherein the first metal layer, the first graphene layer, the second metal layer and the second graphene layer cover the inner wall surface of a groove or a hole.
Further, the groove or the hole is filled with a third metal layer, the first graphene layer is formed on an interface between the first metal layer and the second metal layer, and the second graphene layer is formed on an interface between the second metal layer and the third metal layer.
Further, the first graphene layer and the second graphene layer are formed by implanting carbon into the second metal layer, doping the carbon, and performing heat treatment.
Further, the slot comprises an interconnect wire slot, the hole comprising a through hole.
Further, the slot or hole is formed in the dielectric layer.
Further, the dielectric layer comprises at least one of a low dielectric constant material layer, a silicon dioxide layer, a silicon nitride layer, a silicon carbide layer, an aluminum oxide layer and an aluminum nitride layer.
Further, the first metal layer material comprises tantalum, and the second metal layer material comprises nickel.
Further, the first graphene layer and/or the second graphene layer is a single layer or a plurality of layers.
A method for forming a metal diffusion barrier layer structure comprises the following steps:
the method comprises the following steps: providing a substrate, forming a dielectric layer on the substrate, and forming a groove or a hole on the dielectric layer;
step two: sequentially forming a first metal layer and a second metal layer on the inner wall surface of the groove or the hole;
step three: doping carbon atoms into the second metal layer by using an ion implantation process;
step four: continuously filling a third metal layer in the groove or the hole;
step five: and annealing, and forming graphene layers on the interfaces of the first metal layer and the second metal layer and the interfaces of the second metal layer and the third metal layer respectively.
Further, the annealing comprises laser annealing, and the temperature during annealing is 400-600 ℃.
According to the technical scheme, the graphene layers (the first graphene layer and the second graphene layer) are used for replacing the traditional tantalum nitride to serve as the copper diffusion prevention layer, so that the thickness of the barrier layer can be greatly reduced, the proportion of copper metal (a third metal layer) on a conductive section is increased, and the resistance of the barrier layer can be reduced by replacing the high-resistance tantalum nitride with graphene, so that the metal interconnection resistance can be greatly reduced on the whole. Meanwhile, the graphene layer is wrapped at the interface of the interconnected metal copper, so that the electromigration resistance of the copper wire can be improved. In addition, from the process integration, the total process steps are not increased, and the matching of the preparation process and the current mainstream process is good; in addition, the invention has simple process integration and can be well compatible with the current CMOS process.
Drawings
Fig. 1-7 are schematic views illustrating steps of a method for forming a metal diffusion barrier layer according to the present invention.
In the figure, 101, a silicon substrate, 102, a MOS device, 103, a resistor, 104, contact holes and interconnection lines, 201, a dielectric layer, 202, a wire groove or a through hole (groove or hole), 203, a tantalum film (first metal layer), 204, a nickel film (second metal layer), 205, a copper wire layer (third metal layer), 206, a first graphene film (first graphene layer), 206', a second graphene film (second graphene layer).
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 7, fig. 7 is a metal diffusion barrier layer structure according to a method for forming a metal diffusion barrier layer structure of the present invention in a preferred embodiment of the present invention. As shown in fig. 7, a metal diffusion barrier structure of the present invention includes a first metal layer 203, a first graphene layer 206, a second metal layer 204, and a second graphene layer 206' in this order, which are coated on the inner wall surface of a trench or a hole 202 (refer to fig. 3).
The groove or hole 202 is filled with a third metal layer 205; a first graphene layer 206 is formed at the interface between the first metal layer 203 and the second metal layer 204, and a second graphene layer 206' is formed at the interface between the second metal layer 204 and the third metal layer 205.
As an alternative embodiment, the slot 202 may comprise an interconnect slot and the aperture 202 may comprise a through-hole. The interconnection groove 202 is described below as an example, but not limited thereto.
As an alternative embodiment, the first metal layer 203 may include a tantalum film 203, the second metal layer 204 may include a nickel film 204, and the third metal layer 205 may include a copper wire layer 205 filled in the interconnection groove 202. But is not limited thereto.
Further, the metal diffusion barrier layer structure of the present invention can be built on a semiconductor substrate chip. The chip structure concerned may include: various integrated circuit devices are manufactured and formed on a semiconductor silicon substrate 101 by adopting a standard CMOS (complementary metal oxide semiconductor) process on the substrate 101, wherein the integrated circuit devices comprise MOS devices 102 such as related transistors and capacitors, resistors 103, metal contact holes and interconnection lines 104 between the MOS devices and the resistors, an isolation dielectric layer 105 and the like.
Wherein the digital circuit devices on the silicon substrate 101 can be fabricated using standard CMOS processes and have all the features of the technology node CMOS process. Through the subsequent interconnection process, a circuit module with a specific function can be formed.
Please refer to fig. 7. Interconnect trenches 202 are formed on dielectric layer 201. Dielectric layer 201 may be referred to as an isolation, passivation, and etch stop layer, including but not limited to at least one of a low-K (dielectric constant) material layer, a silicon dioxide layer, a silicon nitride layer, a silicon carbide layer, an aluminum oxide layer, and an aluminum nitride layer. That is, the dielectric layer 201 material of the present invention includes, but is not limited to, at least one of low K material, silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, and aluminum nitride. The thickness of the dielectric layer 201 can be 5 nm-500 nm.
Further, the first graphene layer 206 and/or the second graphene layer 206' may adopt a single-layer graphene film or a multi-layer graphene film structure. The thickness of the single-layer graphene film is about 4 angstroms, and the thickness of the single-layer graphene film can increase with the number of layers.
In the metal diffusion barrier layer structure of the present invention, the total thickness of the first metal layer 203, the first graphene layer 206, the second metal layer 204, and the second graphene layer 206' is not more than 3 nm. The metal material includes, but is not limited to, tantalum (Ta), nickel (Ni), copper (Cu), etc., and may further include a compound containing all or a part of the above elements formed for specific properties.
Taking the tantalum film 203 as the first metal layer 203 and the nickel film 204 as the second metal layer 204 as an example, the thicknesses of the tantalum film 203 and the nickel film 204 can be respectively within 1nm, and the sum of the thicknesses of the tantalum film 203 and the nickel film 204 is not more than 2 nm.
A method for forming a metal diffusion barrier structure according to the present invention is described in detail with reference to the accompanying fig. 1-7.
Referring to fig. 1-7, fig. 1-7 are schematic process steps of fabricating a metal diffusion barrier layer structure according to a method for forming a metal diffusion barrier layer structure of the present invention in a preferred embodiment of the present invention. As shown in fig. 1-7, a method for forming a metal diffusion barrier layer structure according to the present invention can be used to manufacture a metal diffusion barrier layer structure shown in fig. 7, and can include the following steps:
the method comprises the following steps: providing a substrate, forming a dielectric layer on the substrate, and forming a trench or hole in the dielectric layer.
Please refer to fig. 1. One semiconductor silicon substrate 101 may be used. First, various integrated circuit devices, including MOS devices 102 (front-end devices) such as transistors and capacitors, resistors 103, and metal contact holes and interconnection lines 104 therebetween, and isolation dielectric layers 105, etc., can be formed on a silicon substrate 101 by using a standard CMOS process.
Wherein the digital circuit devices on the silicon substrate 101 can be fabricated using standard CMOS processes and have all the features of the technology node CMOS process. Through the subsequent interconnection process, a circuit module with a specific function can be formed.
Please refer to fig. 2. Continuing to deposit a dielectric layer 201 on the isolation dielectric layer 105 of the silicon substrate 101; then, a subsequent metal interconnection process is performed.
Wherein, a dielectric layer 201 film such as silicon nitride, silicon oxide and the like can be deposited on the surface of the isolation dielectric layer 105 by using the CVD and other processes, and the thickness can be 200 nm-1000 nm; then, a trench (via hole) 202 for filling the interconnect metal may be formed on the dielectric layer 201 by photolithography, dry etching, or the like, as shown in fig. 3.
Step two: a first metal layer and a second metal layer are sequentially formed on the inner wall surface of the groove or the hole.
Please refer to fig. 4. In the wire groove 202, a metal tantalum film 203 and a nickel film 204 layer can be sequentially deposited on the dielectric layer 201 and the inner wall surface of the wire groove 202 by utilizing PVD or ALD and other processes, the total thickness is about 2nm, the redundant tantalum film 203 and nickel film 204 layer materials on the surface of the dielectric layer 201 except the wire groove 202 can be removed by a CMP process, the tantalum film 203 and nickel film 204 layers on the inner wall surface of the wire groove 202 are remained, and thus the tantalum film 203 layer as a first metal layer and the nickel film 204 layer as a second metal layer are formed on the inner wall surface of the wire groove 202.
Step three: and doping carbon atoms into the second metal layer by using an ion implantation process.
Next, an ion implantation process may be used to dope carbon atoms into the nickel film 204 layer.
Step four: the third metal layer continues to fill in the trenches or holes.
Please refer to fig. 5. Then, an electroplating or electroless plating process may be used to complete the deposition and filling of the copper metal wire layer 205 in the wire groove 202 by using the nickel film 204 in the wire groove 202 as a seed layer.
Step five: and annealing, and forming graphene layers on the interface of the first metal layer and the second metal layer and the interface of the second metal layer and the third metal layer respectively.
Please refer to fig. 6. Thereafter, a heat treatment process may be performed using laser annealing. The temperature during annealing can be 400-600 ℃.
As a result of the laser annealing, a single-layer or multi-layer graphene film (first graphene layer) 206 is formed at the interface of the tantalum thin film 203 and the nickel thin film 204, and a single-layer or multi-layer graphene film (second graphene layer) 206' is formed at the interface of the nickel thin film 204 and the copper wire layer 205.
Please refer to fig. 7. And finally, polishing to remove the redundant metals such as copper, nickel, tantalum and the like outside the wire groove 202 to form the metal diffusion barrier layer structure.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A metal diffusion barrier layer structure is characterized by sequentially comprising a first metal layer, a first graphene layer, a second metal layer and a second graphene layer, wherein the first metal layer, the first graphene layer, the second metal layer and the second graphene layer cover the inner wall surface of a groove or a hole.
2. The metal diffusion barrier layer structure of claim 1, wherein the trench or hole is further filled with a third metal layer, the first graphene layer is formed on an interface between the first metal layer and the second metal layer, and the second graphene layer is formed on an interface between the second metal layer and the third metal layer.
3. The metal diffusion barrier layer structure of claim 1 or 2, wherein the first graphene layer and the second graphene layer are formed by doping the second metal layer by implanting carbon and performing a heat treatment.
4. The metal diffusion barrier structure of claim 1, wherein the trench comprises an interconnect line trench and the hole comprises a via.
5. The metal diffusion barrier structure of claim 1 or 4, wherein the trench or hole is formed in a dielectric layer.
6. The metal diffusion barrier layer structure of claim 5, wherein the dielectric layer comprises at least one of a layer of low dielectric constant material, a layer of silicon dioxide, a layer of silicon nitride, a layer of silicon carbide, a layer of aluminum oxide, and a layer of aluminum nitride.
7. The metal diffusion barrier structure of claim 1, wherein said first metal layer material comprises tantalum and said second metal layer material comprises nickel.
8. The metal diffusion barrier layer structure of claim 1, wherein the first graphene layer and/or the second graphene layer is a single layer or a plurality of layers.
9. A method for forming a metal diffusion barrier layer structure is characterized by comprising the following steps:
the method comprises the following steps: providing a substrate, forming a dielectric layer on the substrate, and forming a groove or a hole on the dielectric layer;
step two: sequentially forming a first metal layer and a second metal layer on the inner wall surface of the groove or the hole;
step three: doping carbon atoms into the second metal layer by using an ion implantation process;
step four: continuously filling a third metal layer in the groove or the hole;
step five: and annealing, and forming graphene layers on the interfaces of the first metal layer and the second metal layer and the interfaces of the second metal layer and the third metal layer respectively.
10. The method for forming the metal diffusion barrier layer structure according to claim 9, wherein the annealing comprises laser annealing, and the temperature during the annealing is 400-600 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010863932.4A CN112133674A (en) | 2020-08-25 | 2020-08-25 | Metal diffusion barrier layer structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010863932.4A CN112133674A (en) | 2020-08-25 | 2020-08-25 | Metal diffusion barrier layer structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112133674A true CN112133674A (en) | 2020-12-25 |
Family
ID=73847131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010863932.4A Pending CN112133674A (en) | 2020-08-25 | 2020-08-25 | Metal diffusion barrier layer structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112133674A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120258587A1 (en) * | 2011-04-07 | 2012-10-11 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Method of Forming Graphene on a Surface |
| US20140106561A1 (en) * | 2011-12-09 | 2014-04-17 | Intermolecular, Inc. | Graphene Barrier Layers for Interconnects and Methods for Forming the Same |
| KR20160117772A (en) * | 2015-03-31 | 2016-10-11 | 고려대학교 산학협력단 | Method of manufacturing a graphene thin layer |
| US20170062345A1 (en) * | 2015-09-02 | 2017-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| WO2018118081A1 (en) * | 2016-12-23 | 2018-06-28 | Intel Corporation | Graphitic liners for integrated circuit devices |
| CN111106060A (en) * | 2018-10-25 | 2020-05-05 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
-
2020
- 2020-08-25 CN CN202010863932.4A patent/CN112133674A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120258587A1 (en) * | 2011-04-07 | 2012-10-11 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Method of Forming Graphene on a Surface |
| US20140106561A1 (en) * | 2011-12-09 | 2014-04-17 | Intermolecular, Inc. | Graphene Barrier Layers for Interconnects and Methods for Forming the Same |
| KR20160117772A (en) * | 2015-03-31 | 2016-10-11 | 고려대학교 산학협력단 | Method of manufacturing a graphene thin layer |
| US20170062345A1 (en) * | 2015-09-02 | 2017-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| WO2018118081A1 (en) * | 2016-12-23 | 2018-06-28 | Intel Corporation | Graphitic liners for integrated circuit devices |
| CN111106060A (en) * | 2018-10-25 | 2020-05-05 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9076844B2 (en) | Process integration scheme to lower overall dielectric constant in BEoL interconnect structures | |
| CN107836034B (en) | Ruthenium metal feature fill for interconnects | |
| US10879107B2 (en) | Method of forming barrier free contact for metal interconnects | |
| US20170263721A1 (en) | Copper-filled trench contact for transistor performance improvement | |
| US7488677B2 (en) | Interconnect structures with encasing cap and methods of making thereof | |
| US10475742B2 (en) | Method for forming semiconductor device structure having conductive structure with twin boundaries | |
| JP2012527751A (en) | Semiconductor structure and method for forming the same | |
| US6998342B2 (en) | Electronic device manufacturing method | |
| US7586142B2 (en) | Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same | |
| US9793206B1 (en) | Heterogeneous metallization using solid diffusion removal of metal interconnects | |
| US7618887B2 (en) | Semiconductor device with a metal line and method of forming the same | |
| JP5089850B2 (en) | Semiconductor device | |
| US8338951B2 (en) | Metal line of semiconductor device having a diffusion barrier with an amorphous TaBN layer and method for forming the same | |
| CN112133674A (en) | Metal diffusion barrier layer structure and forming method thereof | |
| US20040203228A1 (en) | Method of forming a tungsten plug | |
| US20240105620A1 (en) | Interconnect with disconnected liner and metal cap | |
| KR100462759B1 (en) | Metal line with a diffusion barrier and fabrication method thereof | |
| CN111446152A (en) | Method for preparing low-dielectric-constant dielectric layer | |
| US8053895B2 (en) | Metal line of semiconductor device having a multilayer molybdenum diffusion barrier and method for forming the same | |
| CN115588648A (en) | Manufacturing method of interconnection structure, interconnection structure and semiconductor device | |
| US7981781B2 (en) | Metal line of semiconductor device having a diffusion barrier and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |