CN112133362B - Memory storage device and memory testing method thereof - Google Patents
Memory storage device and memory testing method thereof Download PDFInfo
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- CN112133362B CN112133362B CN201910553942.5A CN201910553942A CN112133362B CN 112133362 B CN112133362 B CN 112133362B CN 201910553942 A CN201910553942 A CN 201910553942A CN 112133362 B CN112133362 B CN 112133362B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a memory storage device and a memory testing method for testing a memory array thereof. The memory testing method comprises the following steps: writing first data to a plurality of first sections of the memory array, and writing second data to a second section of the memory array; reading the plurality of first sections to obtain third data, and reading the second section to obtain fourth data; and converting the fourth data into fifth data, wherein the fifth data is the same as the check data obtained by encoding the first data by an encoding circuit corresponding to a decoding circuit of the memory storage device.
Description
Technical Field
The present invention relates to a memory testing technology, and more particularly, to a memory storage device with error correction code function and a memory testing method thereof.
Background
In general, when testing memory cells of a memory storage device such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a plurality of test data in a specific form, such as all 1 data, all 0 data, checkerboard data, and anti-checkerboard data, are written into the memory cells to test whether the leakage path of each memory cell has abnormal leakage. However, for a memory storage device having an error correction code (Error Correction Code, ECC) function, the data in the data bits and the data in the verification bits cannot be controlled to be in a predetermined form at the same time, resulting in a decrease in test coverage and an increase in test time.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a memory storage device and a memory testing method thereof, which can maintain good test coverage and save test time.
The embodiment of the invention provides a memory testing method for testing a memory array of a memory storage device. The memory testing method comprises the following steps: writing first data to a plurality of first sections of the memory array, and writing second data to a second section of the memory array; reading the plurality of first sections to obtain third data, and reading the second section to obtain fourth data; and converting the fourth data into fifth data, wherein the fifth data is the same as the check data obtained by encoding the first data by an encoding circuit corresponding to a decoding circuit of the memory storage device.
An embodiment of the invention provides a memory storage device, which comprises a memory array and a memory control circuit. The memory array comprises a plurality of first sections and a second section. The memory control circuit includes a data write circuit, a data read circuit, a decode circuit, and a data conversion circuit. The data writing circuit is coupled to the memory array for writing first data into the plurality of first sections and writing second data into the second sections. The data reading circuit is coupled to the memory array for reading the plurality of first sections to obtain third data and reading the second section to obtain fourth data. The decoding circuit is coupled to the data reading circuit. The data conversion circuit is coupled between the data reading circuit and the decoding circuit and is used for converting fourth data into fifth data, wherein the fifth data is identical to check data obtained by encoding the first data by the encoding circuit corresponding to the decoding circuit.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a memory storage device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a memory testing method according to an embodiment of the invention;
FIG. 3 is a flow chart of a memory testing method according to an embodiment of the invention.
Reference numerals illustrate:
100: memory storage device
110: host interface
120: memory control circuit
121: data writing circuit
122: data reading circuit
123: data conversion circuit
124: decoding circuit
125: data correction circuit
130: memory array
D1: first data
D2: second data
D3: third data
D3': corrected third data
D4: fourth data
D5: fifth data
D6: sixth data
S1: first section
S2: second section
S310, S320, S330, S340: steps of a memory test method
Detailed Description
Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to fig. 1, a memory storage device 100 includes a host interface 110, a memory control circuit 120, and a memory array 130. The memory storage device 100 may be, for example, a volatile memory (volatile memory) used with a host system (not shown) that can write data to the memory storage device 100 or read desired data from the memory storage device 100. The memory storage device 100 employs, for example, an error correction code (Error Correction Code, ECC) scheme (scheme).
The host interface 110 is coupled to the host system and is used for communicating with the host system, for example, receiving write data from the host system or transmitting data read by the host system back to the host system. However, the specific type and implementation of the host interface 110 is not limited by the present invention.
The memory control circuit 120 is coupled to the host interface 110 and the memory array 130, and is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations of writing, reading or deleting data in the memory array 130 according to instructions of the host system.
The memory array 130 includes a plurality of memory cells, and each memory cell may be used to store one or more bits of data.
Referring to fig. 2, the memory testing method of the present embodiment is applicable to the memory storage device 100 in fig. 1, and will be described below with reference to the memory storage device 100. The memory control circuit 120 further includes a data write circuit 121, a data read circuit 122, a data conversion circuit 123, a decoding circuit 124, and a data correction circuit 125. The memory cells in the memory array 130 can be divided into a plurality of first segments S1 and a corresponding one of the second segments S2.
In the present embodiment, the memory cells to be tested in the memory array 130 can be divided into 16 first sections S1 and one second section S2, and each of the first sections S1 and the second sections S2 is used for recording 8 bits of data, for example, but the invention is not limited thereto.
In the present embodiment, the decoding circuit 124 of the memory storage device 100 adopting the error correction code scheme is, for example, an error correction code decoder (ECC decoder), and the corresponding encoding circuit of the decoding circuit 124 is an error correction code encoder (ECC decoder). In this embodiment, the error correction code encoder encodes all data (e.g., data consisting of 16 repeated 8-bit data segments) that conforms to a predetermined pattern (e.g., consisting of multiple repeated data segments) to obtain all 0 parity data (e.g., 8-bit parity data). However, the specific algorithm and implementation of the error correction code scheme employed by the memory storage device 100 are not limited herein. In addition, in other embodiments, the memory storage device 100 may also employ other error correction code schemes, and the present invention is not limited thereto.
The data writing circuit 121 is coupled to the host interface 110 and the memory array 130, and is used for writing the first data D1 into the plurality of first segments S1 and writing the second data D2 into the second segments S2. In particular, since the first data D1 and the second data D2 are written without passing through the encoding circuit, the contents of the first data D1 and the second data D2 are controllable. It should be noted that, when the first data D1 and the second data D2 are controllable, the test of the memory array 130 can have high coverage and save test time.
In the present embodiment, the first data D1 is 128-bit data and is composed of 16-bit 8-bit second data D2 (e.g. by concatenation), so that the first data D1 belongs to data conforming to a predetermined pattern. However, the present invention is not limited to the specific data types of the first data D1 and the second data D2, and those skilled in the art can implement the present invention according to their requirements.
In the present embodiment, the first data D1 is written into the plurality of first sections S1 of the memory array 130 by the data writing circuit 121 without passing through the encoding circuit corresponding to the decoding circuit 124, and the second data D2 is written into the second section S2 of the memory array 130 by the data writing circuit 121 without passing through the encoding circuit corresponding to the decoding circuit 124.
The data reading circuit 122 is coupled to the data correction circuit 125 and also coupled between the memory array 130 and the data conversion circuit 123, and is configured to read the first sections S1 to obtain the third data D3, and read the second sections S2 to obtain the fourth data D4, and transmit the fourth data D4 to the data conversion circuit 123.
The data conversion circuit 123 is coupled between the data reading circuit 122 and the decoding circuit 124 for converting the fourth data D4 into the fifth data D5. Specifically, the fifth data D5 is converted by the data conversion circuit 123 into data identical to the check data obtained by encoding the first data D1 by the encoding circuit corresponding to the decoding circuit 124. For example, the encoding circuit corresponding to the decoding circuit 124 can encode the first data D1 to obtain an encoding result, and the encoding result includes a first portion and a second portion, wherein the first portion corresponds to the first data D1 and the second portion corresponds to the check data. In particular, the content of the fifth data D5 outputted from the data conversion circuit 123 is the same as the content of the verification data.
It should be noted that the specific implementation of the data conversion circuit 123 is not limited by the present invention, and those skilled in the art can design the data conversion circuit 123 according to the error correction code scheme and/or the content of the first data D1 adopted by the memory storage device 100.
In this embodiment, since the encoding circuit corresponding to the decoding circuit 124 encodes any data according to the predetermined pattern to obtain all 0 check data, the data conversion circuit 123 may be, for example, a circuit designed to perform an exclusive or (XOR) operation on the input data and the second data D2. In detail, the encoding circuit corresponding to the decoding circuit 124 encodes the first data D1 according to the predetermined pattern to obtain all 0 check data (e.g. 8 bits), so that the data conversion circuit 123 also converts the fourth data D4 into all 0 fifth data (e.g. 8 bits) when the fourth data D4 is identical to the second data D2.
The decoding circuit 124 is coupled to the data reading circuit 122 and the data converting circuit 123, and is configured to determine whether an error bit exists between the third data D3 and the fifth data D5 of the memory array 130 or whether an abnormal memory cell exists between the first and second sections S1 and S2 according to the third data D3 read from the first sections S1 and the fifth data D5 converted from the fourth data D4 read from the second sections S2, and generate the sixth data D6 including the error bit information. For example, the sixth data D6 may include information about which bits of the third data D3 and the fifth data D5 have errors, or information about which memory cells of the first section S1 and the second section S2 have anomalies. In other words, the decoding circuit 124 may check the memory array 130 to find the abnormal memory cells therein according to the third data D3 and the fifth data D5. For example, when the sixth data D6 shows that the third data D3 and the fifth data D5 have no errors, it indicates that the first and second sections S1 and S2 of the memory array 130 pass the verification. Conversely, when the sixth data D6 includes a certain error bit in the third data D3 and the fifth data D5, it indicates that the corresponding memory cells in the first and second sections S1 and S2 of the memory array 130 may be abnormal.
In the present embodiment, after receiving the third data D3 and the fifth data D5, the decoding circuit 124, for example, regards the fifth data D5 as check data and performs an error correction code decoding operation according to the check data, so as to find out the error bits in the third data D3 and the fifth data D5 and generate the sixth data D6 according to the error bits, where the error bits are regarded as corresponding to the abnormal memory cells in the memory array 130. Therefore, the memory testing method of the memory storage device 100 according to the present embodiment can find the abnormal memory cells in the first and second sections S1 and S2 of the memory array 130.
The data correction circuit 125 is coupled to the data reading circuit 122, the decoding circuit 124 and the host interface 110, and is configured to correct the third data D3 according to the sixth data D6, and output the corrected third data D3' to the host system through the host interface 110. For example, the data correction circuit 125 can learn which bits of the third data D3 are incorrect from the sixth data D6, and flip the incorrect bits to obtain corrected third data D3', and output the corrected third data D3' to the host interface 110.
In this embodiment, the data correction circuit is, for example, an Error Correction Code (ECC) corrector. The data correction circuit 125, for example, inverts the error bit in the third data D3 to obtain corrected third data D3 'and outputs the corrected third data D3' to the host interface 110. Therefore, the memory testing method of the memory storage device 100 according to the present embodiment can find out the abnormal memory cells in the first and second sections S1 and S2 of the memory array 130, and can also maintain the error correction function, and correct the data with errors and transmit the corrected data to the host system.
Referring to fig. 3, the memory testing method of the present embodiment is applicable to the memory storage device 100 in fig. 1 and 2, and therefore will be described below with reference to the memory storage device 100. In addition, the details of each step in this embodiment, which are already described in the previous paragraphs, will not be repeated.
First, the data writing circuit 121 writes the first data D1 to the first sections S1 of the memory array 130 and writes the second data D2 to the second sections S2 of the memory array 130 (step S310). Next, the data reading circuit 122 reads the first sections S1 to obtain the third data D3, and reads the second sections S2 to obtain the fourth data D4 (step S320). Subsequently, the data conversion circuit 123 converts the fourth data D4 into the fifth data D5 (step S330). Accordingly, the decoding circuit 124 can verify the memory array 130 according to the third data D3 and the fifth data D5 (step S340), for example, including finding abnormal memory cells in the first and second sections S1 and S2, or determining error bits in the third data D3 and the fifth data D5.
In some cases, there is a need to transmit the read data back to the host system, so the data correction circuit 125 can correct the third data D3 according to the third data D3 and the error bit thereof, and then output the corrected third data D3' to the host system through the host interface 110.
In summary, according to the memory device and the memory testing method thereof provided by the embodiments of the present invention, the first data and the second data are respectively written into the first section and the second section of the memory array in a manner of controlling the data content, the data in the first section and the second section are respectively read, and the data read from the second section is converted into the check data after the first data is encoded by the encoding circuit corresponding to the decoding circuit of the memory device. The memory array is then verified using the decoding circuitry in the memory storage device. Accordingly, the memory storage device can maintain good test coverage and save test time under the condition that the memory storage device also has an error correction function.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A memory testing method for testing a memory array of a memory storage device, the memory testing method comprising:
writing first data to a plurality of first sections of the memory array and writing second data to a second section of the memory array;
reading the plurality of first sections to obtain third data, and reading the second section to obtain fourth data;
converting the fourth data into fifth data, wherein the fifth data is identical to the check data obtained by encoding the first data by an encoding circuit corresponding to a decoding circuit of the memory storage device; and
the memory array is verified based on the third data and the fifth data.
2. The memory testing method of claim 1, further comprising:
and judging error bits in the third data and the fifth data by utilizing the decoding circuit according to the third data and the fifth data, wherein the encoding circuit is an error correction code encoder and the decoding circuit is an error correction code decoder.
3. The memory testing method of claim 2, further comprising:
correcting the third data according to the third data and the error bit; and
outputting the corrected third data to a host system.
4. The memory testing method of claim 1, wherein the first data consists of a plurality of the second data.
5. The memory test method according to claim 1, wherein the encoding circuit is a circuit that encodes any data conforming to a predetermined pattern to obtain all 0 check data.
6. The memory testing method of claim 5, wherein any data comprised of a plurality of repeated data segments conforms to the predetermined pattern.
7. The memory testing method of claim 5, wherein the first data conforms to the preset pattern, wherein converting the fourth data into the fifth data comprises:
and performing exclusive OR operation on the fourth data and the second data to obtain the fifth data.
8. A memory storage device, comprising:
a memory array including a plurality of first sections and second sections; and
a memory control circuit comprising:
a data writing circuit, coupled to the memory array, for writing first data into the plurality of first segments and writing second data into the second segments;
a data reading circuit coupled to the memory array for reading the first sections to obtain third data and the second sections to obtain fourth data;
a decoding circuit coupled to the data reading circuit; and
the data conversion circuit is coupled between the data reading circuit and the decoding circuit and is used for converting the fourth data into fifth data, wherein the fifth data is identical to check data obtained by encoding the first data by an encoding circuit corresponding to the decoding circuit;
wherein the decoding circuitry is to verify the memory array based on the third data and the fifth data.
9. The memory storage device of claim 8, wherein the decoding circuit is further configured to determine error bits in the third data and the fifth data based on the third data and the fifth data, wherein the memory control circuit further comprises:
a data correction circuit, coupled to the data reading circuit and the decoding circuit, for correcting the third data according to the third data and the error bit, wherein the memory storage device further comprises:
the host interface is coupled to the memory control circuit and used for outputting the corrected third data to a host system.
10. The memory storage device of claim 8, wherein the first data consists of a plurality of the second data.
11. The memory storage device of claim 8, wherein the encoding circuit is a circuit that encodes any data that meets a predetermined pattern to obtain all 0 check data.
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| CN1881455A (en) * | 2005-06-16 | 2006-12-20 | 联发科技股份有限公司 | Methods and systems for generating error correction codes |
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