CN112133201A - Array substrate and display panel display device - Google Patents
Array substrate and display panel display device Download PDFInfo
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- CN112133201A CN112133201A CN202011066201.3A CN202011066201A CN112133201A CN 112133201 A CN112133201 A CN 112133201A CN 202011066201 A CN202011066201 A CN 202011066201A CN 112133201 A CN112133201 A CN 112133201A
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Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate includes: the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area and a binding area; the fan-out area is positioned between the binding area and the display area; the fan-out area is provided with a plurality of first connecting lines; the binding region is provided with a plurality of first binding terminals; the first connecting wires are electrically connected with the first binding terminals in a one-to-one correspondence manner; the first binding terminals are arranged along a first direction; along the first direction, the binding region comprises a first region and/or a second region and a third region, and the first region and the second region are positioned at two opposite sides of the third region; the plurality of first binding terminals are located in the first region and/or the second region; in the first direction, lengths of the plurality of first binding terminals in the binding region gradually decrease from the center to both sides, and widths of the plurality of first binding terminals gradually increase from the center to both sides. The embodiment of the invention is beneficial to realizing narrow frame design.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The fingerprint identification technology is the most widely applied one of the biological characteristic identification technologies, and can be applied to an intelligent terminal to realize functions such as intelligent unlocking, online payment and the like. The fingerprint identification module and the display panel can be prepared respectively, and the fingerprint identification module is fixed outside the display panel, so that a display screen for fingerprint identification on the integrated screen is formed; the fingerprint identification module and the display panel can be prepared simultaneously, the fingerprint identification module is arranged in the display panel to form a display screen with fingerprint identification in the integrated screen, and the product has market competitiveness due to the fact that the thickness of the fingerprint identification module is smaller.
Fingerprint identification's display screen in current integrated screen, owing to increased fingerprint identification's function, need set up the signal that is relevant with the fingerprint identification module and walk the line, lead to the increase of the quantity of signal walking the line on the array substrate, consequently need more spaces to set up the signal and walk the line, this is unfavorable for the narrow frame design of display panel.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which are beneficial to realizing narrow frame design.
In a first aspect, an embodiment of the present invention provides an array substrate, including: the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area and a binding area;
the fan-out area is positioned between the binding area and the display area;
the fan-out area is provided with a plurality of first connecting lines; the binding region is provided with a plurality of first binding terminals; the first connecting wires are electrically connected with the first binding terminals in a one-to-one correspondence manner; the first binding terminals are arranged along a first direction;
along the first direction, the binding region comprises a first region and/or a second region and a third region, and the first region and the second region are positioned at two opposite sides of the third region; a plurality of the first binding terminals are located in the first region and/or the second region;
in the first direction, the lengths of the first binding terminals in the binding region gradually decrease from the center to two sides, and the widths of the first binding terminals gradually increase from the center to two sides; the length direction of the first binding terminal is perpendicular to the first direction, and the width direction of the first binding terminal is parallel to the first direction.
In a second aspect, an embodiment of the present invention provides a display panel, including any one of the array substrates provided in the first aspect.
In a third aspect, an embodiment of the present invention provides a display device, including any one of the display panels provided in the second aspect.
According to the technical scheme provided by the embodiment of the invention, the first area and/or the second area and the third area are/is arranged in the binding area along the first direction, the first area and the second area are positioned at two opposite sides of the third area, the plurality of first binding terminals are positioned in the first area and/or the second area, and the length of the plurality of first binding terminals in the binding area is gradually reduced from the center to two sides along the first direction, so that the arrangement number of the first connecting lines can be increased on the premise of not increasing the width of the non-display area, and the narrow-frame design is favorably realized. Through along first direction, set up the width that a plurality of first binding terminals and increase from center to both sides gradually, can compensate along first direction, the first influence that causes the area of binding the terminal of reducing gradually of binding terminal length guarantees good electric conductive property between first connecting wire and the outside connecting wire of array substrate.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of another array substrate structure according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a partial enlarged structure of a display device according to an embodiment of the invention;
fig. 9 is a schematic partial enlarged structure view of another display device according to an embodiment of the present invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.
In the prior art, a fingerprint identification function is added to a fingerprint identification display panel in an integrated screen, and signal routing lines need to be additionally arranged on an array substrate, so that the number of the signal routing lines on the array substrate is increased, and a larger space needs to be reserved on the array substrate to arrange the signal routing lines. This results in an increase in the width of the non-display area of the array substrate, which is not favorable for narrow bezel design.
In order to solve the above technical problem, an embodiment of the present invention provides an array substrate, including a display area and a non-display area surrounding the display area, where the non-display area includes a fan-out area and a binding area; the fan-out area is located between the binding area and the display area.
The fan-out area is provided with a plurality of first connecting lines, and the binding area is provided with a plurality of first binding terminals; the first connecting lines are electrically connected with the first binding terminals in a one-to-one correspondence, and the first binding terminals are arranged along a first direction.
Along the first direction, the binding region includes a first region and/or a second region and a third region, the first region and the second region are located on opposite sides of the third region, and the plurality of first binding terminals are located in the first region and/or the second region.
Along the first direction, the length of a plurality of first binding terminals in the binding region gradually decreases from the center to two sides, the width of the first binding terminals gradually increases from the center to the two sides, the length direction of the first binding terminals is perpendicular to the first direction, and the width direction of the first binding terminals is parallel to the first direction.
Adopt above-mentioned technical scheme, along first direction, set up first district and/or second district and third district in the district of binding, and first district and second district are located the relative both sides of third district, a plurality of first terminals of binding are located first district and/or second district, along first direction, the length that binds a plurality of first terminals of binding in the district reduces from the center to both sides gradually, under the prerequisite that does not increase non-display area width, can increase the quantity that sets up of first connecting line, be favorable to realizing the design of narrow frame. Through along first direction, set up the width that a plurality of first binding terminals and increase from center to both sides gradually, can compensate along first direction, the first influence that causes the area of binding the terminal of reducing gradually of binding terminal length guarantees good electric conductive property between first connecting wire and the outside connecting wire of array substrate.
The above is the core idea of the present invention, and based on the embodiments of the present invention, a person skilled in the art can obtain all other embodiments without creative efforts, which belong to the protection scope of the present invention. The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, as shown in fig. 1, the array substrate 100 includes a display area AA and a non-display area NA surrounding the display area AA, the non-display area NA includes a fan-out area 101 and a bonding area 102; the fan-out area 101 is located between the bonding area 102 and the display area AA.
The fan-out area 101 is provided with a plurality of first connecting lines 110, and the binding area 102 is provided with a plurality of first binding terminals 120; the first connecting lines 110 are electrically connected to the first binding terminals 120 in a one-to-one correspondence, and the first binding terminals 120 are arranged in a first direction.
In the first direction, the binding region 102 includes a first region 1021 and/or a second region 1022 and a third region 1023, the first region 1021 and the second region 1022 are located at opposite sides of the third region 1023, and the plurality of first binding terminals 120 are located at the first region 1021 and/or the second region 1022.
In the first direction, the lengths of the plurality of first binding terminals 120 in the binding region 102 are gradually decreased from the center to both sides, the widths of the plurality of first binding terminals 120 are gradually increased from the center to both sides, the length direction of the first binding terminals 120 is perpendicular to the first direction, and the width direction of the first binding terminals 120 is parallel to the first direction.
Exemplarily, as shown in fig. 1, a fan-out area 101 and a bonding area 102 are disposed in a non-display area NA, the fan-out area 101 is provided with a plurality of first connection lines 110, the bonding area 102 is provided with a plurality of first bonding terminals 120, one end of each first connection line 110 is electrically connected to a corresponding first bonding terminal 120, the other end of each first connection line 110 is electrically connected to a signal trace of the non-display area NA, and each first connection line 110 at least includes an oblique trace. In the first direction, the binding region 102 includes a first region 1021, a second region 1022, and a third region 1023, the first region 1021 and the second region 1022 are located at opposite sides of the third region 1023, and the plurality of first binding terminals 120 are located at the first region 1021 and the second region 1022. In the first direction, the lengths of the plurality of first binding terminals 120 in the binding region 102 in the second direction are gradually decreased from the center to both sides, wherein the second direction is perpendicular to the first direction. Therefore, along the first direction, the width of the space for disposing the first binding terminal 120 in the non-display area NA in the second direction gradually decreases, and then, along the first direction, the width of the space for disposing the first connecting line 110 in the non-display area NA in the second direction gradually increases, and along the second direction, a greater number of oblique routing lines can be disposed, that is, a greater number of first connecting lines 110 can be disposed in the non-display area NA. Therefore, on the premise that the width of the non-display area NA is not increased, the number of the first connecting lines 110 can be increased, and narrow-frame design is facilitated. In other embodiments, it is also possible that in the first direction, the binding area 102 includes a first area 1021 and a third area 1023, and the plurality of first binding terminals 120 are located in the first area 1021; alternatively, in the first direction, the binding region 102 includes the second region 1022 and the third region 1023, and the plurality of first binding terminals 120 are located at the second region 1022.
Specifically, the first connection line 110 is electrically connected to the connection line outside the array substrate 100 through the corresponding first binding terminal 120 and the conductive paste applied on the first binding terminal 120, the length and the width of the first binding terminal 120 determine the area of the first binding terminal 120, and the conductive performance between the first connection line 110 and the connection line outside the array substrate 100 is related to the area of the first binding terminal 120. In the first direction, the lengths of the plurality of first binding terminals 120 in the binding region 102 in the second direction gradually decrease from the center to two sides, resulting in a decrease in the area of the first binding terminals 120, so that the conductivity between the first connecting line 110 and the external connecting line of the array substrate 100 is poor, and the transmission of signals between the first connecting line 110 and the external connecting line of the array substrate 100 is affected. By gradually increasing the width of the plurality of first binding terminals 120 in the first direction from the center to both sides along the first direction, the influence of the gradual decrease of the length of the first binding terminals 120 in the second direction on the area of the first binding terminals 120 along the first direction can be compensated, and good conductivity between the first connecting line 110 and the external connecting line of the array substrate 100 is ensured.
Alternatively, with continued reference to fig. 1, the lengths of the plurality of first connection lines 110 in the fan-out area 101 gradually increase from the center to both sides along the first direction.
Illustratively, as shown in fig. 1, along the first direction, the lengths of the plurality of first binding terminals 120 in the binding region 102 in the second direction gradually decrease from the center to both sides, and the length of the orthographic projection of the first connecting line 110 in the second direction gradually increases from the center to both sides, so that the first connecting line 110 and the first binding terminal 120 can be electrically connected. The inclination angle between the first connecting line 110 and the second direction gradually increases from the center to both sides along the first direction, the length of the first connecting line 110 is in a proportional relationship with the length of the orthographic projection of the first connecting line 110 in the second direction, and is in a proportional relationship with the inclination angle between the first connecting line 110 and the second direction, and thus the lengths of the plurality of first connecting lines 110 in the fan-out area 101 gradually increase from the center to both sides.
Optionally, with continued reference to fig. 1, the first binding terminals 120 in the binding region 102 are equal in area.
Specifically, the area of the first binding terminal 120 determines the contact area of the first connecting line 110 electrically connected with the external connecting line of the array substrate 100, and the difference in the area of each first binding terminal 120 in the binding region 102 may cause the difference in the conductivity of each first connecting line 110 and the external connecting line of the array substrate 100. By setting the areas of the first binding terminals 120 in the binding region 102 to be equal, it is possible to ensure that the conductive performance of the first connection lines 110 is the same as that of the external connection lines of the array substrate 100.
Optionally, fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, as shown in fig. 2, a fan-out region 101 is provided with a plurality of second connection lines 130, and a bonding region 102 is provided with a plurality of second bonding terminals 140; the second connecting wires 130 are electrically connected to the second binding terminals 140 in a one-to-one correspondence, and the second binding terminals 140 are arranged along the first direction.
In the first direction, the third area 1023 includes a first sub-area 1023a, a second sub-area 1023b and a third sub-area 1023c arranged in sequence, and the plurality of second binding terminals 140 are located in the third area 1023.
In the first direction, the lengths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c are greater than the length of the second binding terminals 140 in the second sub-area 1023b, and the widths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c are less than the width of the second binding terminals 140 in the second sub-area 1023 b; the length direction of the second binding terminals 140 is perpendicular to the first direction, and the width direction of the second binding terminals 140 is parallel to the first direction.
Illustratively, as shown in fig. 2, the fan-out area 101 is provided with a plurality of second connecting lines 130, the bonding area 102 is provided with a plurality of second bonding terminals 140, one end of each second connecting line 130 is electrically connected to the corresponding second bonding terminal 140, the other end of each second connecting line 130 is electrically connected to a signal line (not shown) in the display area AA, and each second connecting line 130 at least includes an oblique trace. The lengths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c in the second direction are both greater than the lengths of the second binding terminals 140 in the second sub-area 1023b in the second direction, wherein the second direction is perpendicular to the first direction, and then the width of the space in the second sub-area 1023b for arranging the second binding terminals 140 is smaller in the second direction, that is, the width of the arrangement space of the second connection lines 130 electrically connected with the second binding terminals 140 in the second sub-area 1023b is larger in the second direction, so that a greater number of second connection lines 130 electrically connected with the second binding terminals 140 in the second sub-area 1023b can be arranged. Therefore, on the premise that the width of the non-display area NA is not increased, the number of the second connecting lines 130 can be increased, and narrow-frame design is facilitated.
Specifically, the length and the width of the second binding terminal 140 determine the area of the second binding terminal 140, and the electrical conductivity between the second connection line 130 and the external connection line of the array substrate 100 is related to the area of the second binding terminal 140. In the first direction, the lengths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c in the second direction are greater than the lengths of the second binding terminals 140 in the second sub-area 1023b, which results in a smaller area of the second binding terminals 140 in the second sub-area 1023b, so that the conductivity between part of the second connection lines 110 and the external connection lines of the array substrate 100 is poor, and the signal transmission between the second connection lines 110 and the external connection lines of the array substrate 100 is affected. By setting the widths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c in the first direction to be smaller than the width of the second binding terminals 140 in the second sub-area 1023b in the first direction, the influence of the reduction of the lengths of the second binding terminals 140 in the second direction in the second sub-area 1023b on the area of the second binding terminals 140 can be compensated, and good conductivity between the second connection lines 130 and the connection lines outside the array substrate 100 can be ensured.
Alternatively, with continued reference to fig. 2, in the first direction, the lengths of the plurality of second binding terminals 140 in the binding region 102 gradually increase from the center to both sides, and the widths of the plurality of second binding terminals 140 gradually decrease from the center to both sides.
Illustratively, as shown in fig. 2, the inclination angle between the second connection line 130 and the second direction in the fan-out area 101 gradually decreases from the center to both sides along the first direction, and thus, the length of the space occupied by the second connection line 130 in the second direction gradually decreases along the first direction. By setting the lengths of the plurality of second binding terminals 140 in the binding region 102 in the second direction to gradually increase from the center to both sides along the first direction, a sufficient setting space can be left for the second connection lines 140.
Optionally, with continued reference to fig. 2, the lengths of the plurality of second connecting lines 140 in the fan-out area 101 gradually decrease from the center to both sides along the first direction.
Illustratively, as shown in fig. 2, along the first direction, the lengths of the plurality of second binding terminals 140 in the binding region 102 in the second direction gradually increase from the center to two sides, and the lengths of the orthographic projections of the second connection lines 130 in the second direction gradually decrease from the center to two sides so as to ensure the electrical connection between the second connection lines 130 and the second binding terminals 140. In the first direction, the inclination angle between the second connection line 130 and the second direction gradually decreases from the center to both sides, the length of the second connection line 130 is in a proportional relationship with the length of the orthographic projection of the second connection line 130 in the second direction, and is in a proportional relationship with the inclination angle between the second connection line 130 and the second direction, and therefore, the lengths of the plurality of second connection lines 130 in the fan-out area 101 gradually decrease from the center to both sides.
Optionally, with continued reference to fig. 2, the areas of the second binding terminals 140 in the binding region 102 are equal.
Specifically, the area of the second binding terminal 140 determines the contact area of the second connection line 130 electrically connected to the external connection line of the array substrate 100, and the difference in the area of each second binding terminal 140 in the binding region 102 may cause the difference in the conductivity of each second connection line 130 and the external connection line of the array substrate 100. By setting the areas of the second binding terminals 140 in the binding regions 102 to be equal, the conductive performance of the second connection lines 130 can be ensured to be the same as that of the external connection lines of the array substrate 100.
Optionally, with continued reference to fig. 1 and 2, the area of the first binding terminal 120 in the binding region 102 is equal to the area of the second binding terminal 140.
Specifically, the area of the first binding terminal 120 determines the contact area of the first connecting line 110 electrically connected to the external connecting line of the array substrate 100, the area of the second binding terminal 140 determines the contact area of the second connecting line 130 electrically connected to the external connecting line of the array substrate 100, and the difference between the areas of the first binding terminal 120 and the second binding terminal 140 in the binding region 102 results in the difference between the conductivity of the first connecting line 110 and the conductivity of the second connecting line 130 and the conductivity of the external connecting line of the array substrate 100. By setting the area of each first binding terminal 120 and the area of the second binding terminal 140 in the binding region 102 to be equal, the conductive performance of the first connection line 110 and the external connection line of the array substrate 100 can be ensured to be the same as the conductive performance of the first connection line 110 and the external connection line of the array substrate 100.
Based on the same inventive concept, embodiments of the present invention further provide a display panel, including any one of the array substrates provided in the above embodiments.
Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 1 and fig. 3, the display panel 200 includes an array substrate 100 and a flip chip 210.
The chip on film 210 includes a base film layer 211 and a plurality of first leads 212 disposed on the base film layer 211; the first leads 212 are electrically connected to the first binding terminals 120 in a one-to-one correspondence, and the first leads 212 are arranged in a first direction.
Along the first direction, the chip on film 210 includes a first portion 2101 and/or a second portion 2102 and a third portion 2103, the first portion 2101 and the second portion 2102 are located at opposite sides of the third portion 2103, and a plurality of first leads 212 are located at the first portion 2101 and/or the second portion 2102.
Along a first direction, the lengths of the first leads 212 in the chip on film 210 gradually decrease from the center to two sides, and the length direction of the first leads 212 is perpendicular to the first direction.
Illustratively, as shown in fig. 1 and 3, the chip on film 210 includes a first portion 2101, a second portion 2102, and a third portion 2103, the first portion 2101 and the second portion 2102 are located at two opposite sides of the third portion 2103, a plurality of first leads 212 are located at the first portion 2101 and the second portion 2102, the first leads 212 in the first portion 2101 are electrically connected to the first connection lines 110 through the first binding terminals 120 in the first region 1021 in a one-to-one correspondence manner, and the first leads 212 in the second portion 2102 are electrically connected to the first connection lines 110 through the first binding terminals 120 in the second region 1022 in a one-to-one correspondence manner. Along the first direction, the lengths of the plurality of first binding terminals 120 in the binding region 102 in the second direction gradually decrease from the center to two sides, and the second direction is perpendicular to the first direction, when the first lead 212 completely covers the first binding terminals 120, as the length of the first lead 212 in the second direction continues to increase, the contact area when the first lead 212 is electrically connected with the first connecting line 110 does not change, which does not have a great influence on the conductivity of the first lead 212 and the first connecting line 110, but may cause a line short circuit due to the overlong first lead 212. Therefore, according to the lengths of the plurality of first bonding terminals 120 in the bonding region 102 in the second direction, the lengths of the plurality of first leads 212 in the flip-chip film 210 in the second direction are set to be gradually reduced from the center to two sides along the first direction, so that the electrical conductivity between the first leads 212 and the first connecting lines 110 can be ensured, and the problem of line short circuit caused by the overlong first leads 212 can be avoided. In other embodiments, the flip-chip 210 may further include a first portion 2101 and a third portion 2103 along the first direction, and the plurality of first leads 212 are located on the first portion 2101; alternatively, in the first direction, the flip-chip 210 includes a second portion 2102 and a third portion 2103, and the plurality of first leads 212 are disposed on the second portion 2102.
Optionally, fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 4, the length of the first lead 212 is equal to the length of the base film layer 211 corresponding to the first lead 212.
For example, as shown in fig. 4, along the first direction, the lengths of the plurality of first leads 212 in the chip on film 210 in the second direction gradually decrease from the center to two sides, and the length of the base film layer 211 in the second direction also gradually decreases from the center to two sides, so that the length of each first lead 212 in the second direction is equal to the length of the area, on the base film layer 211, where the first lead 212 is disposed, in the second direction, which can avoid the disposing of the unnecessary base film layer 211, and save raw materials.
Optionally, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 2 and fig. 5, the fan-out region 101 is provided with a plurality of second connecting lines 130, the bonding region 102 is provided with a plurality of second bonding terminals 140, the second connecting lines 130 and the second bonding terminals 140 are electrically connected in a one-to-one correspondence, and the second bonding terminals 140 are arranged along the first direction.
In the first direction, the third area 1023 includes a first sub-area 1023a, a second sub-area 1023b and a third sub-area 1023c arranged in sequence, and a plurality of second binding terminals 140 are located in the third area 1023.
In the first direction, the lengths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c are greater than the lengths of the second binding terminals 140 in the second sub-area 1023b, the widths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c are less than the widths of the second binding terminals 140 in the second sub-area 1023b, and the length direction of the second binding terminals 140 is perpendicular to the first direction; the width direction of the second binding terminal 140 is parallel to the first direction.
The chip on film 210 further includes a plurality of second leads 213 disposed on the base film layer 211, the second leads 213 are electrically connected to the second bonding terminals 140 in a one-to-one correspondence, and the second leads 213 are arranged along a first direction.
The third portion 2103 includes a first sub-portion 2103a, a second sub-portion 2103b and a third sub-portion 2103c arranged in sequence along the first direction, and the plurality of second leads 213 are located in the third portion 2103.
The lengths of the second wires 213 in the first sub-portion 2103a and the third sub-portion 2103c are greater than the length of the second wires 213 in the second sub-portion 2103b along the first direction, and the length direction of the second wires 213 is perpendicular to the first direction.
Illustratively, as shown in fig. 2 and 5, the fan-out area 101 is provided with a plurality of second connection lines 130, the bonding area 102 is provided with a plurality of second bonding terminals 140, the second connection lines 130 are electrically connected with the second lead wires 213 in the first sub-portion 2103a in a one-to-one correspondence through the second bonding terminals 140 in the first sub-portion 1023a, the second connection lines 130 are also electrically connected with the second lead wires 213 in the second sub-portion 2103b in a one-to-one correspondence through the second bonding terminals 140 in the second sub-portion 1023b, and the second connection lines 130 are also electrically connected with the second lead wires 213 in the third sub-portion 2103c in a one-to-one correspondence through the second bonding terminals 140 in the third sub-portion 1023 c. The lengths of the second binding terminals 140 in the first sub-area 1023a and the third sub-area 1023c in the second direction are both greater than the length of the second binding terminals 140 in the second sub-area 1023b in the second direction, and by setting the length of the second lead wires 213 in the first sub-area 2103a and the third sub-area 2103c in the second direction to be greater than the length of the second lead wires 213 in the second sub-area 2103b along the first direction, the conductive performance of the second lead wires 213 and the second connecting wires 130 can be ensured, and the problem of line short circuit caused by the overlong second lead wires 213 can be avoided.
Alternatively, with continued reference to fig. 2 and 5, in the first direction, the lengths of the plurality of second binding terminals 140 in the binding region 102 gradually increase from the center to both sides, and the widths of the plurality of second binding terminals 140 gradually decrease from the center to both sides.
In the first direction, the lengths of the second leads 213 in the chip on film 210 gradually increase from the center to the two sides.
Illustratively, as shown in fig. 2 and 5, the second connection lines 130 are electrically connected to the second leads 213 through the second binding terminals 140 in a one-to-one correspondence. Along the first direction, the lengths of the plurality of second bonding terminals 140 in the bonding region 102 in the second direction gradually increase from the center to the two sides, and the lengths of the plurality of second leads 213 in the second direction in the flip chip 210 gradually increase from the center to the two sides along the first direction, so that the conductivity of the second leads 213 and the second connection line 130 can be ensured, and the problem of line short circuit caused by the overlong second leads 213 can be avoided.
Optionally, continuing with fig. 6, which is a schematic structural diagram of another display panel provided in the embodiment of the present invention, as shown in fig. 6, the length of the second lead 213 is equal to the length of the base film layer 211 corresponding to the second lead 213.
For example, as shown in fig. 6, in the first direction, the length of the second lead wire 213 in the first sub-portion 2103a and the third sub-portion 2103c in the second direction is greater than the length of the second lead wire 213 in the second sub-portion 2103b in the second direction, and the length of the base film layer 211 of the first sub-portion 2103a in the second direction and the length of the base film layer 211 of the third sub-portion 2103c in the second direction are both greater than the length of the base film layer 211 of the second sub-portion 2103b in the second direction, so that the length of each second lead wire 213 in the second direction is equal to the length of the base film layer 211 in the second direction in the region where the strip of second lead wire 213 is disposed, which can avoid disposing an unnecessary base film layer 211, and save raw materials.
Based on the same inventive concept, embodiments of the present invention further provide a display device, including any one of the display panels provided in the above embodiments.
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 7, a display device 300 includes a display panel 200.
The display device 300 according to the embodiment of the present invention has the advantages of the display panel 200 according to the above embodiments, and the description thereof is omitted here. In a specific implementation, the display device 300 may be a mobile phone, a tablet computer, a notebook computer, or any product or component with a display function, such as a television, a digital photo frame, a navigator, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
Optionally, fig. 8 is a schematic diagram of a partial enlarged structure of a display device according to an embodiment of the present invention, as shown in fig. 8, the display device further includes a first chip 310 and a second chip 320, the first chip 310 is used for driving the display panel 200 to perform image display and driving the display panel 200 to perform touch control, and the second chip 320 is used for driving the display panel 200 to perform fingerprint identification.
For example, as shown in fig. 8, the first chip 310 is electrically connected to the display panel 200, the second chip 320 is capable of providing a frame display driving signal to the display panel 200 to drive the display panel 200 to display a frame, and the second chip 320 is also capable of providing a touch driving signal to the display panel 200 to drive the display panel 200 to perform touch control. The second chip is also electrically connected to the display panel 200, and the second chip 320 can provide a fingerprint identification driving signal to the display panel 200 to drive the display panel 200 for fingerprint identification. In the embodiment of the invention, the image display driving function and the touch function are integrated in the same chip, so that the number of chips in the display device 300 can be reduced, the space occupied by the chips in the non-display area is reduced, and the narrow frame design is facilitated.
Optionally, fig. 9 is a schematic diagram of a partial enlarged structure of another display device according to an embodiment of the present invention, and as shown in fig. 9, the display device 300 includes a display panel 200, and further includes a third chip 330, where the third chip 330 is used to drive the display panel 200 to perform image display, drive the display panel 200 to perform touch control, and further drive the display panel 200 to perform fingerprint identification.
For example, as shown in fig. 9, the third chip 330 is electrically connected to the display panel 200, the third chip 330 can provide a picture display driving signal to the display panel 200 to drive the display panel 200 to display a picture, the third chip 330 can also provide a touch driving signal to the display panel 200 to drive the display panel 200 to touch, and the third chip 330 can also provide a fingerprint identification driving signal to the display panel 200 to drive the display panel 200 to perform fingerprint identification. At least part of signal lines of the display device 300 during picture display can be multiplexed into signal lines during fingerprint identification, so that the number of wiring lines in the display device 300 can be reduced; in addition, the image display driving function, the touch function and the fingerprint identification function are integrated in the same chip, so that the number of chips in the display device 300 can be reduced, the space occupied by the chips in a non-display area is reduced, and the narrow-frame design is facilitated.
The foregoing is considered as illustrative of the preferred embodiments of the invention and technical principles employed. The present invention is not limited to the specific embodiments herein, and it will be apparent to those skilled in the art that various changes, rearrangements, and substitutions can be made without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the claims.
Claims (17)
1. An array substrate, comprising: the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a fan-out area and a binding area;
the fan-out area is positioned between the binding area and the display area;
the fan-out area is provided with a plurality of first connecting lines; the binding region is provided with a plurality of first binding terminals; the first connecting wires are electrically connected with the first binding terminals in a one-to-one correspondence manner; the first binding terminals are arranged along a first direction;
along the first direction, the binding region comprises a first region and/or a second region and a third region, and the first region and the second region are positioned at two opposite sides of the third region; a plurality of the first binding terminals are located in the first region and/or the second region;
in the first direction, the lengths of the first binding terminals in the binding region gradually decrease from the center to two sides, and the widths of the first binding terminals gradually increase from the center to two sides; the length direction of the first binding terminal is perpendicular to the first direction, and the width direction of the first binding terminal is parallel to the first direction.
2. The array substrate of claim 1, wherein along the first direction, lengths of the plurality of first connection lines in the fan-out area gradually increase from a center to two sides.
3. The array substrate of claim 1, wherein the first binding terminals in the binding region have equal areas.
4. The array substrate as claimed in claim 1, wherein the fan-out area is provided with a plurality of second connecting lines; the binding region is provided with a plurality of second binding terminals; the second connecting wires are electrically connected with the second binding terminals in a one-to-one correspondence manner; the second binding terminals are arranged along the first direction;
along the first direction, the third region comprises a first sub-region, a second sub-region and a third sub-region which are sequentially arranged; a plurality of the second binding terminals are located at the third region;
in the first direction, the lengths of the second binding terminals in the first and third sub-regions are both greater than the length of the second binding terminal in the second sub-region; the widths of the second binding terminals in the first and third sub-regions are both smaller than the width of the second binding terminals in the second sub-region; the length direction of the second binding terminal is perpendicular to the first direction; the width direction of the second binding terminal is parallel to the first direction.
5. The array substrate of claim 4, wherein along the first direction, the lengths of the second binding terminals in the binding region gradually increase from the center to two sides, and the widths of the second binding terminals gradually decrease from the center to two sides.
6. The array substrate of claim 5, wherein the lengths of the plurality of second connecting lines in the fan-out region gradually decrease from the center to two sides along the first direction.
7. The array substrate of claim 4, wherein the area of each of the second bonding terminals in the bonding region is equal.
8. The array substrate of claim 4, wherein the area of the first binding terminal in the binding region is equal to the area of the second binding terminal.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. The display panel according to claim 9, wherein the display panel further comprises a flip-chip film;
the chip on film comprises a base film layer and a plurality of first leads arranged on the base film layer; the first leads are electrically connected with the first binding terminals in a one-to-one correspondence manner; the first leads are arranged along the first direction;
along the first direction, the chip on film comprises a first part and/or a second part and a third part, and the first part and the second part are positioned at two opposite sides of the third part; a plurality of the first leads are located at the first portion and/or the second portion;
along the first direction, the lengths of the first leads in the chip on film are gradually reduced from the center to two sides; the length direction of the first lead is perpendicular to the first direction.
11. The display panel according to claim 10, wherein a length of the first lead line is equal to a length of the base film layer corresponding to the first lead line.
12. The display panel according to claim 10, wherein the fan-out area is provided with a plurality of second connection lines; the binding region is provided with a plurality of second binding terminals; the second connecting wires are electrically connected with the second binding terminals in a one-to-one correspondence manner; the second binding terminals are arranged along the first direction;
along the first direction, the third region comprises a first sub-region, a second sub-region and a third sub-region which are sequentially arranged; a plurality of the second binding terminals are located at the third region;
in the first direction, the lengths of the second binding terminals in the first and third sub-regions are both greater than the length of the second binding terminal in the second sub-region; the widths of the second binding terminals in the first and third sub-regions are both smaller than the width of the second binding terminals in the second sub-region; the length direction of the second binding terminal is perpendicular to the first direction; a width direction of the second binding terminal is parallel to the first direction;
the chip on film also comprises a plurality of second leads arranged on the base film layer; the second leads are electrically connected with the second binding terminals in a one-to-one correspondence manner; the second leads are arranged along the first direction;
the third part comprises a first sub-part, a second sub-part and a third sub-part which are arranged in sequence along the first direction; a plurality of the second leads are located at the third portion;
the length of the second lead in the first sub-portion and the third sub-portion is greater than the length of the second lead in the second sub-portion along the first direction, and the length direction of the second lead is perpendicular to the first direction.
13. The display panel according to claim 12, wherein in the first direction, lengths of the second binding terminals in the binding region gradually increase from a center to both sides, and widths of the second binding terminals gradually decrease from the center to both sides;
along the first direction, the lengths of the second leads in the chip on film gradually increase from the center to two sides.
14. The display panel according to claim 12, wherein the length of the second lead line is equal to the length of the base film layer corresponding to the second lead line.
15. A display device characterized by comprising the display panel according to any one of claims 9 to 14.
16. The display device according to claim 15, further comprising: a first chip and a second chip;
the first chip is used for driving the display panel to display pictures and driving the display panel to perform touch control; the second chip is used for driving the display panel to perform fingerprint identification.
17. The display device according to claim 15, further comprising a third chip;
the third chip is used for driving the display panel to display pictures, driving the display panel to perform touch control, and driving the display panel to perform fingerprint identification.
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| CN202011066201.3A CN112133201B (en) | 2020-09-30 | 2020-09-30 | Array substrate, display panel and display device |
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| CN202011066201.3A CN112133201B (en) | 2020-09-30 | 2020-09-30 | Array substrate, display panel and display device |
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