CN112119366A

CN112119366A - Time synchronization method, device and system and movable platform

Info

Publication number: CN112119366A
Application number: CN201980031709.9A
Authority: CN
Inventors: 高明明; 杨康; 唐彦琴
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2020-12-22
Also published as: WO2021081806A1

Abstract

A method, a device, a system and a movable platform for time synchronization among a plurality of chips. The plurality of chips comprise a main chip and at least one auxiliary chip, the main chip is connected with each auxiliary chip in the at least one auxiliary chip through a single bus, and the method comprises the following steps: the main chip is communicated with the at least one auxiliary chip through the single bus according to a preset arrangement sequence; the at least one auxiliary chip performs time synchronization operations according to information obtained in communication with the main chip. The method, the device and the system for time synchronization among the chips and the movable platform provided by the embodiment of the application can realize the time synchronization among the chips.

Description

Time synchronization method, device and system and movable platform

Copyright declaration

The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.

Technical Field

The present application relates to the field of data processing, and in particular, to a method, an apparatus, a system, and a movable platform for time synchronization among multiple chips.

Background

The application scenarios of machine vision are increasingly wide, and in order to ensure stable operation and accurate control, the types and the number of sensors used are increasingly large, and the sensors mainly include cameras (cameras), laser radars, millimeter wave radars, Inertial Measurement Units (IMUs), and the like. According to different applications, some systems use a plurality of cameras and radars to monitor a 360-degree field of view, data fusion of data sampled by a plurality of sensors is needed in an algorithm, and in the fusion process, the data sampling time of each sensor is very important; in addition, since there are many sensor components, in order to reduce the complexity of installation and maintenance and not reduce the stability of the system, the system usually requires fewer wired connections as well, so the problem of time stamp synchronization of multiple chips needs to be solved based on the above two points.

Disclosure of Invention

The application provides a time synchronization method, a time synchronization device, a time synchronization system and a movable platform, which can realize time synchronization among a plurality of chips.

In a first aspect, a method for time synchronization among a plurality of chips is provided, where the plurality of chips includes a main chip and at least one auxiliary chip, the main chip is connected to each of the at least one auxiliary chip through a single bus, and the method includes: the main chip is communicated with the at least one auxiliary chip through the single bus according to a preset arrangement sequence; the at least one auxiliary chip performs time synchronization operations according to information obtained in communication with the main chip.

In a second aspect, a method for time synchronization among a plurality of chips including a main chip and at least one auxiliary chip, the main chip being connected to each of the at least one auxiliary chip through a single bus, the method comprising: the main chip is communicated with the at least one auxiliary chip through the single bus according to a preset arrangement sequence, so that the time of the chips is synchronized.

By the technical scheme, the single bus is used for connecting the multiple chips, so that connecting wires among the chips and between the chips and the sensor assembly can be saved; in addition, a main chip and at least one auxiliary chip are arranged in the plurality of chips, the main chip is respectively communicated with the at least one auxiliary chip according to a preset arrangement sequence in a time multiplexing mode, so that the at least one auxiliary chip can carry out time synchronization according to information obtained in communication.

In a third aspect, a time synchronization apparatus is provided, where the time synchronization apparatus is connected to multiple chips through a single bus, and the time synchronization apparatus is configured to communicate with multiple auxiliary chips according to a preset arrangement order, so as to synchronize the time of the multiple chips.

In a fourth aspect, a time synchronization system is provided, which includes a plurality of chips, where the plurality of chips includes a main chip and at least one auxiliary chip, the main chip is connected to each of the at least one auxiliary chip through a single bus, and the main chip is configured to communicate with the at least one auxiliary chip through the single bus according to a preset arrangement order; the auxiliary chip is used for executing time synchronization operation according to the information acquired in the communication between the auxiliary chip and the main chip.

In a fifth aspect, there is provided a movable platform comprising: a body; the power system is arranged on the machine body and used for providing power for the movable platform; a time synchronization system of the first aspect or any possible implementation manner of the first aspect.

Drawings

Fig. 1 is a schematic flow chart of a method for time synchronization between a plurality of chips according to an embodiment of the present application.

Fig. 2 is a schematic diagram of an application scenario of a time synchronization method for multiple chips according to an embodiment of the present application.

FIG. 3 is a schematic block diagram of a plurality of chips of an embodiment of the present application.

FIG. 4 is another schematic block diagram of a plurality of chips of an embodiment of the present application.

Fig. 5 is a timing diagram illustrating communication between the main chip and the auxiliary chip according to an embodiment of the present application.

Fig. 6 is another timing diagram of communication between the main chip and the auxiliary chip according to the embodiment of the present application.

Fig. 7 is a schematic diagram of communication between a main chip and a first auxiliary chip according to an embodiment of the present application.

FIG. 8 is a schematic block diagram of a movable platform of an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In the prior art, software is generally considered to be used to implement a function of time stamp synchronization of multiple chips, for example, a Controller Area Network (CAN) bus may be used, but in the implementation process of software, communication between chips is involved, communication involves processing of interrupts, and interrupts have priority, which causes great jitter in the processing process of software; and, if a single bus scheme is adopted, the delay jitter is greater.

In addition, if a multi-bus connection mode is adopted among a plurality of chips, if the number of sensor assemblies is large, the number of connecting wires is large, and installation and maintenance are relatively complex.

Therefore, embodiments of the present application provide a time synchronization method for multiple chips, which can solve the above problems.

Fig. 1 shows a schematic flow chart of a method 100 for time synchronization between multiple chips according to an embodiment of the present application. The method 100 of the embodiment of the present application is suitable for application scenarios of multiple chips, where the multiple chips may be connected by a single bus, and the number of the multiple chips may be set according to actual applications. Specifically, fig. 2 shows a schematic diagram of an application scenario of an embodiment of the present application, as shown in fig. 2, the application scenario is referred to as a sensor system, and three chips are taken as an example for explanation and referred to as an Integrated Circuit (IC) IC0, an IC1, and an IC2, respectively;

the "camera (camera)" in fig. 2 may represent an image pickup sensor, here taking camera as an example, and the camera in one block in fig. 2 may represent one or a group of cameras, for example, the camera in each block may represent a group of cameras including 8 cameras; the "lidar" in fig. 2 is similar to camera and illustrates that the sensor connected to the chip may be a variety of types of sensors.

Assuming that the sensor system of fig. 2 is mounted on a motion system that can achieve fine control, such as path planning, for application to robotic navigation, it can be seen that in the system shown in fig. 2, there are multiple relatively independent processors (e.g., IC0, IC1, and IC 2); moreover, working clocks between chips may have deviation, so that the power-on and reset time of the system cannot be absolutely the same; the software initialization moments are completely different, if the IC systems are completely independent, the accumulated error is larger and larger after long-time work, so that the sampling time of each sensor is completely different, no correlation exists, and even control failure can be caused.

Therefore, the embodiment of the present application proposes a method 100 for time synchronization between multiple chips, which is applied to a system including multiple chips, for example, the method can be used in the sensor system shown in fig. 2, and the multiple chips can be connected to each other through a single bus.

Specifically, fig. 3 shows a schematic block diagram of a plurality of chips according to an embodiment of the present application, and as shown in fig. 3, the method 100 according to an embodiment of the present application is applied to a scenario including a plurality of chips, which may be regarded as a time synchronization system, the system including a plurality of chips, the plurality of chips including a main chip 210 and at least one auxiliary chip 220, the main chip 210 being connected to each of the at least one auxiliary chip 220 through a single bus. It should be understood that the at least one auxiliary chip 220 may refer to one or more auxiliary chips, and the embodiment of the present application is not limited thereto, and is illustrated in fig. 3 by including 3 auxiliary chips, which are respectively denoted as an auxiliary chip 221, an auxiliary chip 222, and an auxiliary chip 223.

As shown in fig. 1, the method 100 includes: s110, the main chip communicates with the at least one auxiliary chip respectively according to a preset arrangement sequence through the single bus; and S120, the at least one auxiliary chip executes time synchronization operation according to the information acquired in the communication with the main chip.

It should be understood that the plurality of chips in the embodiments of the present application may include one or more types of chips, that is, the types of the plurality of chips may be the same or different. For example, the plurality of chips may include at least one of the following types: a Digital Signal Processor (DSP) chip, a radar chip, or a vision chip, but the embodiment of the present application is not limited thereto.

The master chip in the embodiment of the present application may be any one of the plurality of chips. For example, the main chip 210 shown in fig. 3 may correspond to any one of the three chips IC0, IC1, and IC2 in fig. 2, and the remaining two chips are auxiliary chips.

Specifically, the method 100 may further include: a master chip is determined among the plurality of chips. There are many ways to determine the main chip among the plurality of chips, and the following description will be given by taking the example of determining the first chip among the plurality of chips as the main chip in conjunction with several specific embodiments, where the first chip may be any one of the plurality of chips.

For example, the determining the first chip of the plurality of chips as the master chip may include: and if the chip corresponding to the preset identifier in the plurality of chips is the first chip, determining the first chip as the main chip. Specifically, there may be software communication between chips, such as using an Inter-Integrated Circuit (ic) bus or a CAN bus, and the main chip may be determined by way of system power-on initialization and an Identifier (ID) for identifying hardware by software. For example, ic identifies different devices by different IDs, and may default to a certain ID in the program, that is, a preset identifier, so that the chip corresponding to the ID is the primary chip, and the other chips are the secondary chips.

For another example, the determining the first chip of the plurality of chips as the master chip may further include: the multiple chips receive indication information sent by target equipment, the indication information indicates that a first chip in the multiple chips is the main chip, and the target equipment is connected with the multiple chips; and determining a first chip in the plurality of chips as the main chip according to the indication information. In particular, the plurality of chips may communicate with any target device, the master chip being designated by the target device. For example, multiple ICs communicate with a third party IC, such that the third party IC can designate a chip as a primary chip and other chips as secondary chips.

For another example, the determination that the first chip of the plurality of chips is the primary chip may also be determined in a manner that firmware is programmed by software and automatically specified, for example, as shown in fig. 2, the IC0 may be automatically specified as the primary chip and the other chips may be specified as the secondary chips when firmware is programmed.

Optionally, assuming that after the first chip of the plurality of chips is determined as the master chip, the current master chip fails, that is, the first chip fails, the method 100 further includes: changing the main chip from the first chip to a second chip of the plurality of chips. Specifically, the second chip may be any one of the plurality of chips except the first chip, so that in the case where the current main chip fails, another chip may be selected as the main chip. For example, the method may be similar to the possible method of selecting the first chip as the main chip, that is, a method of preset identifier indication may also be adopted, a method specified by a target device of a third party may also be adopted, or a method automatically specified by software programming firmware may also be adopted, and details are not repeated herein for brevity.

In the embodiment of the application, the main chip is connected with each auxiliary chip through the single bus, the single bus solves the communication problem among a plurality of chips, and all related components are connected. For any one of the auxiliary chips, the main chip may be directly connected to the auxiliary chip through a single bus, for example, as shown in fig. 2, if the main chip is IC0, the auxiliary chips are IC1 and IC2, and IC0 is connected to IC1 and IC2 through a single bus.

Alternatively, for long-distance transmission, the main chip may be connected to one or more intermediate devices via the single bus, and the intermediate devices may be connected to some auxiliary chip via the single bus. Fig. 4 shows another schematic block diagram of a plurality of chips according to an embodiment of the present application, and assuming that the main chip is IC0, the auxiliary chips are IC1 and IC2, and as shown in fig. 4, the IC0 is connected to the intermediate device a through a single bus, the intermediate device a is connected to two intermediate devices B through a single bus, and the two intermediate devices B are connected to the IC1 and the IC2 through single buses, respectively. Optionally, the intermediate device in the embodiment of the present application may be a relay, or may also be another device; and in the case that a plurality of intermediate devices are included, the plurality of intermediate devices may be the same device or different devices, and the embodiment of the present application is not limited thereto.

As shown in fig. 1 and fig. 3, in S110 of the method 100, the main chip 210 communicates with the at least one auxiliary chip 220 through the single bus according to a preset sequence, that is, the main chip communicates with the auxiliary chips one by one in a time division multiplexing manner. Correspondingly, before the S110, the method 100 further includes: the preset arrangement order of the at least one sub chip 220 is determined. Specifically, the main chip 210 determines the preset arranging order for communicating with the at least one auxiliary chip 220; the main chip 210 sends the preset arranging order to the at least one auxiliary chip 220 through the single bus, for example, the main chip 210 may broadcast the preset arranging order to the at least one auxiliary chip 220 in a broadcasting manner.

It should be understood that the determining, by the primary chip 210, the preset ordering for communicating with the at least one secondary chip 220 may include: the main chip 210 determines a number for each auxiliary chip, where the number may indicate the sequence of each auxiliary chip, that is, the main chip may communicate with each auxiliary chip in sequence according to the sequence of the numbers. For example, assuming that the numbering starts with 1, the slave chip numbered 1 represents: the main chip firstly communicates with the auxiliary chip with the number 1; the slave chip numbered 2 represents: the master chip will communicate with the slave chip numbered 2 a second time, and so on.

For convenience of illustration, any two of the at least one secondary chip are taken as an example here, and they are referred to as a first secondary chip and a second secondary chip, and if the first secondary chip is located before the second secondary chip in the preset arrangement order, the S110 may specifically include: during a first time period, the main chip communicates with the first auxiliary chip through the single bus; and in a second time period, the main chip communicates with the second auxiliary chip through the single bus, wherein the first time period is before the second time period, and the first time period is not overlapped with the second time period.

Optionally, the time for the main chip to communicate with each auxiliary chip may be equal or unequal, that is, the first time period may be equal to or unequal to the second time period; in addition, the length of the time for the main chip to communicate with each auxiliary chip can be set according to practical application, that is, the length of the first time period or the length of the second time period can be set according to practical situations and can be set to any value. For example, the time for the main chip to communicate with each of the secondary chips may be set to 5ms, i.e., the length of the first time period equal to the second time period is equal to 5 ms.

In the embodiment of the present application, the communication time periods of the main chip 210 and the at least one auxiliary chip 220 are not overlapped, that is, the first time period and the second time period are not overlapped. For example, if the first auxiliary chip is adjacent to the second auxiliary chip in the preset arrangement sequence, that is, one chip after the first auxiliary chip is the second auxiliary chip, and there is no other auxiliary chip between the first auxiliary chip and the second auxiliary chip, the time interval between the end time of the first time period and the start time of the second time period may be equal to or greater than zero; if the time interval is greater than zero, the primary chip does not communicate with the at least one secondary chip during the time interval, e.g., the primary chip may be in an idle state or the primary chip may also handle other traffic.

In this embodiment, the main chip 210 communicates with the at least one auxiliary chip 220 according to a preset sequence in S110, and correspondingly, in S120, the at least one auxiliary chip 220 may perform a time synchronization operation according to information obtained in the communication with the main chip 210, so as to achieve a time synchronization target among the plurality of chips.

The manner in which the method 100 of the embodiments of the present application uses time division multiplexing will be described in detail below with reference to the accompanying drawings.

Fig. 5 and fig. 6 respectively show schematic diagrams of communication between a main chip and an auxiliary chip in the embodiment of the present application in different manners, taking the main chip 210 and 3 auxiliary chips in fig. 3 as an example, and assuming that a preset arrangement order of the three auxiliary chips is: the secondary chip 221 is the first, the secondary chip 222 is the second, and the secondary chip 223 is the third. In addition, taking a period as an example, the period is divided into 8 time lengths of 5ms according to the number of the slave chips.

As shown in fig. 5 and fig. 6, in the first 5ms duration of the period, the main chip 210 sends a preset arranging sequence to each of the auxiliary chips, for example, the main chip 210 may send (tx) the preset arranging sequence to 3 auxiliary chips in a broadcast manner, and correspondingly, three auxiliary chips receive the preset arranging sequence.

Alternatively, during the first period of 5ms, the actual communication time may only occupy a part of the period, and the actual communication part may be located at any position, wherein the actual communication time may include the preset arranging sequence broadcast-transmitted by the main chip 210, and the preset arranging sequence received by the three auxiliary chips. For example, the total duration of the actual communication may be 0.6ms, the actual communication of 0.6ms may occur anywhere in the first 5ms duration range, and in the 5ms duration range, at times other than 0.6ms, no communication is performed between the primary chip and the secondary chip, for example, they may both be in an idle state, but the embodiment of the present application is not limited thereto.

As shown in FIGS. 5 and 6, during the second 5ms of the cycle, no communication is made between the primary chip 210 and the three secondary chips, which may all be in an idle state, for example.

As shown in fig. 5 and fig. 6, during the third 5ms duration of the period, the main chip 210 first communicates with the auxiliary chip 221 according to the preset ordering, so that the auxiliary chip 221 performs time synchronization according to the information obtained by communication.

Alternatively, in the third 5ms period, the actual communication time may be less than 5ms, that is, the actual communication time may only occupy a portion thereof, for example, the actual communication time may be 2ms, then the 2ms actual communication may occur at any position in the first 5ms duration range, and in the 5ms duration range, the master chip and the slave chip do not communicate for a time other than 2ms, for example, they may both be in an idle state, but the embodiment of the present application is not limited thereto.

As shown in FIGS. 5 and 6, during the fourth 5ms duration of the cycle, similar to the second 5ms duration, no communication is made between the primary chip 210 and the three secondary chips, which may each be in an idle state, for example.

As shown in fig. 5 and fig. 6, in the fifth 5ms duration of the period, the main chip 210 communicates with the auxiliary chip 222 according to the preset arrangement sequence, so that the auxiliary chip 222 performs time synchronization according to the information obtained by communication. This process is similar to the third 5ms duration and is not described here for brevity.

As shown in FIGS. 5 and 6, during the sixth 5ms duration of the cycle, similar to the second and fourth 5ms durations, no communication is made between the primary chip 210 and the three secondary chips, which may all be in an idle state, for example.

As shown in fig. 5 and fig. 6, in the seventh 5ms duration of the period, the main chip 210 communicates with the auxiliary chip 223 according to the preset arrangement sequence, so that the auxiliary chip 223 performs time synchronization according to the information obtained by communication. This process is similar to the third 5ms duration and is not described here for brevity.

As shown in fig. 5 and 6, during the eighth 5ms duration of the cycle, similar to the second, fourth, and sixth 5ms durations, no communication is made between the primary chip 210 and the three secondary chips, e.g., they may all be in an idle state.

After the 8 5ms time periods are finished, that is, after one period is finished, the main chip 210 completes communication with all the slave chips, so that each slave chip can perform time synchronization with the main chip, that is, each slave chip sets time to be synchronized with the main chip, that is, time synchronization of all chips is realized. Such a period similar to fig. 5 and 6 may be performed once or more among a plurality of chips, for example, the period may be cycled among the plurality of chips, and time synchronization may be repeated, so as to achieve the purpose of high-precision time synchronization, but the embodiment of the present application is not limited thereto.

It should be understood that the process of the master chip communicating with any one of the slave chips to time synchronize the slave chip with the master chip may be performed in various ways. For convenience of illustration, the main chip communicates with the first auxiliary chip in the first time period, for example, the first auxiliary chip may be the auxiliary chip 221 shown in fig. 3, and correspondingly, the first time period may refer to the third 5ms time shown in fig. 5 and fig. 6; alternatively, the first secondary chip may be the secondary chip 222 shown in fig. 3, and correspondingly, the first time period may refer to the fifth 5ms time shown in fig. 5 and 6; alternatively, the first secondary chip may be the secondary chip 223 as shown in fig. 3, and correspondingly, the first time period may refer to the seventh 5ms time as shown in fig. 5 and 6.

Specifically, in the first time period, the main chip communicates with a first auxiliary chip, and the first auxiliary chip performs time synchronization according to information obtained in communication with the main chip. Wherein performing time synchronization may include: the first secondary chip determines a time difference with the primary chip. After determining the time difference with the main chip, the first auxiliary chip may correspondingly adjust the time of the first auxiliary chip, for example, a clock or a timestamp of the first auxiliary chip may be adjusted so that the time of the first auxiliary chip is the same as that of the main chip; alternatively, after the first slave chip calculates the time difference with the master chip, the clock or the timestamp of the first slave chip may not be adjusted, but when processing data, the time difference is used by the processing, for example, the time difference is cancelled or compensated, so that the time of the first slave chip and the time of the master chip are consistent, and the embodiment of the present invention is not limited thereto.

It should be appreciated that the first secondary chip may determine the time difference with the primary chip in a variety of ways. For example, the first secondary chip and the primary chip adopt a method of 1588 protocol in communication for compensation and offset calculation in a first time period, but the embodiment of the present application is not limited thereto. Specifically, fig. 7 shows a time diagram of communication between the main chip and the first auxiliary chip, as shown in fig. 7, the main chip time represents the time measured by the main chip, and the auxiliary chip time represents the time measured by the first auxiliary chip. In the first time period, the main chip communicates with the first auxiliary chip through the single bus, and may specifically include: during the first time period, the main chip sends a first data packet to the first auxiliary chip through the single bus, and the sending time of the first data packet is a first time t1 of the time of the main chip; the first auxiliary chip receives the first data packet, and the receiving time of the first data packet is a second time t2 of the time of the first auxiliary chip; in the first time period, the first auxiliary chip sends a second data packet to the main chip through the single bus, and the sending time of the second data packet is a third time t3 of the time of the first auxiliary chip; the master chip receives the second data packet, and the receiving time of the second data packet is the fourth time t4 of the master chip time.

It should be understood that the first time t1 is the sending time of the first packet, which is the time of the master chip; the second time t2 is the receiving time of the second data packet, and the receiving time is the time of the first secondary chip; the third time t3 is the sending time of the second data packet, and the sending time is the time of the first auxiliary chip; the fourth time t4 is the time of reception of the second packet, which is the time of the master chip.

Alternatively, the first auxiliary chip may determine a time difference with the main chip according to the first time t1, the second time t2, the third time t3 and the fourth time t 4. Here, the first time t1 and the third time t3 are times of the master chip, and thus, the master chip may transmit the first time t1 and the third time t3 to the first slave chip. For example, the master chip may transmit the first data packet by carrying a timestamp on the first data packet, with the timestamp indicating the first time t 1; or, the master chip may further send another data packet to the first slave chip through the single bus during the first time period, where the data packet includes the first time t1 and/or the third time t 3; alternatively, as shown in fig. 7, the master chip may further send a third data packet and/or a fourth data packet to the first slave chip through the single bus in the first time period, where the third data packet includes the first time t1, and the fourth data packet includes the third time t3, but the embodiment of the present invention is not limited thereto.

It should be understood that, as shown in fig. 7, for the transmission process of the first data packet, the time difference between the first time t1 and the second time t2 is Δ t1, and the Δ t1 includes the transmission time of the first data packet and the time difference between the main chip and the first auxiliary chip; similarly, for the transmission process of the second data packet, the time difference between the third time t3 and the fourth time t4 is Δ t2, and the Δ t2 includes the transmission time of the second data packet and the time difference between the main chip and the first auxiliary chip. Therefore, if the transmission time of the first data packet is equal to that of the second data packet, it can be determined that the time difference Δ t between the first secondary chip and the primary chip can be calculated by the following equation 1:

if the calculated time difference delta t is a positive number, the time of the first auxiliary chip is later than the time of the main chip; if the calculated time difference delta t is a negative number, the time of the first auxiliary chip is earlier than the time of the main chip.

Optionally, in order to ensure the accuracy of determining the time difference between the master chip and the first slave chip, it is assumed that the transmission time of the first data packet is the same as the transmission time of the second data packet; in order to make the transmission time of the first data packet the same as the transmission time of the second data packet, the following arrangements may be considered.

Firstly, the length of the first data packet is set to be equal to the length of the second data packet. For example, the length of a first data packet sent by the master chip to the first slave chip is 15 bytes, and then the length of a second data packet sent by the first slave chip to the master chip is also set to be 15 bytes.

Secondly, the transmission protocol of the first data packet sent by the main chip is consistent with the transmission protocol of the second data packet sent by the first auxiliary chip, or completely equivalent. For example, each using serial baud rate 115200, so that the data interaction between the master chip and the first slave chip is fully equivalent.

And thirdly, the transmission paths for transmitting the first data and the second data between the main chip and the first auxiliary chip are the same, so that the transmission time of the first data packet is the same as that of the second data packet.

Optionally, if the transmission time of the first data packet is different from the transmission time of the second data packet, the time difference between the main chip and the first auxiliary chip may also be determined when the transmission time of the first data packet or the transmission time of the second data packet is known, which is not limited in this embodiment of the present application.

Therefore, according to the time synchronization method for multiple chips in the embodiment of the present application, by connecting multiple chips through a single bus, wires between chips and sensor assemblies can be saved, and if there are multiple wires in a system, the extra physical wires can be used for redundancy design (e.g., a Field Programmable Gate Array (FPGA)); in addition, a main chip and at least one auxiliary chip are arranged in the plurality of chips, the main chip is respectively communicated with the at least one auxiliary chip according to a preset arrangement sequence in a time multiplexing mode, so that the at least one auxiliary chip can carry out time synchronization according to information obtained in communication.

Optionally, the embodiment of the application further provides a movable platform. In particular, fig. 8 shows a schematic block diagram of a movable platform 300 of an embodiment of the present application. As shown in fig. 8, the movable platform 300 includes: a body 310; a power system 320 disposed in the body 310 for providing power to the movable platform 300; the time synchronization system 330 is disposed in the body 310 and can be used for image processing. For example, the time synchronization system 330 may be the time synchronization system shown in fig. 3 according to the embodiment of the present application, and the time synchronization system 330 may include a main chip 210 and at least one auxiliary chip 220, which are not described herein again for brevity. For another example, the time synchronization system 330 may further include an image capturing device for capturing an image; the time synchronization system 330 may also include an image processing device for processing the image. The image acquisition device maliciously comprises shooting equipment (such as a camera, a video camera and the like) or a visual sensor (such as a monocular camera or a dual/multi-view camera and the like).

The movable platform 300 in embodiments of the present invention may refer to any movable device that may move in any suitable environment, such as in the air (e.g., a fixed-wing aircraft, a rotorcraft, or an aircraft without both fixed wings and rotors), in water (e.g., a ship or submarine), on land (e.g., an automobile or train), in space (e.g., a space plane, a satellite, or a probe), and any combination thereof. The mobile device may be an aircraft, such as an Unmanned Aerial Vehicle (UAV).

The body 310 may also be referred to as a fuselage, which may include a central frame and one or more arms coupled to the central frame, the one or more arms extending radially from the central frame. The foot rest is connected with the fuselage and used for supporting when the UAV lands.

The power system 320 may include an electronic governor (abbreviated as an electric governor), one or more propellers, and one or more motors corresponding to the one or more propellers, wherein the motors are connected between the electronic governor and the propellers, and the motors and the propellers are disposed on corresponding arms; the electronic speed regulator is used for receiving a driving signal generated by the flight controller and providing a driving current to the motor according to the driving signal so as to control the rotating speed of the motor. The motor is used to drive the propeller to rotate, thereby providing power for the flight of the UAV, which enables the UAV to achieve motion in one or more degrees of freedom. It should be understood that the motor may be a dc motor or an ac motor. In addition, the motor can be a brushless motor, and can also be a brush motor.

It should be understood that the apparatus of the embodiments of the present application may be implemented based on a memory and a processor, wherein each memory is used for storing instructions for executing the method of the embodiments of the present application, and the processor executes the instructions to make the apparatus execute the method of the embodiments of the present application.

It should be understood that the Processor mentioned in the embodiments of the present Application may be a Central Processing Unit (CPU), and may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory referred to in the embodiments of the application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, the memory (memory module) is integrated in the processor.

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Embodiments of the present application further provide a computer-readable storage medium, on which instructions are stored, and when the instructions are executed on a computer, the instructions cause the computer to execute the method of each of the above method embodiments.

An embodiment of the present application further provides a computing device, which includes the computer-readable storage medium.

The embodiment of the application can be applied to the aircraft, especially the unmanned aerial vehicle field.

It should be understood that the division of circuits, sub-units of the various embodiments of the present application is illustrative only. Those of ordinary skill in the art will appreciate that the various illustrative circuits, sub-circuits, and sub-units described in connection with the embodiments disclosed herein can be split or combined.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., Digital Video Disk (DVD)), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It should be understood that the embodiments of the present application are described with respect to a total bit width of 16 bits (bit), and the embodiments of the present application may be applied to other bit widths.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for time synchronization among a plurality of chips, wherein the plurality of chips includes a main chip and at least one auxiliary chip, the main chip is connected to each of the at least one auxiliary chip through a single bus, the method comprising:

the main chip is communicated with the at least one auxiliary chip through the single bus according to a preset arrangement sequence;

the at least one auxiliary chip performs time synchronization operations according to information obtained in communication with the main chip.

2. The method of claim 1, further comprising:

the main chip determines the preset arrangement sequence for communicating with the at least one auxiliary chip;

and the main chip sends the preset arrangement sequence to the at least one auxiliary chip through the single bus.

3. The method according to claim 1 or 2, wherein the preset arranging order comprises: a first secondary chip of the at least one secondary chip precedes a second secondary chip,

the main chip respectively communicates with the at least one auxiliary chip through the single bus according to a preset arrangement sequence, and the method comprises the following steps:

in a first time period, the main chip communicates with the first auxiliary chip through the single bus;

and in a second time period, the main chip communicates with the second auxiliary chip through the single bus, wherein the first time period is before the second time period, and the first time period is not overlapped with the second time period.

4. The method of claim 3, wherein the at least one secondary chip performs time synchronization operations based on information obtained in communication with the primary chip, comprising:

and in the first time period, the first auxiliary chip determines the time difference with the main chip according to the information acquired in the communication with the main chip.

5. The method of claim 4, further comprising:

and the first auxiliary chip adjusts the time to be synchronous with the time of the main chip according to the time difference.

6. The method of claim 4 or 5, wherein the communicating, by the master chip and the first slave chip via the single bus during the first time period, comprises:

in the first time period, the main chip sends a first data packet to the first auxiliary chip through the single bus, and the sending time of the first data packet is the first time of the main chip;

the first auxiliary chip receives the first data packet, and the receiving time of the first data packet is the second time of the first auxiliary chip;

in the first time period, the first auxiliary chip sends a second data packet to the main chip through the single bus, and the sending time of the second data packet is the third time of the first auxiliary chip;

and the master chip receives the second data packet, and the receiving time of the second data packet is the fourth time of the master chip time.

7. The method of claim 6, wherein the determining, by the first secondary chip, the time difference with the primary chip based on information obtained in the communication with the primary chip comprises:

and the first auxiliary chip determines the time difference with the main chip according to the first time, the second time, the third time and the fourth time.

8. The method according to claim 6 or 7, characterized in that the method further comprises:

and the main chip sends a third data packet and a fourth data packet to the first auxiliary chip through the single bus in the first time period, wherein the third data packet comprises the first moment, and the fourth data packet comprises the third moment.

9. The method of any one of claims 6 to 8, wherein the length of the first packet is equal to the length of the second packet.

10. The method according to any one of claims 6 to 9, wherein the transmission protocol of the first data packet sent by the master chip is identical to the transmission protocol of the second data packet sent by the first slave chip.

11. The method according to any one of claims 6 to 9, wherein the transmission path through which the first data and the second data are transmitted between the primary chip and the first secondary chip is the same.

12. The method according to any one of claims 3 to 11, wherein the duration of the first time period is equal to the duration of the second time period.

13. The method of any of claims 3 to 12, wherein the first secondary chip is adjacent to the second secondary chip in the preset ordering,

a time interval between an end time of the first time period and a start time of the second time period is greater than zero, and the main chip does not communicate with the at least one auxiliary chip within the time interval.

14. The method of any of claims 1 to 13, wherein the master chip is connected to an intermediate device via the single bus, and wherein the intermediate device is connected to any of the at least one slave chips via the single bus.

15. The method of claim 14, wherein the intermediate device is a relay.

16. The method according to any one of claims 1 to 15, further comprising:

determining a first chip of the plurality of chips as the master chip.

17. The method of claim 16, wherein determining a first chip of the plurality of chips to be the master chip comprises:

and if the chip corresponding to the preset identifier in the plurality of chips is the first chip, determining the first chip as the main chip.

18. The method of claim 16, wherein determining a first chip of the plurality of chips to be the master chip comprises:

the multiple chips receive indication information sent by target equipment, the indication information indicates that a first chip in the multiple chips is the main chip, and the target equipment is connected with the multiple chips;

and determining a first chip in the plurality of chips as the main chip according to the indication information.

19. The method of any of claims 16 to 18, wherein after determining a first chip of the plurality of chips as the master chip, the method further comprises:

if the first chip fails, the main chip is changed from the first chip to a second chip in the plurality of chips.

20. The method of any one of claims 1 to 19, wherein the plurality of chips comprises at least one of a Digital Signal Processing (DSP) chip, a radar chip, or a vision chip.

21. A method for time synchronization among a plurality of chips, wherein the plurality of chips includes a main chip and at least one auxiliary chip, the main chip is connected to each of the at least one auxiliary chip through a single bus, the method comprising:

the main chip is communicated with the at least one auxiliary chip through the single bus according to a preset arrangement sequence, so that the time of the chips is synchronized.

22. The method of claim 21, further comprising:

23. The method of claim 22, wherein the sending, by the master chip to the at least one slave chip via the single bus, the preset ordering comprises:

and the main chip broadcasts and sends the preset arrangement sequence to each auxiliary chip through the single bus.

24. The method according to any one of claims 21 to 23, wherein the preset ordering comprises: a first secondary chip of the at least one secondary chip precedes a second secondary chip,

25. The method of claim 24, wherein during the first time period, the master chip communicates with the first slave chip via the single bus, comprising:

in the first time period, the main chip sends a first data packet to the first auxiliary chip through the single bus, the sending time of the first data packet is the first time of the main chip, and the receiving time of the first data packet is the second time of the first auxiliary chip;

in the first time period, the main chip receives a second data packet sent by the first auxiliary chip through the single bus, the sending time of the second data packet is the third time of the first auxiliary chip, the receiving time of the second data packet is the fourth time of the main chip, and the first time, the second time, the third time and the fourth time are used for determining the time difference between the first auxiliary chip and the main chip.

26. The method of claim 25, further comprising:

27. The method of claim 25 or 26, wherein the length of the first packet is equal to the length of the second packet.

28. The method of any one of claims 25 to 27, wherein the transmission protocol of the first data packet sent by the master chip is identical to the transmission protocol of the second data packet sent by the first slave chip.

29. The method according to any one of claims 25 to 28, wherein the transmission path for transmitting the first data and the second data between the primary chip and the first secondary chip is the same.

30. The method of any one of claims 23 to 29, wherein the duration of the first time period is equal to the duration of the second time period.

31. The method of any one of claims 23 to 30, wherein the first secondary chip is adjacent to the second secondary chip in the preset ordering,

and the time interval between the ending time of the first time period and the starting time of the second time period is greater than zero, and the main chip does not perform time synchronization with the at least one auxiliary chip in the time interval.

32. The method of any one of claims 21 to 31, wherein the plurality of chips comprises at least one of a Digital Signal Processing (DSP) chip, a radar chip, or a vision chip.

33. The method of any of claims 21 to 32, wherein the master chip is connected to an intermediate device via the single bus, and wherein the intermediate device is connected to any of the at least one slave chips via the single bus.

34. The method of claim 33, wherein the intermediate device is a relay.

35. A time synchronizer, characterized in that the time synchronizer is connected with a plurality of chips through a single bus,

the time synchronization device is used for communicating with the plurality of auxiliary chips according to a preset arrangement sequence so as to synchronize the time of the plurality of chips.

36. The time synchronizer of claim 35, wherein the time synchronizer is further configured to:

determining the preset arrangement order for communicating with the at least one secondary chip;

and sending the preset arrangement sequence to the at least one auxiliary chip through the single bus.

37. The time synchronizer of claim 36, wherein the time synchronizer is configured to:

and broadcasting and sending the preset arrangement sequence to each auxiliary chip through the single bus.

38. The time synchronizer of any one of claims 35 to 37, wherein the preset arranging order comprises: a first secondary chip of the at least one secondary chip precedes a second secondary chip,

the time synchronizer is further configured to:

communicating with the first auxiliary chip through the single bus within a first time period;

and communicating with the second auxiliary chip through the single bus in a second time period, wherein the first time period is before the second time period, and the first time period and the second time period are not overlapped.

39. The time synchronizer of claim 38, wherein the time synchronizer is configured to:

in the first time period, sending a first data packet to the first auxiliary chip through the single bus, wherein the sending time of the first data packet is the first time of the time synchronization device, and the receiving time of the first data packet is the second time of the first auxiliary chip;

and in the first time period, receiving a second data packet sent by the first auxiliary chip through the single bus, wherein the sending time of the second data packet is a third time of the first auxiliary chip, the receiving time of the second data packet is a fourth time of the time synchronization device, and the first time, the second time, the third time and the fourth time are used for determining the time difference between the first auxiliary chip and the time synchronization device.

40. The time synchronizer of claim 39, wherein the time synchronizer is further configured to:

and in the first time period, sending a third data packet and a fourth data packet to the first auxiliary chip through the single bus, wherein the third data packet comprises the first time, and the fourth data packet comprises the third time.

41. The time synchronizer of claim 39 or 40, wherein the length of the first data packet is equal to the length of the second data packet.

42. The time synchronizer of any one of claims 39 to 41, wherein a transmission protocol of the time synchronizer for transmitting the first data packet is identical to a transmission protocol of the first slave chip for transmitting the second data packet.

43. The time synchronizer of any one of claims 39 to 42, wherein the transmission path for transmitting the first data and the second data between the time synchronizer and the first secondary chip is the same.

44. The time synchronizer of any one of claims 37 to 43, wherein the duration of the first time period is equal to the duration of the second time period.

45. The time synchronizer of any one of claims 37 to 44, wherein said first slave chip is adjacent to said second slave chip in said preset alignment order,

and the time interval between the ending time of the first time period and the starting time of the second time period is greater than zero, and the time synchronization device does not perform time synchronization with the at least one auxiliary chip in the time interval.

46. The time synchronizer of any one of claims 35 to 45, wherein the plurality of chips comprises at least one of a Digital Signal Processing (DSP) chip, a radar chip, or a vision chip.

47. The time synchronizer of any one of claims 35 to 46, wherein the time synchronizer is coupled to an intermediate device via the single bus, the intermediate device being coupled to any one of the at least one slave chip via the single bus.

48. The time synchronizer of claim 47, wherein the intermediate device is a relay.

49. A time synchronization system, comprising a plurality of chips including a main chip and at least one auxiliary chip, the main chip being connected to each of the at least one auxiliary chip via a single bus,

the main chip is used for communicating with the at least one auxiliary chip through the single bus according to a preset arrangement sequence;

the auxiliary chip is used for executing time synchronization operation according to the information acquired in the communication between the auxiliary chip and the main chip.

50. The time synchronization system of claim 49, wherein the master chip is further configured to:

51. The system according to claim 49 or 50, wherein the predetermined arrangement sequence comprises: a first secondary chip of the at least one secondary chip precedes a second secondary chip,

the master chip is further configured to:

52. The time synchronization system of claim 51, wherein the at least one secondary core is further configured to:

and determining the time difference with the main chip according to the information acquired in the communication with the main chip in the first time period.

53. The time synchronization system of claim 52, wherein the first secondary chip is further configured to:

and adjusting the time to be synchronous with the time of the main chip according to the time difference.

54. The time synchronization system of claim 52 or 53, wherein the master chip is further configured to:

in the first time period, sending a first data packet to the first auxiliary chip through the single bus, wherein the sending time of the first data packet is the first time of the main chip;

the first secondary chip is further configured to:

receiving the first data packet, wherein the receiving time of the first data packet is a second time of the first auxiliary chip time,

in the first time period, sending a second data packet to the main chip through the single bus, wherein the sending time of the second data packet is the third time of the first auxiliary chip;

the master chip is further configured to:

and receiving the second data packet, wherein the receiving time of the second data packet is the fourth time of the main chip.

55. The time synchronization system of claim 54, wherein the first secondary chip is further configured to:

and determining the time difference with the main chip according to the first time, the second time, the third time and the fourth time.

56. The time synchronization system of claim 54 or 55, wherein the master chip is further configured to:

57. The system according to any one of claims 54 to 56, wherein the length of the first data packet is equal to the length of the second data packet.

58. The time synchronization system of any one of claims 54-57, wherein a transmission protocol of the first data packet transmitted by the master chip is identical to a transmission protocol of the second data packet transmitted by the first slave chip.

59. The time synchronization system according to any one of claims 54 to 57, wherein the transmission path for transmitting the first data and the second data between the main chip and the first auxiliary chip is the same.

60. The time synchronization system of any one of claims 51 to 59, wherein a duration of said first time period is equal to a duration of said second time period.

61. The time synchronization system of any one of claims 51 to 60, wherein in the preset ordering, the first secondary chip is adjacent to the second secondary chip,

62. The time synchronization system of any one of claims 49-61, wherein said master chip is connected via said single bus to an intermediate device, said intermediate device being connected via said single bus to any one of said at least one slave chip.

63. The time synchronization system of claim 62, wherein the intermediate device is a relay.

64. The time synchronization system of any one of claims 49-63, wherein a first chip of said plurality of chips is said master chip.

65. The time synchronization system according to claim 64, wherein the first chip is the master chip if a chip corresponding to a predetermined identifier among the plurality of chips is the first chip.

66. The time synchronization system of claim 64, wherein the plurality of chips are further configured to:

receiving indication information sent by target equipment, wherein the indication information indicates that a first chip in the plurality of chips is the main chip, and the target equipment is connected with the plurality of chips.

67. The system according to any one of claims 64 to 66, wherein if a first chip of the plurality of chips is the master chip and the first chip fails, the master chip is changed from the first chip to a second chip of the plurality of chips.

68. The time synchronization system of any one of claims 49-67, wherein the plurality of chips comprises at least one of a Digital Signal Processing (DSP) chip, a radar chip, or a vision chip.

69. A movable platform, comprising:

a body;

the power system is arranged on the machine body and used for providing power for the movable platform;

the time synchronization system of any one of claims 49-68.