CN112117736B - Solid state power controller - Google Patents
Solid state power controller Download PDFInfo
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- CN112117736B CN112117736B CN202010838464.5A CN202010838464A CN112117736B CN 112117736 B CN112117736 B CN 112117736B CN 202010838464 A CN202010838464 A CN 202010838464A CN 112117736 B CN112117736 B CN 112117736B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/04—Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
- H02H11/006—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of too high or too low voltage
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Abstract
The invention provides a fault detection circuit design applied to a solid-state power controller, and aims to solve the problem that the normal shutdown mode and the fault shutdown mode of the solid-state power controller cannot be accurately identified. The solid state power controller includes a fault detection circuit comprised of a power (reset) circuit, a signal detection circuit, and a status output circuit. The power supply (reset) circuit controls the power-on and power-off of the signal detection circuit and the state output circuit, a VCC power supply is generated by the voltage division and rectification of a bus power supply of the solid-state power controller, and a reset signal is generated at the moment of power-on to control the signal detection circuit to carry out reset operation; the signal detection circuit receives a reset signal generated by the power supply (reset) circuit at the moment of electrification, performs reset operation on the circuit, and outputs a high level or a low level according to a starting reset signal generated by the switch control circuit and a level control signal generated by the solid-state power controller through the current acquisition circuit and the protection circuit; and the state output circuit outputs high and low level signals respectively according to the level signals output by the signal detection circuit.
Description
Technical Field
The invention relates to a novel solid-state power controller with a fault detection circuit and a turn-off reason monitoring means, belonging to the technical field of electrical design.
Background
With the rapid development of microelectronic technology and chip process design in the domestic electronic industry, the solid-state power controller has also been widely applied to various power supply and distribution systems as a core control switch in the field of power electronic control.
The general solid-state power controller comprises a power supply circuit, a switch control circuit, a power driving circuit, a current acquisition circuit, a protection circuit, an indication circuit and the like, and is used for switching on and switching off corresponding circuits in an instruction mode and acquiring and monitoring bus current in real time. Once over-current/short-circuit faults occur, the controller can immediately identify and directly cut off the power supply to protect the system where the controller is located, and the controller has the advantages of high response speed, strong anti-interference capability, recoverability after fault removal and the like.
The operating modes of the existing solid-state power controller are divided into three types, namely normal on, normal off and fault off. As shown in fig. 1, when the circuit is in a normal state after power-on, the on/off indicating circuit outputs a low level; when the controller circuit enters a working state after a switch-on instruction is input, the switch-on/off indicating circuit outputs a high level; when the controller circuit is in a turn-off state after a turn-off instruction is input, the on/off indicating circuit outputs a low level; when faults such as overcurrent/short circuit occur, the controller circuit enters a fault mode, at the moment, the power supply is cut off, and the on/off indicating circuit still outputs low level. Therefore, in the conventional controller circuit, no matter the circuit is turned off in a fault or is controlled to be turned off in a normal working state, the on/off indicating end outputs a low level, and a user cannot directly and specifically judge the working state of the circuit when the circuit is turned off from the outside of the controller, so that the monitoring and control on whether the power device and the bus circuit work normally or not cannot be implemented based on the solid-state power controller, and the safety of a corresponding power supply and distribution system is not protected.
In view of this, the present patent application is specifically proposed.
Disclosure of Invention
The solid-state power controller aims to solve the problems existing in the prior art and provides a fault detection circuit design applied to the solid-state power controller so as to solve the problem that the normal shutdown and fault shutdown modes of the solid-state power controller cannot be accurately identified, and therefore the accuracy of judging the working state of the controller circuit is improved.
To achieve the above design objective, the solid-state power controller includes a fault detection circuit composed of a power supply (reset) circuit, a signal detection circuit, and a status output circuit.
Specifically, the power supply (reset) circuit controls the power-on and power-off of the signal detection circuit and the state output circuit, a VCC power supply of the power supply (reset) circuit is generated by voltage division and rectification of a bus power supply of the solid-state power controller, and a reset signal is generated at the moment of power-on to control the signal detection circuit to carry out reset operation; the signal detection circuit receives a reset signal generated by the power supply (reset) circuit at the moment of electrification, performs reset operation on the circuit, and outputs a high level or a low level according to a starting reset signal generated by the switch control circuit and a level control signal generated by the solid-state power controller through the current acquisition circuit and the protection circuit; and the state output circuit outputs high and low level signals respectively according to the level signals output by the signal detection circuit.
According to the design concept, in order to solve the problem that normal turn-off and fault turn-off cannot be judged, the fault detection circuit is designed, and when the circuit is normally turned on or turned off, the fault detection circuit always outputs a low level; when the circuit has overload fault, the fault detection circuit outputs high level; after the fault is removed, the input turn-on instruction circuit is turned on again, and the fault detection circuit outputs low level again, so that the normal turn-off state and the fault turn-off state can be fundamentally distinguished.
Further, in the power supply (reset) circuit, one end of a resistor R1 is simultaneously connected to one end of a resistor R2 and a power supply end (i.e., a bus power supply end of the solid-state power controller) VCC of the fault detection circuit, the other end of the resistor R1 is simultaneously connected to a negative electrode of the regulator tube Z1 and a base electrode of the transistor Q1, the other end of the resistor R2 is connected to a collector of the transistor Q1, an emitter of the transistor Q1 is simultaneously connected to one end of the resistor R3 and a negative electrode of the diode D1, the other end of the resistor R3 is simultaneously connected to an anode of the diode D1 and one end of the capacitor C1, and the other end of the capacitor C1 is simultaneously connected to a positive end of the regulator tube Z1 and a GND end (i.e., a GND end of the solid-state power controller) of the fault detection circuit.
Furthermore, in the signal detection circuit, one end of a resistor R4 is simultaneously connected with the D end of the D flip-flop U2, the emitter of the triode Q1, the cathode of the diode D1 and one end of a resistor R3, the other end of a resistor R4 is connected with the VDD end of the D flip-flop U2, one end of a resistor R5 is simultaneously connected with the R end of the D flip-flop U2, the negative electrode of the diode D2 and the negative electrode of the diode D3 are connected, the other end of the resistor R5 is connected with the GND end of the fault detection circuit, the positive electrode of the diode D2 is connected with the output end of the inverting amplifier U1, the positive electrode of the diode D3 is connected with the Vr end of the fault detection circuit, the input end of the inverting amplifier U1 is simultaneously connected with the other end of the resistor R3, one end of the capacitor C1 and the positive electrode of the diode D1, the VSS end of the D flip-flop U2 is connected with the GND end of the fault detection circuit, and the CK end of the D flip-flop U2 is connected with the Vin end of the fault detection circuit.
Furthermore, in the state output circuit, one end of a resistor R6 is connected to the Q end of the D flip-flop U2, the other end of the resistor R6 is connected to the negative electrode of the regulator tube Z2 and the base of the transistor Q2, one end of a resistor R7 is connected to the emitter of the transistor Q2 and the output terminal Vout of the fault detection circuit, the other end of the resistor R7 is connected to the positive electrode of the regulator tube Z2 and the GND end of the fault detection circuit, and the collector of the transistor Q2 is connected to one end of the resistor R3, one end of the resistor R4, the negative electrode of the diode D1, the emitter of the transistor Q1, and the D end of the D flip-flop U2.
In summary, the solid state power controller described in the present application has the following advantages:
1. through the signal detection circuit, whether the controller is in a normal shutdown state or a fault shutdown state can be effectively identified, repeated operation in an error state is avoided, the reliability of the power circuit is favorably improved, the service life of the power circuit is prolonged, and the power supply and distribution system can be ensured to operate in a safe, stable and reliable state.
2. The circuit fault troubleshooting time is short, and the operation efficiency is high.
3. The power supply (reset) circuit can effectively avoid the phenomenon of outputting high level at the moment of power-on and always existing due to the last fault state, and the signal detection circuit is reset to avoid the phenomenon of disorder of the output state.
4. The starting reset signal can be introduced through the switch control circuit, and the signal detection circuit can be reset at the starting moment, so that the output high level phenomenon existing all the time due to the last fault state is effectively avoided, and the system safety is further improved.
5. The driving capability of the circuit output end can be obviously improved through the state output circuit, the phenomenon that the output level is reduced due to load change is effectively avoided, and the application range of the controller circuit is expanded.
Drawings
The following drawings are illustrative of specific embodiments of the present application.
FIG. 1 is a circuit schematic block diagram of a prior art solid state power controller;
FIG. 2 is a functional block diagram of a solid state power controller circuit having fault detection circuitry as described herein;
FIG. 3 is a block diagram of a fault detection circuit included in the solid state power controller of the present application;
fig. 4 is a waveform diagram of key points of a fault detection operation process using the solid state power controller of the present application.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings.
Embodiment 1, as shown in fig. 2 and 3, the present application proposes a novel solid-state power controller having a fault detection circuit including a power supply (reset) circuit, a signal detection circuit, and a status output circuit.
The power supply (reset) circuit comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a diode D1, a voltage regulator tube Z1 and a triode Q1, wherein one end of the resistor R1 is simultaneously connected with one end of the resistor R2 and a power supply end (namely a bus power supply end of a solid-state power controller) VCC, the other end of the resistor R1 is simultaneously connected with a negative electrode of the voltage regulator tube Z1 and a base electrode of the triode Q1, the other end of the resistor R2 is connected with a collector of the triode Q1, an emitter of the triode Q1 is simultaneously connected with one end of the resistor R3 and a negative electrode of the diode D1, the other end of the resistor R3 is simultaneously connected with a positive electrode of the diode D1 and one end of the capacitor C1, and the other end of the capacitor C1 is simultaneously connected with a GND of the voltage regulator tube Z1 and a GND end of the fault detection circuit (namely a GND end of the solid-state power controller). The solid-state power controller bus power supply voltage division rectification generates a VCC power supply to control the power-on and power-off of the signal detection circuit and the state output circuit, and generates a reset signal at the power-on moment to control the signal detection circuit to perform reset operation.
The signal detection circuit comprises a resistor R4, a resistor R5, a diode D2, a diode D3, an inverting amplifier U1 and a D flip-flop U2, wherein one end of the resistor R4 is connected with the D end of the D flip-flop U2, the emitter of a triode Q1, the cathode of a diode D1 and one end of the resistor R3 at the same time, the other end of the resistor R4 is connected with the VDD end of the D flip-flop U2, one end of the resistor R5 is connected with the R end of the D flip-flop U2, the cathode of a diode D2 and the cathode of a diode D3 at the same time, the other end of the resistor R5 is connected with the GND end of the fault detection circuit, the anode of a diode D2 is connected with the output end of the inverting amplifier U1, the anode of the diode D3 is connected with the Vr end of the fault detection circuit, the input end of the inverting amplifier U1 is connected with the other end of the resistor R3, one end of the capacitor C1 and the anode of the diode D1, the VSS end of the D2 is connected with the GND end of the fault detection circuit, the CK terminal of the D flip-flop U2 is connected with the Vin terminal of the fault detection circuit. At the moment of power-on, the signal detection circuit receives a reset signal generated by the power supply (reset) circuit and performs reset operation on the circuit, the Vin end receives a level control signal generated by the solid-state power controller through the current acquisition circuit and the protection circuit, the Vr end receives a start reset signal generated by the switch control circuit, and the D trigger U2 outputs a high level or a low level according to the reset signal generated by the power supply (reset) circuit or the Vr end and the change of the level signal of the Vin end.
The state output circuit comprises a resistor R6, a resistor R7, a voltage regulator tube Z2 and a triode Q2, wherein one end of the resistor R6 is connected with the Q end of a D flip-flop U2, the other end of the resistor R6 is connected with the negative electrode of the voltage regulator tube Z2 and the base electrode of the triode Q2, one end of a resistor R7 is connected with the emitter of the triode Q2 and the output end Vout of a fault detection circuit, the other end of the resistor R7 is connected with the positive electrode of the voltage regulator tube Z2 and the GND end of the fault detection circuit, and the collector of the triode Q2 is connected with one end of the resistor R3, one end of the resistor R4, the negative electrode of a diode D1, the emitter of the triode Q1 and the D end of the D flip-flop U2. When the signal detection circuit outputs a high level, the voltage regulator tube Z2 works in a voltage-stabilizing state, the triode Q2 is conducted, and Vout outputs a high level signal; when the signal detection circuit outputs a low level, the voltage regulator tube Z2 works in a cut-off state, the triode Q2 is turned off, and Vout outputs a low level signal.
Based on the design of the fault detection circuit, the application also realizes a novel fault detection method for the solid-state power controller, which comprises the following steps:
in the power supply (reset) circuit, a VCC power supply is generated by the bus voltage division rectification of a solid-state power controller, a power supply is generated by an emitter of a triode Q1, and the power supply voltage is determined by a voltage stabilizing value VZ1 of a voltage stabilizing tube Z1 and a BE junction voltage VQ1_ BE of the triode Q1 and is equal to VZ1-VQ1_ BE; the voltage is used for controlling the power-on and power-off of the signal detection circuit and the state output circuit;
at the moment that the power supply (reset) circuit is powered on, the connection end of the capacitor C1 and the resistor R3 generates a low level signal, and the low level signal is changed into a high level signal after the capacitor C1 is charged; a low-level signal generated at the moment of power-on is converted by an inverting amplifier of the signal detection circuit to generate a high-level reset signal, and the high-level reset signal is output to the R end of the D flip-flop U2, so that the signal detection circuit is reset, and the Q end of the D flip-flop U2 outputs a low-level signal; after the capacitor C1 is charged, the signal at the connection end of the capacitor C1 and the resistor R3 becomes high level, and is converted by an inverting amplifier of the signal detection circuit to generate a low level signal, so that the reset operation of the D flip-flop U2 is completed;
a positive pulse signal (namely, a starting signal) is introduced into the Vr end of the signal detection circuit through the switch control circuit, passes through the reverse prevention diode D3 and is output to the R end of the D trigger U2, so that the signal detection circuit is reset again, and the Q end of the D trigger U2 outputs a low-level signal; a Vin end of the signal detection circuit receives a level control signal generated by the solid-state power controller through the current acquisition circuit and the protection circuit, when the solid-state power controller is in normal work or is normally turned off, a voltage signal generated by the current acquisition circuit is lower than a threshold voltage of a comparator of the protection circuit, so that the protection circuit outputs a low level signal to the Vin end of the signal detection circuit, and a Q end of the D trigger U2 maintains the last working state (namely the low level signal generated by the reset operation) and outputs the low level; when the solid-state power controller circuit is turned off due to a fault, the voltage signal generated by the current acquisition circuit is higher than the threshold voltage of the protection circuit comparator, the output signal of the protection circuit is changed from low level to high level, a rising edge signal is generated and sent to the Vin end of the signal detection circuit, and the Q end of the D trigger U2 is equal to the high-level voltage of the D end and outputs high level.
The state output circuit amplifies the level signal output by the signal detection circuit and outputs the level signal to a Vout end of the fault detection circuit, when the signal detection circuit outputs a low level, the voltage regulator tube Z2 works in a cut-off state, the base electrode of the triode Q2 is at a low level and is in a cut-off state, and the Vout end outputs a low level signal; when the signal detection circuit outputs a high level, the voltage regulator tube Z2 works in a voltage stabilization state, the base voltage of the triode Q2 is equal to the voltage stabilization value of the voltage regulator tube Z2 and is in a conduction state, and after the signal is amplified by the triode Q2, the Vout end outputs a high level signal.
In fig. 4, (a) is a fault detection process in a normal operation or normal shutdown state, (b) is a fault detection process in a fault state, and (c) is a fault detection process after the fault is released.
As shown in fig. 4 (a), when a controller bus VCC power supply of the fault detection circuit is powered on, VCC voltage is applied to a voltage regulator tube Z1 through a resistor R1, when the VCC voltage is higher than a voltage regulator tube Z1, the voltage regulator tube Z1 works in a voltage-stabilized state, the voltage of the negative terminal of the voltage regulator tube Z1 is equal to the voltage-stabilized value of the voltage regulator tube Z1, the voltage value acts on the base of a triode Q1, Q1 is turned on, the voltage of a Q1 emitter (namely, VCC 1) is equal to the voltage value VZ1 of the voltage regulator tube Z1 minus the BE junction voltage VQ1_ BE of the triode Q1, and the voltage of the VCC1 is used for controlling the power-on and power-off of the signal detection circuit and the state output circuit. After the Q1 is turned on, the bus power VCC starts to charge the capacitor C1 through the resistor R2, the triode Q1, the resistor R3 and the anti-reverse diode D1, because the voltage at two ends of the capacitor cannot change suddenly, namely the upper end (Vrst 1 end) of the C1 at the moment of power-on is at a low level, the voltage at the Vrst1 end outputs a high level signal after being converted by the inverting amplifier U1, and then the high level signal is output to the D trigger R end through the anti-reverse diode D2, at this time, the Vrst2 end is at a high level, the D trigger U2 performs reset operation, the Vq end outputs a low level signal, the voltage regulator Z2 works in a cut-off state, the triode Q2 is turned off, and the Vout output end is at a low level. When the capacitor C1 is charged to the time t1, the Vrst1 voltage is equal to the inversion threshold of the inverting amplifier U1, the U1 inverts to output a low-level signal, the Vrst2 changes to a low level, the D-flip-flop U2 finishes the reset operation, the output voltage of the Q end of the D-flip-flop is maintained at a low level, and the output end of Vout is maintained at a low level.
As shown in fig. 4 (b), when the circuit normally works or is normally turned off, the Vin terminal is always at a low level after the solid-state power controller passes through the current collecting circuit and the protection circuit. At the time of t4, when an overcurrent or short-circuit fault occurs on a bus of the solid-state power controller, the voltage output by the current acquisition circuit exceeds the overturning threshold voltage of a comparator inside the protection circuit, the comparator outputs a high-level signal, namely, the Vin end is changed into a high-level signal, at the moment, the D trigger U2 transmits the high-level signal of the D end of U2 to the Q end under the clock action of the rising edge, Vq is changed into a high level, the voltage stabilizing tube Z2 enters a voltage stabilizing state, the triode Q2 is turned on, and the Vout end outputs a high-level signal. At the time of t5, after the solid-state power controller is turned off under the action of the protection circuit, the voltage output by the current acquisition circuit is lower than the turnover threshold voltage of the comparator inside the protection circuit again, the comparator outputs a low level signal, that is, the Vin end becomes a low level signal again, the CK end of the D flip-flop U2 is a falling edge at the time, the D end of the U2 maintains the previous state, that is, the Vq end voltage is always a high level, the Vout end of the fault detection circuit always outputs a high level, and the indication circuit enters a fault turn-off working mode.
As shown in fig. 4 (c), after the failure is resolved, the operation of the failure detection circuit is as follows: at the time of t6, after an overcurrent or short-circuit fault occurs in a bus of the solid-state power controller, the fault detection circuit outputs a high level, after the fault is relieved, at the time of t7, a positive pulse signal (namely, a starting signal) is introduced through the switch control circuit, the positive pulse signal is input to a Vr end of the signal detection circuit, the Vr end of the signal detection circuit passes through the anti-reverse diode D3 and is output to an R end of the D trigger U2, at the moment, the Vrst2 end is the high level, the D trigger U2 carries out reset operation, the Vq end outputs a low level signal, the voltage regulator Z2 works in a cut-off state, the triode Q2 is turned off, the Vout output end is the low level, and the solid-state power controller circuit enters a normal working state. At time t8, the reset operation is finished, the output voltage of the Q end of the D flip-flop is maintained at a low level, the output end of the Vout is maintained at a low level, and the solid-state power controller is kept in a normal working state.
In summary, the embodiments presented in connection with the figures are only preferred. Those skilled in the art can derive other alternative structures according to the design concept of the present invention, and the alternative structures should also fall within the scope of the solution of the present invention.
Claims (3)
1. A solid state power controller, characterized by: the fault detection circuit comprises a power supply reset circuit, a signal detection circuit and a state output circuit;
the power supply reset circuit controls the power-on and power-off of the signal detection circuit and the state output circuit, a VCC power supply is generated by the voltage division and rectification of a bus power supply of the solid-state power controller, and a reset signal is generated at the moment of power-on to control the signal detection circuit to carry out reset operation;
one end of a resistor R1 of the power supply reset circuit is simultaneously connected with one end of a resistor R2 and a power supply end of a fault detection circuit, namely a power supply end VCC of a bus of the solid-state power controller, the other end of the resistor R1 is simultaneously connected with a negative electrode of a voltage regulator tube Z1 and a base electrode of a triode Q1, the other end of a resistor R2 is connected with a collector of a triode Q1, an emitter of the triode Q1 is simultaneously connected with one end of the resistor R3 and a negative electrode of a diode D1, the other end of the resistor R3 is simultaneously connected with a positive electrode of a diode D1 and one end of a capacitor C1, and the other end of a capacitor C1 is simultaneously connected with a positive end of the voltage regulator tube Z1 and a GND end of the fault detection circuit, namely a GND end of the solid-state power controller;
the signal detection circuit receives a reset signal generated by the power supply reset circuit at the moment of electrification, performs reset operation on the circuit, and outputs a high level or a low level according to a starting reset signal generated by the switch control circuit and a level control signal generated by the solid-state power controller through the current acquisition circuit and the protection circuit;
and the state output circuit outputs high and low level signals respectively according to the level signals output by the signal detection circuit.
2. The solid state power controller of claim 1, wherein: one end of a resistor R4 of the signal detection circuit is connected with a D end of a D trigger U2, an emitter of a triode Q1, a cathode of a diode D1 and one end of a resistor R3 at the same time, the other end of a resistor R4 is connected with a VDD end of a D trigger U2, one end of a resistor R5 is connected with an R end of the D trigger U2, a cathode of a diode D2 and a cathode of the diode D3 at the same time, the other end of the resistor R5 is connected with a GND end of the fault detection circuit, an anode of the diode D2 is connected with an output end of an inverting amplifier U1, an anode of the diode D3 is connected with a Vr end of the fault detection circuit, an input end of the inverting amplifier U1 is connected with the other end of a resistor R3, one end of a capacitor C1 and an anode of a diode D1 at the same time, a VSS end of a D trigger U2 is connected with a GND end of the fault detection circuit, and a CK end of a D trigger U2 is connected with a Vin end of the fault detection circuit.
3. The solid state power controller of claim 1, wherein: in the state output circuit, one end of a resistor R6 is connected with a Q end of a D trigger U2, the other end of a resistor R6 is connected with the negative electrode of a voltage regulator tube Z2 and the base electrode of a triode Q2, one end of a resistor R7 is connected with the emitter of the triode Q2 and the output end Vout of the fault detection circuit, the other end of the resistor R7 is connected with the positive electrode of the voltage regulator tube Z2 and the GND end of the fault detection circuit, and the collector of the triode Q2 is connected with one end of a resistor R3, one end of a resistor R4, the negative electrode of a diode D1, the emitter of a triode Q1 and the D end of a D trigger U2.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102570412A (en) * | 2011-12-29 | 2012-07-11 | 航天时代电子技术股份有限公司 | DC solid-state power controller |
| CN111030654A (en) * | 2019-11-29 | 2020-04-17 | 山东航天电子技术研究所 | Solid-state power controller |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7505820B2 (en) * | 2006-03-30 | 2009-03-17 | Honeywell International Inc. | Backup control for solid state power controller (SSPC) |
| US7656634B2 (en) * | 2006-11-30 | 2010-02-02 | Hamilton Sundstrand Corporation | Increasing the system stability and lightning capability in a power distribution system that utilizes solid-state power controllers |
| GB2561225B (en) * | 2017-04-06 | 2020-02-19 | Ge Aviation Systems Group Ltd | Power distribution node |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102570412A (en) * | 2011-12-29 | 2012-07-11 | 航天时代电子技术股份有限公司 | DC solid-state power controller |
| CN111030654A (en) * | 2019-11-29 | 2020-04-17 | 山东航天电子技术研究所 | Solid-state power controller |
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