CN112115666A - Method and system for drawing schematic diagram - Google Patents
Method and system for drawing schematic diagram Download PDFInfo
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- CN112115666A CN112115666A CN201910458175.XA CN201910458175A CN112115666A CN 112115666 A CN112115666 A CN 112115666A CN 201910458175 A CN201910458175 A CN 201910458175A CN 112115666 A CN112115666 A CN 112115666A
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Abstract
The embodiment of the invention discloses a method and a system for drawing a schematic diagram, which relate to the technical field of automatic design. The method comprises the following steps: acquiring product information from a design document, acquiring a product CBB corresponding to the product information from a universal basic module CBB library, and writing the product CBB into a netlist file according to a preset format; traversing the clock interface of the product CBB, acquiring the clock CBB corresponding to the clock interface from the CBB library, and writing the clock CBB into the netlist file according to a preset format; traversing the power supply interface of the product CBB, acquiring the power supply CBB corresponding to the power supply interface from the CBB library, and writing the power supply CBB into the netlist file according to a preset format; and drawing the schematic diagram according to the netlist file.
Description
Technical Field
The invention belongs to the technical field of automatic design in the field of electronic equipment, and particularly relates to a method and a system for drawing a schematic diagram.
Background
With the market competition becoming more and more intense, electronic equipment manufacturers are able to rapidly bring products to the market as a core competitiveness. Meanwhile, along with the continuous rising of the labor cost, the profit of the product continuously slides down, and the per capita output rate is urgently needed to be improved. In contrast, various electronic equipment manufacturers are constantly searching for methods for reducing the product development cycle and improving the per-capita yield. Practice proves that design automation is an effective method for reducing the research and development period of products and improving the per-capita yield. In the development process of electronic equipment, drawing a schematic diagram is a very important ring in the development process of products. How to rapidly draw the schematic diagram to meet the requirement of rapidly pushing the product to the market is a problem actively explored by electronic equipment manufacturers, and some methods for automatically drawing the schematic diagram are proposed at present. However, these methods also have the disadvantages of low automation degree and huge database building workload, and cannot meet the requirement of fast drawing schematic diagrams.
Disclosure of Invention
The invention provides a method for drawing a schematic diagram, which is used for solving the problems that the conventional method for automatically drawing the schematic diagram is low in automation degree, large in library building workload and incapable of meeting the requirement of quickly drawing the schematic diagram.
In order to achieve the above object, in a first aspect, the present invention provides a method of drawing a schematic diagram, the method comprising:
acquiring product information from a design document, acquiring a product CBB corresponding to the product information from a universal basic module CBB library, and writing the product CBB into a netlist file according to a preset format;
traversing the clock interface of the product CBB, acquiring the clock CBB corresponding to the clock interface from the CBB library, and writing the clock CBB into the netlist file according to a preset format;
traversing the power supply interface of the product CBB, acquiring the power supply CBB corresponding to the power supply interface from the CBB library, and writing the power supply CBB into the netlist file according to a preset format;
and drawing the schematic diagram according to the netlist file.
In a second aspect, the present invention provides a system for drawing a schematic diagram, the system comprising:
the acquisition module is used for acquiring product information from the design document;
the matching module is used for acquiring a product CBB corresponding to the product information from a universal basic module CBB library and writing the product CBB into a netlist file according to a preset format;
the matching module is further configured to traverse a clock interface of the product CBB, obtain a clock CBB corresponding to the clock interface from the CBB library, and write the clock CBB into the netlist file according to a predetermined format;
the matching module is further configured to traverse a power interface of the product CBB, obtain a power CBB corresponding to the power interface from the CBB library, and write the power CBB into the netlist file according to a predetermined format;
and the drawing module is used for drawing the schematic diagram according to the netlist file.
The method for drawing the schematic diagram provided by the embodiment of the invention can automatically analyze the product information from the design document, acquire the product CBB corresponding to the product information from the CBB library according to the product information, automatically traverse and count the clock parameter information and the power supply parameter information, and acquire the corresponding clock CBB and the power supply CBB from the CBB library. According to the method provided by the embodiment of the invention, after a small amount of key information of a product in a design document is analyzed, detailed clock parameter information, power supply parameter information and the like are automatically acquired, and then the corresponding clock CBB, power supply CBB and the like are automatically matched from the CBB library, so that the workload of manually counting and calculating the relevant parameters of the clock and the power supply is greatly reduced, and the workload of manually reading a CBB use manual and manually matching the CBB is saved. The labor cost can be effectively saved, the schematic diagram drawing efficiency is improved, and the development cycle of products is accelerated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a method for drawing a schematic diagram according to an embodiment of the present invention;
FIG. 2 is an exemplary core chip list according to an embodiment of the present invention;
FIG. 3 is an exemplary external interface list of the product according to the embodiment of the present invention;
FIG. 4 is an exemplary CBB parameter table according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a system for drawing a schematic diagram according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The system architecture and the service scenario described in the embodiment of the present invention are for more clearly illustrating the technical solution of the embodiment of the present invention, and do not form a limitation on the technical solution provided in the embodiment of the present invention, and it can be known by those skilled in the art that the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems along with the evolution of the system architecture and the appearance of a new service scenario.
The above method is described in detail with reference to specific examples.
In the development process of electronic equipment, drawing a schematic diagram is a very important ring in the development process of products. The drawing of the schematic diagram is completed quickly and efficiently, the requirement that products are rapidly pushed to the market can be well met, and the per-capita yield is improved. In the embodiment of the present invention, a circuit having independent functions and multiplexing values, which is composed of main materials, peripheral devices thereof, and the like, may be made into a Common Building Block (CBB for short). For example, a circuit corresponding to a small system formed by a Central Processing Unit (CPU) and peripheral devices thereof is made into a CBB. And packaging the CBB into a schematic diagram symbol, and directly calling when the schematic diagram is drawn. Usually, according to the multiplexing rate of CBBs, etc., the CBBs may be pre-established and stored in the CBB library, for example, the power CBB, the clock CBB, the interface connector CBB, the interface chip CBB, etc. with higher multiplexing rate may be pre-established and stored in the CBB library.
The method for drawing the schematic diagram provided by the embodiment of the invention compiles a design document according to a set format, wherein the design document comprises a product core chip, a product external interface type, a product external interface and other core requirement information of a small number of product designs, and then a drawing tool automatically searches and matches a corresponding CBB and a device to perform operations such as placement, pin interconnection and the like. The drawing tool automatically recognizes the type of CBB and performs page layout according to a predetermined format. The method can automatically traverse and count the clock parameter information and the power supply parameter information, and place the corresponding clock CBB and the power supply CBB according to the clock parameter information and the power supply parameter information. The design document does not need to enumerate the required devices and the interconnection relation of device pins one by one, and compared with the prior method which requires compiling a schematic diagram scheme, the method provided by the embodiment of the invention greatly reduces the workload. Meanwhile, the method of the embodiment of the invention aims at the small workload of the CBB library building; the clock parameter information and the power parameter information are automatically traversed and counted, and the automation degree of drawing is improved.
An embodiment of the present invention provides a method for drawing a schematic diagram, as shown in fig. 1, the method includes:
In the embodiment of the invention, the design document is compiled according to a preset format, wherein the preset format can be a self-defined format, namely, specific information is filled in a form sequence of the design document and a row and column corresponding to the form according to a predetermined convention. After the design document is imported into the drawing tool, the design document is analyzed according to a set format, namely, the product information is obtained in the design document by taking the table sequence and the rows and columns corresponding to the tables as search bases, and the product CBB corresponding to the product information is obtained from the CBB library according to the product information. Specifically, the CBB corresponding to the product information may be acquired in the CBB library according to the material number in the product information; and if more than one product CBB corresponding to the product information is acquired in the CBB library according to the material number of the product information, selecting a unique corresponding product CBB for the product information according to the information of the version number or the interface bus type of each product CBB. Here, the selection may be performed manually or automatically according to a set rule, the set rule may be set by a user according to actual needs, for example, the set rule may be set to be selected according to a version number, if the set rule is to select a product CBB with a largest value of the version number (i.e., a latest version), if a unique corresponding product CBB can be determined according to the version number, the product CBB is selected, and if a unique corresponding product CBB cannot be determined according to the version number, the selection is performed according to an interface bus type, and a product CBB with an interface bus type identical to that of the interface bus of the interconnection device is selected. A uniquely corresponding product CBB is determined for the product information. In the embodiment of the invention, each interface of the product CBB corresponding to the product information is traversed, if the interface type is the bus type, the specific bus name is obtained, and the interface bus names of the product CBB corresponding to the interconnected devices are the same, so that the product CBB only corresponding to the interconnected devices is determined. And after determining a unique corresponding product CBB of the product information, writing the information of the name, the version number and the like of the determined product CBB into the netlist file according to a preset format.
In the embodiment of the invention, only a small amount of core requirement information of the product, including but not limited to core chip information of the product such as a CPU, a switching chip, a core device and the like, is required to be acquired from the design document, and the required devices and the interconnection relation of device pins do not need to be enumerated in the design document one by one. Compared with the scheme that the schematic diagram needs to be manually written in the prior art, the drawing time of the schematic diagram is shortened, and the drawing efficiency is improved.
As an implementation manner of the embodiment of the present invention, a small amount of core requirement information of a product design, including but not limited to information such as product core chips, product external interface types, and product external interface numbers of a CPU, a switch chip, a core device, and the like, may be filled in a design document according to a predetermined format.
Acquiring product information from a design document, specifically comprising: analyzing the design document according to a set format, and determining a product core chip, a product external interface type and the number of product external interfaces;
in the embodiment of the present invention, the core chips required for product design may be one or more of a CPU, a switch chip, a core device, and the like, and therefore, when the design document is analyzed, the determined product core chips may be one or more, which is only an example to illustrate how to obtain a core chip CBB corresponding to one product core chip in the CBB library, and when there are multiple product core chips, the implementation process of obtaining the corresponding core chip CBB in the CBB library is the same, and details are not repeated here.
In this step, a product CBB corresponding to the product information is obtained in the CBB library, and the product CBB is written into the netlist file according to a predetermined format, which specifically includes: acquiring a core chip CBB corresponding to the core chip from a CBB library according to the material number of the product core chip; in the embodiment of the present invention, if a corresponding core chip CBB is obtained from the CBB library according to the material number of the product core chip, the core chip CBB is selected, and if more than one corresponding core chip CBB is obtained from the CBB library according to the material number of the product core chip, a unique corresponding core chip CBB is determined for the product core chip according to the version number or the interface bus type of each core chip CBB.
As a preferred mode of the embodiment of the present invention, after determining the core chip CBB corresponding to the core chip of the product, the signal interface of the core chip CBB is traversed to determine whether signal connection is required. And if the interface needs to carry out signal connection, giving the name of the signal line to the interface. And determining whether an interface signal line needs a pull-up and pull-down resistor, an AC coupling matching capacitor, a series resistor, a level matching circuit and the like according to the interface attribute of the core chip CBB. And writing the determined related information into a netlist file according to a predetermined format, wherein the netlist file is a text file of txt. The predetermined format is a custom format including a format in which specific information is present in a predetermined position and each specific information is spaced apart by a predetermined symbol.
Determining an interface chip or an interface connector according to the type and the number of external interfaces of the product, and acquiring an interface chip CBB corresponding to the interface chip in a CBB library according to the material number of the interface chip; acquiring an interface connector CBB corresponding to the interface connector in a CBB library according to the material number of the interface connector; in the embodiment of the invention, the interface chips or the interface connectors are determined according to the type of the product external interface, the number of the required interface chips or interface connectors can be calculated according to the number of the product external interfaces after the interface chips or the interface connectors are determined, the interface chip CBB corresponding to the interface chip is obtained in a CBB library according to the material number of the interface chip, if the corresponding interface chip CBB is obtained from the CBB library according to the material number of the interface chip, the interface chip CBB is selected, and if more than one corresponding interface chip CBB is obtained from the CBB library according to the material number of the interface chip, a unique corresponding interface chip CBB is determined for the interface chip according to the version number or the interface bus type of each interface chip CBB. And acquiring the interface connector CBB corresponding to the interface connector in the CBB library according to the material number of the interface connector. And if more than one corresponding interface connector CBB is obtained from the CBB library according to the material number of the interface connector, determining a unique corresponding interface connector CBB for the interface connector according to the version number or the interface bus type of each interface connector CBB. In the embodiment of the present invention, the interface chip CBB includes, but is not limited to, a PHY chip CBB, a UART serial port chip CBB, and the like. Interface connectors CBB include, but are not limited to, RJ45 electrical port CBB, SFP + photocage CBB, USB interface CBB, RST reset interface CBB, and the like.
As an implementation manner of the embodiment of the present invention, in this step, after the core chip CBB, the interface chip CBB, and the interface connector CBB are determined, the related information of the core chip CBB, the interface chip CBB, and the interface connector CBB may be written into the netlist file according to a predetermined format.
As another implementation manner of the embodiment of the present invention, in this step, after the core chip CBB, the interface chip CBB, and the interface connector CBB are determined, signal line pre-connection may be performed among the core chip CBB, the interface chip CBB, and the interface connector CBB, and after signal line level matching and coupling configuration are completed, connection information of the core chip CBB, the interface connector CBB, and the signal line is written into the netlist file according to a predetermined format.
traversing a clock interface of a product CBB, acquiring the clock CBB corresponding to the clock interface from a CBB library, and writing the clock CBB into the netlist file according to a predetermined format, wherein the method specifically comprises the following steps:
traversing the core chip CBB, the interface chip CBB and the clock interface of the interface connector CBB to obtain clock parameter information; the clock parameter information includes, but is not limited to, frequency, jitter, level format, coupling mode, etc.
Acquiring a clock CBB corresponding to the clock interface in a CBB library according to the clock parameter information;
and pre-connecting a signal wire to an input/output interface of the clock CBB, and writing the clock CBB and the peripheral network connection information into a netlist file according to a preset format after completing signal wire level matching and coupling configuration. In the embodiment of the invention, at least one clock CBB including but not limited to crystal oscillators CBB with various frequencies, clock driving CBB and the like is automatically acquired from a CBB library according to the clock parameter information. And signal line pre-connection is respectively carried out on the input and output interfaces of each acquired clock CBB, signal line level matching and coupling configuration are completed, and relevant information of each clock CBB and peripheral network connection information are written into a netlist file according to a preset format.
103, traversing a power interface of the CBB product, acquiring a power CBB corresponding to the power interface from a CBB library, and writing the power CBB into the netlist file according to a preset format;
traversing the power interface of the product CBB, obtaining the power CBB corresponding to the power interface from a CBB library, and writing the power CBB into the netlist file according to a predetermined format, specifically comprising:
traversing the core chip CBB, the interface chip CBB and the power interface of the interface connector CBB, acquiring information such as a voltage value, a current value and a power-on slope of the power interface, and summarizing and calculating to obtain power parameter information; power source CBB herein includes, but is not limited to, DC-DC power source CBB and the like, e.g., 12V to 3.3V power source CBB.
Acquiring a power supply CBB corresponding to the power supply interface in a CBB library according to the power supply parameter information;
after the voltage, the power-on slope and the like of the power supply CBB are pre-configured, signal line pre-connection is carried out on an input/output interface of the power supply CBB;
after the filter capacitor is configured according to the ripple value, the voltage value and the current value of the input and output interface of the power supply CBB, signal line pre-connection is carried out; in the embodiment of the invention, the required filter capacitance value, the number of filter capacitors and the withstand voltage value of the filter capacitors are calculated and matched according to the ripple value, the voltage value and the current value of the input and output interface of the power supply CBB, so that the proper filter capacitors are selected, and the signal lines are pre-connected to the filter capacitors. And writing the power supply CBB and the peripheral network connection information into a netlist file according to a preset format. In the embodiment of the invention, at least one corresponding power supply CBB is automatically selected from a CBB library according to parameter information such as a voltage value, a current value or a power-on slope, signal line pre-connection is carried out on an input/output interface of each power supply CBB after pre-configuration operation such as the voltage value and the power-on slope is carried out on each power supply CBB, required filter capacitance value, filter capacitance quantity and filter capacitance withstand voltage are calculated and matched according to the ripple value, the voltage value and the current value of the input/output interface of each power supply CBB, and the signal line pre-connection is carried out on the filter capacitance after a proper filter capacitance is selected. And finally, writing the matched information of each power supply CBB which is subjected to the pre-configuration operation and the signal line pre-connection and the peripheral network connection information into a netlist file according to a preset format.
And 104, drawing a schematic diagram according to the netlist file. In the embodiment of the invention, the schematic diagram is automatically drawn after the netlist file is analyzed by the drawing tool. The drawing tool may be generated by performing secondary development based on Electronic Design Automation (EDA) or other auxiliary Design software, and may generally select Allegro Design auxiliary Design software of cadence.
The method for drawing the schematic diagram provided by the embodiment of the invention can automatically analyze the product information from the design document, acquire the product CBB corresponding to the product information from the CBB library according to the product information, automatically traverse and count the clock parameter information and the power supply parameter information, and acquire the corresponding clock CBB and the power supply CBB from the CBB library. According to the method provided by the embodiment of the invention, after a small amount of key information of a product in a design document is analyzed, detailed clock parameter information, power supply parameter information and the like are automatically acquired, and then the corresponding clock CBB, power supply CBB and the like are automatically matched from the CBB library, so that the workload of manually counting and calculating the relevant parameters of the clock and the power supply is greatly reduced, and the workload of manually reading a CBB use manual and manually matching the CBB is saved. The labor cost can be effectively saved, the schematic diagram drawing efficiency is improved, and the development cycle of products is accelerated.
For example, in the embodiment of the present invention, a design document written by a word may be interpreted by a program written in C #, and information such as a product core chip, a product external interface type, and a product external interface number may be acquired from the design document, where this part of information is mostly presented in a table form in the design document, as shown in fig. 2, an example core chip list is presented, as shown in fig. 3, an example product external interface list is presented, which is obviously only an example here, and a specific presentation manner is not limited in the embodiment of the present invention, as long as the information can be analyzed.
In the embodiment of the invention, the C # program can acquire the product information according to the table number and the row number in the design document. The CBB library was built by Microsoft SQL Server database software. The CBB parameters are stored in a database. The C # program logs in and reads the CBB parameters in the database through the SQL standard statement, and the CBB parameters are stored in the database in a table manner, as shown in fig. 4, which presents an exemplary CBB parameter table. Firstly, analyzing product information from a design document of a product, wherein the product core chip information is analyzed and obtained from a core chip list shown in fig. 2, the product core chip in fig. 2 includes a CPU and a switch chip, and a core chip CBB corresponding to the CPU is obtained in a CBB library according to a material number of the CPU in the core chip list, # 010253 (the name of CBB is Module _ CPU _ LongSon 2H); in the example, only one corresponding core chip CBB is obtained according to the material numbers of the CPU and the Switch chip, the two obtained core chips CBB are directly selected, and if a set consisting of a plurality of core chips CBBs with the same material number is obtained in the CBB library according to the material number of the CPU or the Switch chip, the core chip CBB corresponding to the Switch chip is obtained in the CBB library (the name of the CBB is Module _ Switch _ CTC 8096). A unique corresponding core chip CBB may be determined for the CPU or switch chip based on the version number or interface bus type of each core chip CBB in the set of core chips CBB. And traversing signal interfaces of the core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H) and the core chip CBB (the name of the CBB is Module _ Switch _ CTC8096) to judge whether signal connection is needed. And if signal connection is needed, giving the name of the signal line to the interface. And determining whether the interface signal line needs a pull-up and pull-down resistor, an AC coupling matching capacitor, a series resistor, a level matching circuit and the like according to the interface attributes of the core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H) and the core chip CBB (the name of the CBB is Module _ Switch _ CTC 8096). And writing the acquired relevant information of the core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H) and the core chip CBB (the name of the CBB is Module _ Switch _ CTC8096) into a netlist file according to a predetermined format, wherein the netlist file is a text file of txt. The predetermined format is a custom format including a format in which specific information is present in a predetermined position and each specific information is spaced apart by a predetermined symbol.
Analyzing and acquiring the type of the product external interface and the quantity information of the product external interfaces from the product external interface list shown in fig. 3, in the example shown in fig. 3, the external interfaces of the product include interface types of gigabit ethernet interfaces GET, and the quantity of the interface types is 4; the interface type is ten gigabit Ethernet optical port XGEF, and the number is 4; the interface type is USB interface, the quantity is 1; the interface type is debug Ethernet DC0, the number is 1; the interface type is a debugging serial port UART, and the number of the interfaces is 1; the interface type is reset interfaces RST, and the number is 1. Acquiring corresponding interface chips CBB and interface connectors CBB in a CBB library based on the interface types in the figure 3, and calculating the number of the required interface chips CBB and interface connectors CBB based on the number of external interfaces of the product in the figure 3; and writing the acquired related information of the interface chip CBB and the interface connector CBB into a netlist file according to a preset format. Signal line pre-connection is carried out on interfaces between a core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H) and the core chip CBB (the name of the CBB is Module _ Switch _ CTC8096), an interface chip CBB and an interface connector CBB, and after signal line level matching and coupling configuration are completed, the signal line is written into a netlist file according to a preset format.
The exe executive program or file is provided for a subsequent drawing tool (such as an embedded TCL script of Allegro Design-aided software) to call so that the drawing tool can finish drawing the schematic diagram.
Traversing the core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H) and the core chip CBB (the name of the CBB is Module _ Switch _ CTC8096), the interface chip CBB and the clock interface of the interface connector CBB to obtain clock parameter information, and writing the obtained clock CBB and peripheral network connection information into a netlist file according to a preset format after obtaining at least one clock CBB including but not limited to a crystal oscillator CBB, a clock drive CBB and the like according to the clock parameter information.
Traversing the power supply interfaces of the core chip CBB (the name of the CBB is Module _ CPU _ LongSon2H), the core chip CBB (the name of the CBB is Module _ Switch _ CTC8096), the interface chip CBB and the interface connector CBB to obtain power supply parameter information including a voltage value, a current value, a power supply slope and the like, calculating each power supply parameter information of the schematic diagram according to the voltage value, the current value, the power supply slope and the like in the power supply parameter information, obtaining the power supply CBB corresponding to the power supply interface from the CBB library, calculating and matching required filter capacitance values, capacitance numbers and capacitance withstand voltage values according to the ripple values, the voltage values and the current values of the input and output interfaces of each power supply CBB, and further performing signal line pre-connection on the filter capacitance after selecting a proper filter capacitance. And finally, writing the matched information of each power supply CBB which is subjected to the pre-configuration operation and the signal line pre-connection and the peripheral network connection information into a netlist file according to a preset format.
After the steps are completed, a complete netlist file can be generated. In an embodiment of the present invention, the netlist file generation may be accomplished by using an exe execution program or file to call the C # program using a TCL script interface as provided by Allegro Design aided Design software. The Allegro Design aided Design software provides a TCL script secondary development interface, and allows the TCL script to call an Allegro Design internal drawing function. After the netlist file is generated, the embedded TCL script of the Allegro Design aided Design software is imported into the netlist file. And calling a drawing function of Allegro Design aided Design software by the TCL script, and drawing according to the netlist file. The automatic drawing of the schematic diagram in the embodiment of the invention mainly comprises the following drawing works of placing the CBB, carrying out CBB interface signal interconnection, naming signal lines, placing peripheral devices and the like.
An embodiment of the present invention further provides a system for drawing a schematic diagram, as shown in fig. 5, the system includes:
an obtaining module 501, configured to obtain product information from a design document;
a matching module 502, configured to obtain a product CBB corresponding to the product information from the universal basic module CBB library, and write the product CBB into the netlist file according to a predetermined format; wherein the predetermined format is a custom format.
The matching module 502 is further configured to traverse a clock interface of the product CBB, obtain a clock CBB corresponding to the clock interface from the CBB library, and write the clock CBB into the netlist file according to a predetermined format;
the matching module 502 is further configured to traverse a power interface of the product CBB, obtain a power CBB corresponding to the power interface from the CBB library, and write the power CBB into the netlist file according to a predetermined format;
and a drawing module 503, configured to draw the schematic diagram according to the netlist file.
The matching module 502 is specifically configured to obtain a corresponding product CBB in the CBB library according to the material number in the product information;
and if more than one product CBB is obtained, obtaining a unique corresponding product CBB according to the version number or the interface bus type of each product CBB.
The obtaining module 501 is specifically configured to analyze a design document according to a predetermined format, and determine a product core chip, a product external interface type, and a product external interface number; wherein the predetermined format is a custom format.
A matching module 502, specifically configured to obtain a core chip CBB corresponding to a core chip in a CBB library according to a material number of the product core chip;
determining an interface chip or an interface connector according to the type and the number of external interfaces of the product, and acquiring an interface chip CBB corresponding to the interface chip in a CBB library according to the material number of the interface chip; acquiring an interface connector CBB corresponding to the interface connector in a CBB library according to the material number of the interface connector;
signal line pre-connection is carried out among the core chip CBB, the interface chip CBB and the interface connector CBB, after signal line level matching and coupling configuration are completed, connection information of the core chip CBB, the interface connector CBB and the signal lines is written into a netlist file according to a preset format.
The matching module 502 is specifically configured to traverse the core chip CBB, the interface chip CBB, and the clock interface of the interface connector CBB to obtain clock parameter information;
acquiring a clock CBB corresponding to a clock interface in a CBB library according to the clock parameter information;
and pre-connecting a signal wire to an input/output interface of the clock CBB, and writing the clock CBB and the peripheral network connection information into a netlist file according to a preset format after completing signal wire level matching and coupling configuration.
The matching module 502 is specifically configured to:
traversing the core chip CBB, the interface chip CBB and the power interface of the interface connector CBB to obtain power parameter information;
acquiring a power supply CBB corresponding to the power supply interface in a CBB library according to the power supply parameter information;
after the voltage and the power-on slope of the power supply CBB are pre-configured, signal line pre-connection is carried out on an input/output interface of the power supply CBB;
after the filter capacitor is configured according to the ripple value, the voltage value and the current value of the input and output interface of the power supply CBB, signal line pre-connection is carried out;
and writing the power supply CBB and the peripheral network connection information into the netlist file according to a preset format.
The system for drawing the schematic diagram provided by the embodiment of the invention can automatically analyze the product information from the design document, acquire the product CBB corresponding to the product information from the CBB library according to the product information, automatically traverse and count the clock parameter information and the power supply parameter information, and acquire the corresponding clock CBB and the power supply CBB from the CBB library. According to the system provided by the embodiment of the invention, after a small amount of key information of a product in a design document is analyzed, detailed clock parameter information, power supply parameter information and the like are automatically acquired, and further, the corresponding clock CBB, power supply CBB and the like are automatically matched from the CBB library, so that the workload of manually counting and calculating the relevant parameters of the clock and the power supply is greatly reduced, and the workload of manually reading a CBB use manual and manually matching the CBB is saved. The labor cost can be effectively saved, the schematic diagram drawing efficiency is improved, and the development cycle of products is accelerated.
An embodiment of the present invention further provides an electronic device, and specifically, the electronic device includes: a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of a method for drawing schematic diagrams provided by any of the above embodiments.
The processor is a control center of the electronic equipment, connects a plurality of parts of the whole terminal equipment by various interfaces and lines, and executes various functions and processes data of the electronic equipment by running or executing software programs and/or modules stored in the memory and calling the data stored in the memory, thereby carrying out the overall monitoring on the electronic equipment. A processor may include one or more processing units; preferably, the processor may integrate a signal processor and an image processor, wherein the application processor mainly processes an operating system, a user interface, an application program, and the like, and the image processor mainly processes an image.
The memory may be used to store software programs as well as various data. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements multiple processes of the wireless network visualization method provided in the foregoing embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium includes, for example, a Random-Access Memory (RAM), a Read-Only Memory (ROM), a Flash Memory (Flash Memory), a Hard Disk Drive (HDD), a Solid-State Drive (SSD), and an optical disc.
It should be noted that, in a specific implementation process, each step executed by the repeater and the controller in the method flow shown in the above figures may be implemented by a processor in a hardware form executing a computer execution instruction in a software form stored in a memory, and details are not described here to avoid repetition. In addition, all the programs corresponding to the actions executed by the authentication server can be stored in the memory of the authentication server in a software form, so that the processor can call and execute the operations corresponding to the modules.
The memory above may include volatile memory, such as random access memory; non-volatile memory, such as read-only memory, flash memory, hard disks, solid state disks, etc.; combinations of the above categories of memory may also be included.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and modules may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the present invention.
Claims (12)
1. A method of drawing a schematic diagram, the method comprising:
acquiring product information from a design document, acquiring a product CBB corresponding to the product information from a universal basic module CBB library, and writing the product CBB into a netlist file according to a preset format;
traversing the clock interface of the product CBB, acquiring the clock CBB corresponding to the clock interface from the CBB library, and writing the clock CBB into the netlist file according to a preset format;
traversing the power supply interface of the product CBB, acquiring the power supply CBB corresponding to the power supply interface from the CBB library, and writing the power supply CBB into the netlist file according to a preset format;
and drawing the schematic diagram according to the netlist file.
2. The method according to claim 1, wherein the obtaining of the product CBB corresponding to the product information in the CBB library specifically comprises:
acquiring a corresponding product CBB in the CBB library according to the material number in the product information;
and if more than one product CBB is obtained, obtaining a unique corresponding product CBB according to the version number or the interface bus type of each product CBB.
3. The method according to claim 1 or 2, wherein the obtaining of product information from a design document specifically comprises: analyzing the design document according to a set format, and determining a product core chip, a product external interface type and the number of product external interfaces; wherein the predetermined format is a custom format.
4. The method according to claim 3, wherein the obtaining of the product CBB corresponding to the product information in the CBB library and the writing of the product CBB into a netlist file according to a predetermined format specifically comprises:
acquiring a core chip CBB corresponding to the product core chip from the CBB library according to the material number of the product core chip;
determining an interface chip or an interface connector according to the type and the number of the product external interfaces, and acquiring an interface chip CBB corresponding to the interface chip in the CBB library according to the material number of the interface chip; acquiring an interface connector CBB corresponding to the interface connector in the CBB library according to the material number of the interface connector;
and signal line pre-connection is carried out among the core chip CBB, the interface chip CBB and the interface connector CBB, and after signal line level matching and coupling configuration are completed, the connection information of the core chip CBB, the interface connector CBB and the signal line is written into the netlist file according to a preset format.
5. The method as claimed in claim 4, wherein traversing the clock interface of the product CBB, obtaining the clock CBB corresponding to the clock interface from the CBB library, and writing the clock CBB into the netlist file according to a predetermined format, specifically includes:
traversing the core chip CBB, the interface chip CBB and the clock interface of the interface connector CBB to obtain clock parameter information;
acquiring a clock CBB corresponding to the clock interface in the CBB library according to the clock parameter information;
and pre-connecting a signal line to an input/output interface of the clock CBB, and writing the clock CBB and the peripheral network connection information into the netlist file according to a preset format after completing signal line level matching and coupling configuration.
6. The method as claimed in claim 4, wherein traversing the power interface of the product CBB, obtaining the power CBB corresponding to the power interface from the CBB library, and writing the power CBB into the netlist file according to a predetermined format, specifically includes:
traversing the core chip CBB, the interface chip CBB and the power interface of the interface connector CBB to obtain power parameter information;
acquiring a power supply CBB corresponding to the power supply interface in the CBB library according to the power supply parameter information;
after the voltage and the power-on slope of the power supply CBB are preset, signal line pre-connection is carried out on an input/output interface of the power supply CBB;
after a filter capacitor is configured according to the ripple value, the voltage value and the current value of the input and output interface of the power supply CBB, signal line pre-connection is carried out;
and writing the power supply CBB and the peripheral network connection information into the netlist file according to a preset format.
7. A system for drawing a schematic diagram, the system comprising:
the acquisition module is used for acquiring product information from the design document;
the matching module is used for acquiring a product CBB corresponding to the product information from a universal basic module CBB library and writing the product CBB into a netlist file according to a preset format;
the matching module is further configured to traverse a clock interface of the product CBB, obtain a clock CBB corresponding to the clock interface from the CBB library, and write the clock CBB into the netlist file according to a predetermined format;
the matching module is further configured to traverse a power interface of the product CBB, obtain a power CBB corresponding to the power interface from the CBB library, and write the power CBB into the netlist file according to a predetermined format;
and the drawing module is used for drawing the schematic diagram according to the netlist file.
8. The system of claim 7, wherein the matching module is specifically configured to obtain a corresponding product CBB in the CBB library according to a material number in the product information;
and if more than one product CBB is obtained, obtaining a unique corresponding product CBB according to the version number or the interface bus type of each product CBB.
9. The system according to claim 7 or 8, wherein the obtaining module is specifically configured to parse the design document according to a predetermined format to determine a product core chip, a product external interface type, and a product external interface number; wherein the predetermined format is a custom format.
10. The system according to claim 9, wherein the matching module is specifically configured to obtain a core chip CBB corresponding to the core chip in the CBB library according to the material number of the product core chip;
determining an interface chip or an interface connector according to the type and the number of the product external interfaces, and acquiring an interface chip CBB corresponding to the interface chip in the CBB library according to the material number of the interface chip; acquiring an interface connector CBB corresponding to the interface connector in the CBB library according to the material number of the interface connector;
and signal line pre-connection is carried out among the core chip CBB, the interface chip CBB and the interface connector CBB, and after signal line level matching and coupling configuration are completed, the connection information of the core chip CBB, the interface connector CBB and the signal line is written into the netlist file according to a preset format.
11. The system according to claim 10, wherein the matching module is specifically configured to traverse the core chip CBB, the interface chip CBB, and the clock interface of the interface connector CBB to obtain clock parameter information;
acquiring a clock CBB corresponding to the clock interface in the CBB library according to the clock parameter information;
and pre-connecting a signal line to an input/output interface of the clock CBB, and writing the clock CBB and the peripheral network connection information into the netlist file according to a preset format after completing signal line level matching and coupling configuration.
12. The system of claim 10, wherein the matching module is specifically configured to:
traversing the core chip CBB, the interface chip CBB and the power interface of the interface connector CBB to obtain power parameter information;
acquiring a power supply CBB corresponding to the power supply interface in the CBB library according to the power supply parameter information;
after the voltage and the power-on slope of the power supply CBB are preset, signal line pre-connection is carried out on an input/output interface of the power supply CBB;
after a filter capacitor is configured according to the ripple value, the voltage value and the current value of the input and output interface of the power supply CBB, signal line pre-connection is carried out;
and writing the power supply CBB and the peripheral network connection information into the netlist file according to a preset format.
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