CN112115659A - High-reliability system packaging integrated chip of redundancy technology - Google Patents
High-reliability system packaging integrated chip of redundancy technology Download PDFInfo
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- CN112115659A CN112115659A CN202010973696.1A CN202010973696A CN112115659A CN 112115659 A CN112115659 A CN 112115659A CN 202010973696 A CN202010973696 A CN 202010973696A CN 112115659 A CN112115659 A CN 112115659A
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- 238000004806 packaging method and process Methods 0.000 title abstract description 14
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- 238000004364 calculation method Methods 0.000 abstract description 5
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- 238000012536 packaging technology Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention relates to a high-reliability system packaging integrated chip of redundancy technology, belonging to the technical field of computer technology and avionics system. The invention realizes redundancy calculation and control functions in a single package. The application reliability of the micro-system chip in a complex environment is improved, and processor failure or calculation errors which often occur in a single processor are avoided. The result voting algorithm is realized by adopting devices with programmable capability such as FPGA and the like, the flexibility of later algorithm updating is improved, and the online upgrading capability and certain real-time data comparison capability are realized. The system has chip-level automatic fault detection and isolation functions. Under the condition of not influencing normal work, the internal failure processor chip is quickly isolated.
Description
Technical Field
The invention belongs to the technical field of computer technology and avionics systems, and particularly relates to a high-reliability system packaging integrated chip of redundancy technology.
Background
With the rapid development of computer technology and avionics systems, digital flight control systems are mostly adopted in flight control systems of airplanes. In order to ensure flight safety, the redundancy technology can effectively improve the reliability and fault-tolerant capability of a flight control computer system, the reliability requirement of the system is very high, and the fault-tolerant capability and survival capability of the system can be fundamentally improved by adopting the redundancy technology. The redundancy technology has the advantages that the core component flight control computer (FLCC) of the redundancy technology mostly adopts a redundancy digital flight control computer, cross comparison voting is adopted among all channel computers of the flight control system, the working mode adopts hot backup, the fault safety capacity is ensured, and fault work or fault degradation work can be realized under certain conditions, so that the safety and the reliability of the system are ensured. On the other hand, the redundancy digital flight control computer can realize the functions of detecting the flight control system on line, finding faults and isolating fault parts.
The system packaging mainly comprises the steps of putting various chip original sheets with complete system functions into one chip package through a 3D packaging technology, realizing the integration of the system functions and the reduction of the volume and the weight, and is a product of high cross fusion of various advanced design and processing technologies such as a chip design technology, a 3D packaging technology, a substrate, a tube shell design, processing and manufacturing technology and the like. In the system packaging process, the chip, the bare chip, the passive device and the like can be used for mixed packaging, more system functions can be realized, and the system packaging method has the characteristics of more flexibility, low cost and the like. The redundancy technology is an important means for improving the task reliability and the safety reliability of the system. By adopting redundancy technology, a system with high reliability or ultrahigh reliability can be formed by components with general reliability, so that the system has wide application in the aspects of aerospace flight control, air traffic control, computer management of bank and communication systems, nuclear power station control and the like.
In order to meet the application environments of various aircrafts and the like in recent years and simultaneously give consideration to the basic reliability of the system, the redundancy number of the computer cannot be increased without limit, and factors in the aspects of reliability, weight, volume, cost, realization of redundancy management and the like need to be balanced, so that the redundancy technology is combined with the system packaging integration technology, the limitation of the volume and the weight of the whole aircraft is solved, and the reliability of a control module is greatly improved under the condition of realizing redundancy design. As semiconductor device production lines mature more and more, SiP costs are also lower and lower.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide a high-reliability redundancy chip architecture design method suitable for system packaging integrated chip application, and computer redundancy calculation and control at a micro system chip level are realized.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a high reliability system package integrated chip of redundancy technology, comprising: the processor or the control unit, the result voting algorithm circuit and the failure processor isolation execution circuit;
the processor or the control unit is an odd number of independently operated bare chips of the processor or the control unit;
the result voting algorithm circuit is realized by adopting an FPGA chip or a CPLD chip and is used for receiving the output results of the bare chips of the processors or the control units and determining the final program execution result by using a voting algorithm, and the result voting algorithm circuit is also used for detecting whether the bare chips of the processors or the control units have failure problems or not;
the failure processor isolation execution circuit is used for isolating a failure processor or control unit bare chip, when the result voting algorithm circuit finds that the processor or control unit bare chip has a fault, a control signal is output to the failure processor isolation execution circuit, and the failure processor isolation execution circuit cuts off a working power supply signal of a fault processor to realize isolation of the failure processor or control unit bare chip.
Preferably, the bare chips of the processors or the control units share the same data source and clock signals, run the same program, and output the program execution results independently, and the bare chips of the processors or the control units work independently and are equivalent to one processor or control unit externally.
Preferably, the result voting algorithm circuit is specifically configured to determine whether the bare chip of the processor or the control unit has a fault by detecting a difference between an output result and a result of the bare chip of the other processor or the control unit for multiple times.
Preferably, each processor or control unit bare chip is independent of the data path of the result voting algorithm circuit.
Preferably, the failure processor isolation execution circuit is placed in an FPGA chip or is implemented by using an independent control chip, and the failure processor isolation execution circuit is placed inside the packaged integrated chip or not depending on whether the power shutdown execution circuit during failure isolation is placed inside the packaged integrated chip or not.
Preferably, the power supply of the bare chip of the plurality of processors or control units is an independent and separated power plane when the packaged integrated chip is designed, and when the voting circuit finds that the processor is in an abnormal state, the power supply of the abnormal processor chip is disconnected by outputting a control signal to the outside of the chip.
Preferably, the power supply circuit of the plurality of bare chips of the processor or the control unit includes a plurality of power supply switches.
Preferably, the power supply switches of the bare chips of the plurality of processors or control units are implemented by high-power MOS tubes.
Preferably, the failure processor isolation execution circuit is used for performing isolation operation on the failure processor or control unit bare chip according to the control signal output by the result voting algorithm circuit, and the power supply disconnection of the failure processor or control unit bare chip is realized by controlling the power supply switch.
Preferably, the power switches of the bare chips of the plurality of processors or control units are placed inside the package or outside the package.
(III) advantageous effects
The invention realizes the redundancy calculation and control functions in single package, improves the application reliability of the micro-system chip in a complex environment, and avoids processor failure or calculation errors frequently occurring in a single processor. The result voting algorithm is realized by adopting devices with programmable capability such as FPGA and the like, the flexibility of later algorithm updating is improved, and the online upgrading capability and certain real-time data comparison capability are realized. The system has chip-level automatic fault detection and isolation functions. Under the condition of not influencing normal work, the internal failure processor chip is quickly isolated.
Drawings
FIG. 1 is a high reliability system package integrated chip architecture diagram based on redundancy techniques of the present invention;
FIG. 2 is a schematic diagram of the fault isolation and processor power supply of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The theoretical basis of the invention is that a plurality of identical processors are used for simultaneously obtaining identical data, operating identical programs and outputting respective operation results. And the final output result is controlled by a plurality of results by using a voting program, so that the problems of operation errors, failures and the like which may occur to a single processor are avoided, and the reliability level of the chip in the core key task is improved.
The internal architecture of the high-reliability system packaging integrated chip of the redundancy technology is shown in figure 1, and comprises a processor or a control unit, a result voting algorithm circuit and a failure processor isolation execution circuit, wherein a power supply isolation design is adopted in the design of a packaging integrated substrate to realize the redundancy design at the packaging level of a micro system, and the processor or the control unit is used for realizing the core function of the chip; the result voting algorithm circuit is used for outputting a final execution result; and the failure processor isolation execution circuit is used for quickly isolating the failure processor.
An odd number of independently operating bare chips of the processors or the control units are packaged and integrated in the chip architecture, and the processors are placed as close as possible in the package in order to ensure the operating consistency of the processors. The number of the bare chips of the processor or the control unit is odd, and the uniqueness of output result voting is mainly ensured on the physical structure. The bare chips of the processors or the control units share the same data source and clock signals, run the same program and respectively and independently output the program execution result. The operation of each bare chip of the processor or the control unit is mutually independent and is externally equivalent to a processor or a control unit.
The result voting algorithm circuit is realized by adopting an FPGA chip or a CPLD chip and is used for receiving the output results of a plurality of bare chips of the processors or the control units, determining the final program execution result by using a voting algorithm, simultaneously detecting whether the bare chips of the processors or the control units have failure problems or not by the result voting algorithm circuit, and judging whether the bare chips of the processors or the control units have failure or not by detecting the difference between the output results and the results of the bare chips of other processors or the control units for a plurality of times. The result voting algorithm is realized by adopting devices with programmable capability such as FPGA, CPLD and the like, so that the flexibility of later algorithm updating is improved, and the online upgrading capability and certain real-time data comparison capability are realized. Each processor or control unit bare chip and the data channel of the result voting algorithm circuit are independent, and a parallel port or serial communication protocol is adopted and mainly depends on the requirement of external control.
The failure processor isolation execution circuit is used for rapidly isolating the failure processor. When finding that a certain processor has a fault, the result voting algorithm circuit outputs a control signal to the failure processor isolation execution circuit, and the circuit cuts off a working power supply signal of the failure processor to realize the isolation of the failure processor. The failure processor isolation execution circuit can be placed in an FPGA chip or an independent control chip according to the complexity of implementation, and is mainly determined whether a power supply shutdown execution circuit during failure isolation is placed in a packaged integrated chip or not.
FIG. 2 is a schematic diagram of package failure isolation and processor power supply according to the present invention. When the voting circuit finds that the processor is in an abnormal state, the power supply of the abnormal processor chip can be disconnected by outputting a control signal to the outside of the chip. The power supply circuit comprises a plurality of power supply switches, the power supply switches are generally realized by adopting high-power MOS (metal oxide semiconductor) tubes, can be placed inside the package or outside the package, and are connected with a uniform external power supply. The failure processor isolation execution circuit is used for carrying out isolation operation on the failure processor or the control unit bare chip according to the control signal output by the result voting algorithm circuit, and the power supply disconnection of the failure processor or the control unit bare chip is realized by controlling the power supply switch.
Therefore, the invention realizes the high reliability of the task execution of the system packaging integrated chip in the complex environment, and can effectively avoid the system function failure caused by the processor failure. Meanwhile, the fault processor can be effectively and quickly isolated from the whole system by adopting independent power supply control in packaging, so that the reliability of the system is improved, and the seamless link of task execution switching is improved.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A highly reliable system-in-package integrated chip for redundancy techniques, comprising: the processor or the control unit, the result voting algorithm circuit and the failure processor isolation execution circuit;
the processor or the control unit is an odd number of independently operated bare chips of the processor or the control unit;
the result voting algorithm circuit is realized by adopting an FPGA chip or a CPLD chip and is used for receiving the output results of the bare chips of the processors or the control units and determining the final program execution result by using a voting algorithm, and the result voting algorithm circuit is also used for detecting whether the bare chips of the processors or the control units have failure problems or not;
the failure processor isolation execution circuit is used for isolating a failure processor or control unit bare chip, when the result voting algorithm circuit finds that the processor or control unit bare chip has a fault, a control signal is output to the failure processor isolation execution circuit, and the failure processor isolation execution circuit cuts off a working power supply signal of a fault processor to realize isolation of the failure processor or control unit bare chip.
2. The chip of claim 1, wherein the processor or control unit bare chips share the same data source and clock signal, and run the same program, and output the program execution result independently, and the operation of each processor or control unit bare chip is independent and equivalent to one processor or control unit.
3. The chip of claim 2, wherein the result voting algorithm circuit is specifically configured to determine whether the bare chip of the processor or the control unit has a failure by detecting a difference between the output result and the result of the bare chip of the other processor or the control unit a plurality of times.
4. The chip of claim 3, wherein each processor or control unit die is independent of a data channel of the result voting algorithm circuit.
5. The chip of claim 1, wherein the failing processor isolation execution circuit is placed in an FPGA chip or implemented using a separate control chip, depending on whether the power down execution circuit at the time of failure isolation is placed inside the packaged integrated chip.
6. The chip of claim 5, wherein the power supply of the plurality of bare chips of the processors or the control units is an independent and separate power plane when the packaged integrated chip is designed, and when the voting circuit finds that the processor is in an abnormal state, the power supply disconnection of the abnormal processor chip is realized by outputting a control signal to the outside of the chip.
7. The chip of claim 6, wherein the power supply circuitry of the plurality of processor or control unit die comprises a plurality of power supply switches.
8. The chip of claim 7, wherein the power switches of the bare chip of the plurality of processors or control units are implemented by high-power MOS transistors.
9. The chip of claim 7, wherein the failing processor isolation execution circuit is configured to perform an isolation operation on the failing processor or control unit bare chip according to the control signal output by the result voting algorithm circuit, and the power supply switch is controlled to disconnect the power supply of the failing processor or control unit bare chip.
10. The chip of claim 8, wherein the power switches of the plurality of bare chips of processors or control units are placed inside the package or outside the package.
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| CN202010973696.1A CN112115659A (en) | 2020-09-16 | 2020-09-16 | High-reliability system packaging integrated chip of redundancy technology |
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| JP2006019663A (en) * | 2004-07-05 | 2006-01-19 | Denso Corp | Bare chip set, bare chip inspection method, bare chip, and bare chip mounting circuit board |
| CN103869781A (en) * | 2014-03-14 | 2014-06-18 | 北京航空航天大学 | Non-similar three-redundancy onboard electric load management center |
| CN105094007A (en) * | 2014-05-22 | 2015-11-25 | 瑞萨电子株式会社 | Microcontroller and electronic control device using the same |
| CN106933094A (en) * | 2017-03-01 | 2017-07-07 | 北京天恒长鹰科技股份有限公司 | A kind of pair of airborne flight control computer of remaining |
| CN108228391A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of LockStep processors and management method |
| CN111209246A (en) * | 2019-12-25 | 2020-05-29 | 北京时代民芯科技有限公司 | Micro programmable on-chip computer based on multi-chip packaging technology |
-
2020
- 2020-09-16 CN CN202010973696.1A patent/CN112115659A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019663A (en) * | 2004-07-05 | 2006-01-19 | Denso Corp | Bare chip set, bare chip inspection method, bare chip, and bare chip mounting circuit board |
| CN103869781A (en) * | 2014-03-14 | 2014-06-18 | 北京航空航天大学 | Non-similar three-redundancy onboard electric load management center |
| CN105094007A (en) * | 2014-05-22 | 2015-11-25 | 瑞萨电子株式会社 | Microcontroller and electronic control device using the same |
| CN108228391A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of LockStep processors and management method |
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Application publication date: 20201222 |