CN112115096A - Data transmission control method based on embedded microprocessor - Google Patents
Data transmission control method based on embedded microprocessor Download PDFInfo
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- CN112115096A CN112115096A CN202010973680.0A CN202010973680A CN112115096A CN 112115096 A CN112115096 A CN 112115096A CN 202010973680 A CN202010973680 A CN 202010973680A CN 112115096 A CN112115096 A CN 112115096A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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Abstract
The invention relates to a data transmission control method based on an embedded microprocessor, belonging to the technical field of data transmission of digital chips. The invention separates the DMA starting transmission instruction operation and the DMA interruption state register clear operation function from the microprocessor, and designs a DMA control module to complete the data transmission function. The microprocessor only needs to configure the DMA control module with the transmission parameters (such as the configuration parameters of the byte number of single transmission, the initial address of a data source, the initial address of a data destination and the like) required by the DMA when the system is initialized, and when the microprocessor system works, the starting transmission and operation of the DMA and the clearing operation of the DMA interrupt state register are all completed by the DMA control module, and the microprocessor is released from the control of the DMA, so that the working efficiency of the microprocessor is improved.
Description
Technical Field
The invention belongs to the technical field of data transmission of digital chips, and particularly relates to a data transmission control method based on an embedded microprocessor.
Background
The embedded microprocessor is the core of the embedded micro-system and is a hardware unit for controlling and assisting the system operation, and the embedded microprocessor is directly related to the performance of the whole embedded micro-system. The embedded microprocessor is evolved from a CPU in a general-purpose computer, has higher performance, only retains functional hardware closely related to the embedded application in practical embedded application, removes other redundant functional parts, has the advantages of small volume, low cost, high reliability and the like compared with an industrial control computer, and is widely applied at present. DMA (direct memory access) is an indispensable important component in a modern processor system, realizes a large-batch data transmission function, and does not need a microprocessor to participate in transmission operation in the transmission process, so that the operations of fetching and sending numbers and the like of the microprocessor are omitted. DMA can meet the requirement of high-speed I/O equipment and is beneficial to the exertion of microprocessor efficiency.
When the DMA works in the microprocessor system, the data transmission process does not need the participation of the microprocessor every time, but the DMA starts transmission but needs the microprocessor to issue a start transmission instruction, after the transmission is finished, the DMA feeds back the finishing state to the microprocessor, and then the microprocessor resets the relevant register state of the DMA. Although the proportion of the time occupied by the issuing of the starting instruction and the response of the transmission ending action of the microprocessor in each DMA data transmission process is small, frequent DMA data transmission work can frequently interrupt the microprocessor to influence other operation processes of the microprocessor, and the working efficiency of the microprocessor can be reduced under the application scene that the DMA data transmission is very frequent.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to improve the working efficiency of a microprocessor in the data transmission control process.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a data transmission control system, including: the data transmission system is realized and comprises an embedded microprocessor module, a DMA control module, a data processing module, an entry cache module, a DMA module, a DDR cache module and a DMA interrupt clearing module;
the embedded microprocessor module is used for issuing initialization parameters of DMA data transmission to a configuration register module of the DMA control module after power-on initialization;
the data processing module is used for processing the entry data according to the requirement and storing the entry data into the entry cache module;
the entry cache module is used for sending a data transmission request to a transmission request processing module of the DMA control module when the data stored in the entry cache module reaches the single data volume of the DMA transport;
the DMA control module is used for issuing data transmission parameters to the DMA module according to the initialization parameters of the configuration register module and sending data transmission starting instructions when the transmission request processing module receives the data transmission request;
the DMA module is used for carrying the data in the entry cache module to the DDR cache module according to the data transmission parameters after receiving the data transmission starting instruction; after the data transmission is finished, sending a data transmission finishing interrupt signal to a DMA interrupt response module of the DMA control module;
the DMA control module is also used for accumulating the destination address of the configuration register module by one data length after receiving the data transmission completion interrupt signal by using the DMA interrupt response module and simultaneously informing the DMA interrupt clearing module;
the DMA interruption clearing module is used for clearing the interruption state register of the DMA module.
Preferably, the DMA control module comprises a configuration register module.
Preferably, the DMA control module further comprises a transmission request processing module.
Preferably, the DMA control module further comprises a DMA interrupt response module.
The invention also provides a data transmission method based on the embedded microprocessor, which is realized based on the system and comprises the following steps:
1) the embedded microprocessor module sends initialization parameters of DMA data transmission to a configuration register module of the DMA control module;
2) the data processing module processes the entry data according to the requirement and stores the entry data into the entry cache module;
3) when the data stored in the entry cache module reaches the single data volume of DMA (direct memory access) transportation, sending a data transmission request to a transmission request processing module of the DMA control module;
4) the transmission request processing module receives the data transmission request, issues data transmission parameters to the DMA module according to the initialization parameters of the configuration register module and sends a data transmission starting instruction;
5) the DMA module receives a data transmission starting instruction and carries data in the entry cache module to the DDR cache module according to the data transmission parameters;
6) after the DMA module finishes data transmission, sending a data transmission completion interrupt signal to a DMA interrupt response module of the DMA control module;
7) the DMA interrupt response module receives a data transmission completion interrupt signal, accumulates the destination address of the configuration register module by one data length, and simultaneously informs the DMA interrupt clearing module;
8) the DMA interruption clearing module clears the interruption state register of the DMA module.
Preferably, the initialization parameter includes a data transfer source address.
Preferably, the initialization parameter further includes a destination address.
Preferably, the initialization parameter further includes a data length.
The invention also provides an application of the system in the technical field of digital chip data transmission.
The invention also provides an application of the method in the technical field of digital chip data transmission.
(III) advantageous effects
The invention separates the DMA starting transmission instruction operation and the DMA interruption state register clear operation function from the microprocessor, and designs a DMA control module to complete the data transmission function. The microprocessor only needs to configure the DMA control module with the transmission parameters (such as the configuration parameters of the byte number of single transmission, the initial address of a data source, the initial address of a data destination and the like) required by the DMA when the system is initialized, and when the microprocessor system works, the starting transmission and operation of the DMA and the clearing operation of the DMA interrupt state register are all completed by the DMA control module, and the microprocessor is released from the control of the DMA, so that the working efficiency of the microprocessor is improved.
Drawings
FIG. 1 is a block diagram of a data transmission control method before improvement
FIG. 2 is a block diagram of an improved data transmission control method of the present invention;
FIG. 3 is a block diagram of a DMA control module in the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The invention uses the DMA control module with independent function, separates the starting function and the processing function after the transmission from the microprocessor module to form the DMA control module, does not occupy the processing period of the microprocessor when the data is transmitted, receives the data transmission request of the upstream module, and starts the DMA module to finish the transmission of the data to the DDR cache module. Therefore, the data transmission through the DMA is completed without interrupting the work of the microprocessor module.
Fig. 1 shows a data transmission control method before improvement.
Method before improvement:
1) the data processing module processes the entry data according to the requirement and stores the entry data into the entry cache module;
2) when the data stored in the entry cache module reaches the single data volume of DMA (direct memory access) transportation, sending a data transmission request to the embedded microprocessor module;
3) the embedded microprocessor module receives the data transmission request, issues data transmission parameters to the DMA module and sends a data transmission starting instruction;
4) the DMA module receives a data transmission starting instruction and carries data in the entry cache module to the DDR cache module according to the data transmission parameters;
5) after the DMA module finishes data transmission, sending a data transmission finishing interrupt signal to the embedded microprocessor module;
6) the embedded microprocessor module receives the data transmission completion interrupt signal and clears the interrupt status register of the DMA module.
Fig. 2 is a block diagram of an improved data transmission control method, the improved part is a part in a dashed box, and an implementation block diagram of a DMA control module in the dashed box is shown in fig. 3.
The improved method is a data transmission method for reducing the pressure of the embedded microprocessor, which is realized based on a data transmission system, wherein the system comprises an embedded microprocessor module, a DMA control module, a data processing module, an entry cache module, a DMA module, a DDR cache module and a DMA interrupt clearing module;
the embedded microprocessor module is used for issuing initialization parameters of DMA data transmission to a configuration register module of the DMA control module after power-on initialization, wherein the initialization parameters comprise a data carrying source address, a destination address and a data length;
the data processing module is used for processing the entry data according to the requirement and storing the entry data into the entry cache module;
the entry cache module is used for sending a data transmission request to a transmission request processing module of the DMA control module when the data stored in the entry cache module reaches the single data volume of the DMA transport;
the DMA control module is used for issuing data transmission parameters to the DMA module according to the initialization parameters (data handling source address, destination address and data length) of the configuration register module and sending a data transmission starting instruction when the transmission request processing module receives a data transmission request;
the DMA module is used for carrying the data in the entry cache module to the DDR cache module according to the data transmission parameters after receiving the data transmission starting instruction; after the data transmission is finished, sending a data transmission finishing interrupt signal to a DMA interrupt response module of the DMA control module;
the DMA control module is also used for accumulating the destination address of the configuration register module by one data length after receiving the data transmission completion interrupt signal by using the DMA interrupt response module and simultaneously informing the DMA interrupt clearing module;
the DMA interruption clearing module is used for clearing the interruption state register of the DMA module.
The data transmission method implemented based on the above system includes the following steps:
1) the method comprises the following steps that power-on initialization is carried out, and an embedded microprocessor module issues initialization parameters (including a data carrying source address, a destination address and a data length) of DMA data transmission to a configuration register module of a DMA control module;
2) the data processing module processes the entry data according to the requirement and stores the entry data into the entry cache module;
3) when the data stored in the entry cache module reaches the single data volume of DMA (direct memory access) transportation, sending a data transmission request to a transmission request processing module of the DMA control module;
4) the transmission request processing module receives the data transmission request, issues data transmission parameters to the DMA module according to the initialization parameters (data handling source address, destination address and data length) of the configuration register module and sends a data transmission starting instruction;
5) the DMA module receives a data transmission starting instruction and carries data in the entry cache module to the DDR cache module according to the data transmission parameters;
6) after the DMA module finishes data transmission, sending a data transmission completion interrupt signal to a DMA interrupt response module of the DMA control module;
7) the DMA interrupt response module receives a data transmission completion interrupt signal, accumulates the destination address of the configuration register module by one data length, and simultaneously informs the DMA interrupt clearing module;
8) the DMA interruption clearing module clears the interruption state register of the DMA module.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A data transmission control system, comprising: the data transmission system is realized and comprises an embedded microprocessor module, a DMA control module, a data processing module, an entry cache module, a DMA module, a DDR cache module and a DMA interrupt clearing module;
the embedded microprocessor module is used for issuing initialization parameters of DMA data transmission to a configuration register module of the DMA control module after power-on initialization;
the data processing module is used for processing the entry data according to the requirement and storing the entry data into the entry cache module;
the entry cache module is used for sending a data transmission request to a transmission request processing module of the DMA control module when the data stored in the entry cache module reaches the single data volume of the DMA transport;
the DMA control module is used for issuing data transmission parameters to the DMA module according to the initialization parameters of the configuration register module and sending data transmission starting instructions when the transmission request processing module receives the data transmission request;
the DMA module is used for carrying the data in the entry cache module to the DDR cache module according to the data transmission parameters after receiving the data transmission starting instruction; after the data transmission is finished, sending a data transmission finishing interrupt signal to a DMA interrupt response module of the DMA control module;
the DMA control module is also used for accumulating the destination address of the configuration register module by one data length after receiving the data transmission completion interrupt signal by using the DMA interrupt response module and simultaneously informing the DMA interrupt clearing module;
the DMA interruption clearing module is used for clearing the interruption state register of the DMA module.
2. The system of claim 1, wherein the DMA control module comprises a configuration register module.
3. The system of claim 1, wherein the DMA control module further comprises a transfer request processing module.
4. The system of claim 1, wherein the DMA control module further comprises a DMA interrupt response module.
5. An embedded microprocessor based data transmission method implemented based on the system of any one of claims 1 to 4, comprising the following steps:
1) the embedded microprocessor module sends initialization parameters of DMA data transmission to a configuration register module of the DMA control module;
2) the data processing module processes the entry data according to the requirement and stores the entry data into the entry cache module;
3) when the data stored in the entry cache module reaches the single data volume of DMA (direct memory access) transportation, sending a data transmission request to a transmission request processing module of the DMA control module;
4) the transmission request processing module receives the data transmission request, issues data transmission parameters to the DMA module according to the initialization parameters of the configuration register module and sends a data transmission starting instruction;
5) the DMA module receives a data transmission starting instruction and carries data in the entry cache module to the DDR cache module according to the data transmission parameters;
6) after the DMA module finishes data transmission, sending a data transmission completion interrupt signal to a DMA interrupt response module of the DMA control module;
7) the DMA interrupt response module receives a data transmission completion interrupt signal, accumulates the destination address of the configuration register module by one data length, and simultaneously informs the DMA interrupt clearing module;
8) the DMA interruption clearing module clears the interruption state register of the DMA module.
6. The method of claim 5, wherein the initialization parameters comprise a data transport source address.
7. The method of claim 6, wherein the initialization parameters further comprise a destination address.
8. The method of claim 7, wherein the initialization parameters further comprise a data length.
9. Use of a system according to any of claims 1 to 4 in the field of digital chip data transmission.
10. Use of the method according to any one of claims 5 to 8 in the field of digital chip data transmission technology.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113449347A (en) * | 2021-09-01 | 2021-09-28 | 飞腾信息技术有限公司 | Microprocessor, data processing method, electronic device, and storage medium |
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| CN104932994A (en) * | 2015-06-17 | 2015-09-23 | 青岛海信信芯科技有限公司 | Data processing method and device |
| CN105786735A (en) * | 2016-02-19 | 2016-07-20 | 大唐微电子技术有限公司 | Direct memory access DMA controller and data access method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113449347A (en) * | 2021-09-01 | 2021-09-28 | 飞腾信息技术有限公司 | Microprocessor, data processing method, electronic device, and storage medium |
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