CN112104066A

CN112104066A - Data power-down holding circuit and equipment of static random access memory

Info

Publication number: CN112104066A
Application number: CN202011052023.9A
Authority: CN
Inventors: 王贤瑾; 陈超; 邓其生
Original assignee: Kyland Technology Co Ltd
Current assignee: Kyland Technology Co Ltd
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2020-12-18

Abstract

The invention provides a data power-down holding circuit of a static random access memory, which comprises a voltage monitoring unit, a logic control unit, a key signal protection unit, a power supply switching unit and a power supply unit, wherein the power supply unit comprises a power supply module and a standby power supply module; the voltage monitoring unit is connected with the power supply module of the power supply unit and is used for monitoring a voltage signal output by the power supply module; the logic control unit is connected with the voltage monitoring unit and used for generating a control enabling signal according to the received level signal; the key signal protection unit is connected with the logic control unit; the power supply switching unit is connected with the logic control unit and the power supply unit and controls the power supply module or the standby power supply module of the power supply unit to switch power supply. The method can effectively avoid the risk that the data of the static random access memory is easy to lose in the power failure process, and simultaneously, the data in the static random access memory is prevented from being lost due to the instability of key signals in the power failure process.

Description

Data power-down holding circuit and equipment of static random access memory

Technical Field

The invention relates to the technical field of data storage, in particular to a data power-down holding circuit and a data power-down holding device of a static random access memory.

Background

Random access memory is a commonly used and indispensable information storage device in various microprocessor-based electronic devices. In the field of data storage, a Static Random-Access Memory (SRAM) is usually used for data storage, and the SRAM has the advantages of high speed, no limitation on the number of read and write operations, and the disadvantage that power-down data cannot be stored, so that power must be supplied to the SRAM alone when the system is powered down.

In the conventional power-down protection design, a power supply of a system is used for supplying power to a static random access memory when the system is powered on and a battery on a mainboard is used for supplying power to the static random access memory when the system is powered off in a mode of adding a mainboard battery and an external circuit, so that data are protected from being lost when the system is powered off. However, the external circuit configured in this design is generally low in reliability, and does not protect key signals such as main control signals in the electronic device, and when the electronic device is powered on or powered off, interference signals may interfere with the key signals to input data in the sram, so that the data in the sram is lost, and the life of the motherboard battery is usually only one to two years, and the data needs to be processed when the battery is replaced, thereby causing unnecessary troubles to a user.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide a data power-down holding circuit and device for a static random access memory, which can effectively avoid the risk that data of the static random access memory is easily lost during a power-down process, and simultaneously prevent data in the static random access memory from being lost due to instability of a key signal during the power-down process.

The invention adopts the technical scheme that the data power-down maintaining circuit of the static random access memory comprises a voltage monitoring unit, a logic control unit, a key signal protection unit, a power supply switching unit and a power supply unit, wherein the power supply unit comprises a power supply module and a standby power supply module and is used for supplying power to the key signal protection unit and the static random access memory;

the voltage monitoring unit is connected with the power supply module of the power supply unit and is used for monitoring the voltage signal output by the power supply module and outputting a level signal according to the monitored voltage signal;

the logic control unit is connected with the voltage monitoring unit and used for generating a control enabling signal according to the received level signal and respectively outputting the control enabling signal to the key signal protection unit and the power supply switching unit;

the key signal protection unit is connected with the logic control unit and is used for controlling the on-off of a key signal output to the static random access memory according to a received control enabling signal;

the power supply switching unit is connected with the logic control unit and the power supply unit and used for outputting a power supply switching signal according to the received control enabling signal, controlling the switching of the power supply module or the standby power supply module of the power supply unit and supplying power to the key signal protection unit and the static random access memory.

Therefore, the invention monitors the voltage signal output by the power supply unit in real time through the voltage monitoring unit and outputs a corresponding level signal according to the monitored voltage signal, the high and low of the level signal can control the conduction of the logic control unit at the rear end, when the power failure occurs, the level detection unit outputs a high level signal, the logic control unit is conducted and outputs a control enabling signal to the key signal protection unit and the power supply switching unit at the rear end, the key signal protection unit is controlled to stop the interference input of the key signal of the static random access memory, the power supply switching unit is controlled to switch the power supply output mode of the power supply unit, the power supply output is switched to be output by the standby battery module or the capacitor module, thereby ensuring that the power supply mode is switched in time when the power is off, ensuring that the data of the static random access memory is not lost, meanwhile, the data in the static random access memory is prevented from being lost due to the instability of key signals in power failure.

Preferably, the voltage monitoring unit comprises a reset chip;

the power end of the reset chip is connected with the power module and is used for collecting voltage signals; the grounding end of the reset chip is grounded, and the power end and the grounding end are connected in series with a capacitor;

when the voltage signal that the power end of this reset chip gathered is normal supply voltage, the output of this reset chip exported high level signal, and when the voltage signal who gathers was less than normal supply voltage, this output exported low level signal.

By above, this voltage monitoring unit utilizes the reset of the chip that resets to fall the function and realizes the monitoring of voltage, through connecting and monitoring the voltage that power module exported, when the voltage is normal, this chip that resets exports high level signal, and when power module falls down, when the voltage is less than normal voltage, this chip that resets exports low level signal.

Preferably, the logic control unit includes:

the first logic control circuit is connected with the key signal protection unit, and the second logic control circuit is connected with the power supply switching unit;

when receiving a low level signal, the first logic control circuit outputs a first control enabling signal to the key signal protection unit, and the first control enabling signal is used for driving the key signal protection unit to be locked to stop the input of a key signal;

when receiving the low level signal, the second logic control circuit outputs a second control enabling signal to the power supply switching unit for driving the power supply switching unit to switch to the standby power supply module for supplying power.

According to the technical scheme, the logic control unit outputs different control enabling signals to the key signal protection unit and the power supply switching unit at the rear end according to high and low level signals output by the voltage monitoring unit, when power failure occurs and the voltage monitoring unit outputs low level signals, a first logic control circuit and a second logic control circuit of the logic control unit are both disconnected, the control enabling signals are output to the corresponding key signal protection unit and the corresponding power supply switching unit, the key signal protection unit is driven to stop inputting of key signals, and the power supply switching unit is driven to be switched to the standby power supply module for supplying power.

Preferably, the first logic control circuit comprises a first NPN triode;

the base electrode of the first NPN triode is connected with the output end of the voltage monitoring unit after being connected with a first resistor in series, the collector electrode of the first NPN triode is connected with a second resistor in series and is connected with a power supply, a third resistor is further connected between the collector electrode and the base electrode in series, and the emitting electrode of the first NPN triode is grounded;

the collector outputs a first control enabling signal to the key signal protection unit when the first NPN triode is conducted.

According to the characteristics of the NPN triode, when the base is at a high level, the NPN triode is conducted, the power supply of the collector is pulled down at the moment, the control enabling signal of the low level is output, the key signal protection unit at the rear end normally outputs the key signal to the static random access memory, when power failure occurs, the NPN triode is disconnected when the base is at the low level, the control enabling signal of the high level is output by the collector at the moment, the key signal protection unit at the rear end is locked, and the key signal is stopped being output to the static random access memory.

Preferably, the second logic control circuit comprises a second NPN triode and a third NPN triode;

the base electrode of the second NPN triode is connected with the output end of the voltage monitoring unit after being connected with a fourth resistor in series, the collector electrode of the second NPN triode is connected with a fifth resistor in series and is connected with a power supply, a sixth resistor is also connected between the collector electrode and the base electrode in series, and the emitting electrode of the second NPN triode is grounded;

the base electrode of the third NPN triode is connected with the collector electrode of the second NPN triode, the collector electrode of the third NPN triode is connected with a seventh resistor in series and is connected with the power supply, and the emitting electrode of the third NPN triode is grounded;

and the collector of the third NPN triode outputs a second control enabling signal to the power supply switching unit when being conducted.

According to the characteristics of the NPN triodes, when the base of the second NPN triode is at a high level, the second NPN triode is conducted, the base outputs a low level, the third NPN triode is disconnected, a high level control enabling signal is output, the power supply switching unit at the rear end still keeps supplying power for the power supply module, when power failure occurs, the base of the second NPN triode is at a low level, the second NPN triode is disconnected, the base outputs a high level, the third NPN triode is conducted, a low level control enabling signal is output, and the power supply switching unit at the rear end is controlled to be switched to the standby power supply module to supply power.

Preferably, the key signal protection unit comprises a tri-state gate trigger;

the input end of the tri-state gate trigger is connected with an input source of a key signal, the control end of the tri-state gate trigger is connected with the output end of the logic control unit, the power supply end of the tri-state gate trigger is connected with the power supply unit, and the output end of the tri-state gate trigger is connected with the static random access memory.

The key signal protection unit utilizes the characteristics of the tri-state gate trigger, the control enabling signal output by the front-end logic control unit is used as a driving signal of the tri-state gate trigger, when the control enabling signal is a low-level signal, the key signal passes through the tri-state gate trigger to the static random access memory, and when power failure occurs and the control enabling signal is a high-level signal, the tri-state gate trigger is locked to output a high-resistance state, and the input of the key signal to the static random access memory is stopped.

Preferably, the power switching unit includes a P-channel MOS transistor;

the grid electrode of the MOS tube is connected with the output end of the logic control unit, the source electrode is connected with a voltage stabilizing circuit in series and is connected with the standby power supply module, the drain electrode is a power supply output end, the drain electrode is connected with a voltage stabilizing diode in series and is connected with the power supply module, and the drain electrode is also connected with a filter capacitor in series and is grounded.

By last, this power switching unit utilizes the characteristic of P channel MOS pipe, and the control enable signal of being exported by front end logic control unit is as the drive signal of this MOS pipe, and when control enable signal was high level signal, this MOS pipe disconnection, the power module that the drain electrode was connected this moment outwards supplies power through the drain electrode, and when taking place to fall the electricity, when control enable signal was low level signal, this MOS pipe switched on, and the reserve power module of source electrode connection outwards supplies power through the drain electrode.

Preferably, the standby power supply module comprises a super capacitor module;

the power module is used for charging the super capacitor module.

Preferably, the backup power supply module is a battery module.

By last, reserve power module can adopt battery module, can realize the function as reserve power supply when the power falls, still can adopt super capacitor module, except realizing the function as reserve power supply when the power falls, still can charge for this super capacitor module when power module normally works to solve the drawback that the battery need be changed of using.

The invention also provides a data power-down holding device of the static random access memory, which comprises the data power-down holding circuit of the static random access memory.

Drawings

FIG. 1 is a block diagram of a data power-down hold circuit of a static random access memory according to the present invention;

FIG. 2 is a circuit diagram of a voltage monitoring unit according to the present invention;

FIG. 3 is a circuit diagram of the control logic for outputting key signals in the logic control unit according to the present invention;

FIG. 4 is a circuit diagram of the output power switching control logic in the logic control unit according to the present invention;

FIG. 5 is a circuit diagram of a key signal protection unit according to the present invention;

fig. 6 is a circuit diagram of the power switching unit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.

In order to solve the problems in the prior art, the invention provides a data power-down holding circuit of a static random access memory and equipment comprising the same, which can effectively avoid the risk that data of the static random access memory is easy to lose in the power-down process, and simultaneously prevent the data in the static random access memory from being lost due to the instability of key signals in the power-down process.

As shown in fig. 1, the data power-down maintaining circuit of the static random access memory includes a voltage monitoring unit 100, a logic control unit 200, a critical signal protection unit 300, a power switching unit 400, and a power supply unit 500, where the power supply unit 500 includes a power module 510 and a standby power module 520, and is used to supply power to the critical signal protection unit 300 and the static random access memory 600;

the voltage monitoring unit 100 is connected to the power module 510 of the power supply unit 500, and configured to monitor a voltage signal output by the power module 510 and output a level signal according to the monitored voltage signal;

the logic control unit 200 is connected to the voltage monitoring unit 100, and configured to generate a control enable signal according to the received level signal, and output the control enable signal to the critical signal protection unit 300 and the power switching unit 400 respectively;

the key signal protection unit 300 is connected to the logic control unit 200, and is configured to control on/off of a key signal output to the sram 600 according to a received control enable signal, where the key signal is generally a main control signal, for example, a chip select signal for a CPU to access the sram or a signal for the CPU to enable the sram, and when the signal is normally input to the sram, read/write operation on the sram may be performed, otherwise, read/write operation on the sram may not be performed;

the power switching unit 400 is connected to the logic control unit 200 and the power supply unit 500, and configured to output a power switching signal according to the received control enable signal, control the power module 510 or the standby power module 520 of the power supply unit 500 to switch, and supply power to the critical signal protection unit 300 and the sram 600.

The power module 510 may adopt a conventional 3.3V power supply, and the standby power module 520 may adopt a common button battery, which may work for more than one year due to the very low power consumption of the static random access memory in a static state; and a super capacitor module can be selected for use, the super capacitor module can provide the same power supply function as the button battery, and can be charged when the power module 510 normally works, so that the purpose of recycling and replacement is not needed, a one-way diode and a current-limiting resistor are connected between the super capacitor module and the power module 510, the one-way diode can be used for preventing power failure, the super capacitor reversely supplies power, the current-limiting resistor is used for limiting charging current, and the super capacitor is protected from being damaged by large current.

As shown in fig. 2, the voltage monitoring unit 100 includes a reset chip U129 and a circuit thereof, a power supply terminal 3 of the reset chip U129 is connected to the power supply module 510 to collect a voltage signal output by the power supply module, a ground terminal 1 of the reset chip is grounded, a capacitor C761 is connected in series to the power supply terminal 3 and the ground terminal 1, and an output terminal 2 outputs a reset high level signal or a reset low level signal according to the voltage signal of the power supply terminal 3;

according to the illustrated circuit, when the voltage signal collected by the power supply terminal 3 of the reset chip U129 is a normal power supply voltage, the output terminal 2 outputs a high level signal, and when the voltage signal collected by the power supply terminal 3 is lower than the normal power supply voltage (for example, lower than 2.93V) in the event of a power failure, the output terminal 2 outputs a low level signal.

As shown in fig. 3-4, the logic control unit 200 includes two parts, which respectively provide logic control signals for the rear-end key signal protection unit 300 and the power switching unit 400;

as shown in fig. 3, the circuit for outputting the key signal control logic in the logic control unit includes an NPN type triode U130, the base of the triode U130 is connected in series with a resistor R2152 and then connected to the output terminal 2 of the reset chip U129 to receive the output level signal, the collector is connected in series with a resistor R2118 and then connected to a reference power supply VDD, the reference power supply VDD provides a 3.3V collector reference voltage for the circuit, a resistor R2119 is further connected in series between the collector and the base, the emitter is grounded, and the collector outputs a control enable signal OE to the key signal protection unit 300 at the rear end;

when the normal power supply supplies power, the output end 2 of the reset chip U129 outputs a high level signal, at this time, according to the NPN transistor characteristic, the transistor U130 is turned on, the voltage of the collector is pulled low, and a low level control enable signal OE is output; when power down occurs, the output terminal 2 of the reset chip U129 outputs a low level signal, and at this time, the transistor U130 is turned off according to the NPN transistor characteristic, and the collector outputs a high level control enable signal OE.

As shown in fig. 4, the circuit of the output power switching control logic in the logic control unit includes a two-stage NPN transistor, wherein the base of the transistor U97 is connected in series with the resistor R2124 and then connected to the output terminal 2 of the reset chip U129 to receive the output level signal, the collector of the transistor U2150 is connected to the reference power VDD, the collector and the base of the transistor are also connected in series with the resistor R2123, the emitter is grounded, the collector of the transistor U97 is connected to the base of the transistor U77, the collector of the transistor U77 is connected in series with the resistor R2125 and then connected to the reference power VDD, the emitter is grounded, and the collector of the transistor U97 outputs the control enable signal BAT _ SWITCH to the power switching unit 400 at the rear end;

when the normal power supply supplies power, the output end 2 of the reset chip U129 outputs a high level signal, at this time, according to the characteristics of the NPN triode, the triode U97 is conducted, the voltage of the collector is pulled down, a low level signal is output to the base electrode of the triode U77, the triode U77 is disconnected, and the collector outputs a high level control enable signal BAT _ SWITCH; when power failure occurs, the output end 2 of the reset chip U129 outputs a low level signal, the triode U97 is turned off, the collector outputs a high level signal to the base of the triode U77, the triode U77 is turned on, and the collector outputs a low level control enable signal BAT _ SWITCH.

As shown in fig. 5, the key signal protection unit 300 implements the construction of the protection circuit through a tri-state gate, and specifically includes a tri-state gate trigger U128 and its circuit, a power supply terminal 5 of the tri-state gate trigger U128 is powered by an upper power supply unit 500, an input terminal 2 of the tri-state gate trigger U128 is connected to an input source of a key signal, receives a key signal CS3_ N, a control terminal 1 is connected to a collector of the triode U130, receives a control enable signal OE input by the triode U, an output terminal 4 is connected to the sram, an output terminal 4 and the power supply terminal 5 are further connected in series to a resistor R2120, and a ground terminal 3 is grounded;

when the power is supplied by a normal power supply, the triode U130 outputs a low-level control enable signal OE, the tri-state gate trigger U128 is in a normal working state, and the key signal CS3_ N is directly input to the sram 600 through the tri-state gate trigger U128; when power failure occurs, the triode U130 outputs a high-level control enable signal OE, the tri-state gate trigger U128 is locked, the output is in a high-impedance state, and the critical signal CS3_ N cannot pass through the tri-state gate trigger U128, and the interference input to the critical signal CS3_ N of the sram is stopped.

As shown in fig. 6, the power switching unit 400 includes a P-channel MOS transistor U127 and its circuit;

the gate G of the MOS transistor U127 is connected to the collector of the triode U77 to receive the control enable signal BAT _ SWITCH inputted thereto, the button cell CR2032 is connected in series to a zener diode D12 and a resistor R2126 in parallel to form a voltage stabilizing circuit, which is connected to the source S of the MOS transistor U127, the power supply is connected to the drain D2 of the MOS transistor U127 after being connected to a zener diode D11 in series, the zener diode D11 is further used to prevent the drain D2 from being connected to the power supply output terminal when the standby power supply module supplies power, so as to provide the supply voltage CPU1_ SRAM _ VDD to the SRAM 600 and the critical signal protection unit 300, and the drain D2 is further connected in series to a filter capacitor C784 to be grounded to filter the output supply voltage;

when a normal power supply supplies power, the collector of the triode U77 outputs a high-level control enable signal BAT _ SWITCH, at the moment, the MOS tube U127 is disconnected, and the power supply output end keeps supplying power to the power supply; when power failure occurs, the collector of the triode U77 outputs a low-level control enable signal BAT _ SWITCH, the MOS tube U127 is conducted at the moment, and the power supply output end is switched to the button cell CR2032 for power supply;

it should be noted that, because the general switch or the relay switch, etc. may be ignited due to poor contact to cause interference input when being pulled in, the present embodiment selects the MOS transistor, and based on the operating characteristic of the voltage control current thereof, there is actually a linear process when being closed or opened, so that there is no interference such as ignition, thereby avoiding the input of interference signals when being powered on or powered off; meanwhile, the added filter capacitor can be used as an energy storage capacitor, so that the stability of the power supply is further enhanced.

In summary, the working principle of the data power-down holding circuit of the static random access memory is as follows:

when the power supply is normal, the power supply module supplies power to the key signal protection unit and the static random access memory, the voltage signal acquired by the voltage monitoring unit is a normal voltage signal, the output end of the voltage signal outputs a high level signal, the logic control unit respectively outputs a low level control enable signal OE to the key signal protection unit and a high level control enable signal BAT _ SWITCH to the power supply switching unit, the power supply switching unit controls the power supply unit to supply power to the power supply module under the drive of the high level control enable signal BAT _ SWITCH, the key signal CS3_ N is directly input into the static random access memory under the drive of the low level control enable signal OE, and the static random access memory can perform normal read-write operation;

when power failure occurs, the voltage signal acquired by the voltage monitoring unit is lower than a normal voltage signal, the output end of the voltage monitoring unit outputs a low-level signal, the logic control unit respectively outputs a high-level control enable signal OE to the key signal protection unit and a low-level control enable signal BAT _ SWITCH to the power supply switching unit, the power supply switching unit controls the power supply unit to SWITCH to a standby power supply module for supplying power under the drive of the low-level control enable signal BAT _ SWITCH, namely the standby power supply module supplies power to the key signal protection unit and the static random access memory, the key signal protection unit outputs a high-resistance state under the drive of the low-level control enable signal OE, the key signal CS3_ N stops being input into the static random access memory, and the static random access memory cannot perform normal read-write operation;

when the power-down problem is solved and the power module can supply power outwards again, the voltage signal collected by the voltage monitoring unit is changed into a normal voltage signal again, the output end of the voltage monitoring unit outputs a high-level signal, the logic control unit respectively outputs a low-level control enable signal OE to the key signal protection unit and a high-level control enable signal BAT _ SWITCH to the power switching unit, the power switching unit controls the power supply unit to supply power to the power module again from the standby power supply module under the driving of the high-level control enable signal BAT _ SWITCH, the key signal CS3_ N is directly input into the static random access memory under the driving of the low-level control enable signal OE, and the static random access memory can perform normal read-write operation at the moment.

In summary, the data power-down holding circuit of the static random access memory provided by the invention can effectively avoid the risk that the data of the static random access memory is easy to lose in the power-down process, and simultaneously, the data in the static random access memory is prevented from being lost due to the instability of key signals in the power-down process.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A data power-down holding circuit of a static random access memory is characterized by comprising a voltage monitoring unit, a logic control unit, a key signal protection unit, a power supply switching unit and a power supply unit, wherein the power supply unit comprises a power supply module and a standby power supply module and is used for supplying power to the key signal protection unit and the static random access memory;

2. The data power-down holding circuit of the static random access memory according to claim 1, wherein the voltage monitoring unit comprises a reset chip;

3. The data power-down holding circuit of the static random access memory according to claim 1, wherein the logic control unit comprises:

4. The data loss holding circuit of claim 3, wherein the first logic control circuit comprises a first NPN transistor;

5. The data loss holding circuit of the static random access memory according to claim 3, wherein the second logic control circuit comprises a second NPN transistor and a third NPN transistor;

6. The data power-down holding circuit of the static random access memory according to claim 1, wherein the key signal protection unit comprises a tri-state gate flip-flop;

7. The data power-down holding circuit of the static random access memory according to claim 1, wherein the power switching unit comprises a P-channel MOS transistor;

8. The data power-down maintaining circuit of the static random access memory according to claim 1, wherein the standby power supply module comprises a super capacitor module;

the power module is used for charging the super capacitor module.

9. The data loss holding circuit of the static random access memory according to claim 1, wherein the backup power supply module comprises a battery module.

10. A data power-down holding apparatus for a static random access memory, comprising the data power-down holding circuit for a static random access memory according to any one of claims 1 to 9.