CN112102863B

CN112102863B - Static random access memory control circuit, method, memory and processor

Info

Publication number: CN112102863B
Application number: CN202010931569.5A
Authority: CN
Inventors: 孙燃; 姚其爽; 杨昌楷
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-09-07
Filing date: 2020-09-07
Publication date: 2023-04-25
Anticipated expiration: 2040-09-07
Also published as: CN112102863A

Abstract

The application provides a static random access memory control circuit, a method, a memory and a processor, wherein the static random access memory control circuit comprises: a static random access memory cell, a first bit line, a second bit line, and a precharge cell; the precharge unit includes: a first precharge unit and a second precharge unit; the first precharge unit is connected with the static random access memory unit through a first bit line; the second precharge unit is connected with the static random access memory unit through a second bit line; the first precharge unit comprises a first peripheral precharge subunit and a first array precharge subunit, and the first peripheral precharge subunit and the first array precharge subunit are respectively connected with the first bit line; the second precharge unit includes a second peripheral precharge subunit and a second array precharge subunit, each of which is connected to a second bit line.

Description

Static random access memory control circuit, method, memory and processor

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a static random access memory control circuit, a static random access memory control method, a static random access memory, and a static random access memory processor.

Background

Since the low-level metal wire has a large resistance and the high-level metal wire has a low resistance, the wiring of the metal wire has a large influence on the chip when the chip is designed. However, as the requirements of the chip are higher and higher, the thickness of the chip is thinner and thinner, so that the high-level metal wiring resources are limited, and some power signals arranged on the packaging layer need to change the wiring positions, so that the wiring positions of the packaging layer are reserved for some other key signals. But the lower level metal resistance is greater relative to the package level routing and the use of lower level metal lines for the power signal may result in circuit failure due to electromigration and voltage drop.

Disclosure of Invention

It is an object of the present application to provide a sram control circuit, method, memory and processor that alleviates the problem of circuit failure due to electromigration and voltage drop.

In a first aspect, an embodiment of the present invention provides a sram control circuit, including: a static random access memory cell, a first bit line, a second bit line, and a precharge cell;

the precharge unit includes: a first precharge unit and a second precharge unit;

the first precharge unit is connected with the first bit line;

The second precharge unit is connected with the second bit line;

the first precharge unit comprises a first peripheral precharge subunit and a first array precharge subunit, the first peripheral precharge subunit and the first array precharge subunit are respectively connected with the first bit line, the first peripheral precharge subunit is used for charging the first bit line through a peripheral logic power supply, and the first array precharge subunit is used for charging the first bit line through a storage array power supply;

the second precharge unit comprises a second peripheral precharge subunit and a second array precharge subunit, the second peripheral precharge subunit and the second array precharge subunit are respectively connected with the second bit line, the second peripheral precharge subunit is used for charging the second bit line through the peripheral logic power supply, and the second array precharge subunit is used for charging the second bit line through the storage array power supply.

In an alternative embodiment, the first peripheral pre-charge subunit comprises: a fifteenth transistor and a seventeenth transistor;

the source electrode of the fifteenth transistor is connected with the voltage of the peripheral logic power supply;

A drain of the fifteenth transistor is connected to a drain of the seventeenth transistor;

the source of the seventeenth transistor is connected to the first bit line.

In the embodiment of the application, the peripheral logic power supply is used for precharging the bit line through the functions of the fifteenth transistor and the seventeenth transistor, so that the effect of reducing the power supply current pressure of the memory array can be realized.

In an alternative embodiment, the second peripheral pre-charge subunit comprises: a sixteenth transistor and an eighteenth transistor;

the source of the sixteenth transistor is connected with the voltage of the peripheral logic power supply;

the drain of the sixteenth transistor is connected with the drain of the eighteenth transistor;

the source of the eighteenth transistor is connected to the second bit line.

In the embodiment of the application, the peripheral logic power supply is used for precharging the bit line through the actions of the sixteenth transistor and the eighteenth transistor, so that the effect of reducing the power supply current pressure of the memory array can be realized.

In an alternative embodiment, the precharge unit further includes: and a balance tube connected between the first bit line and the second bit line.

In an alternative embodiment, the method further comprises: a bit line read transfer unit and a bit line write transfer unit;

the bit line read transmission unit is used for reading data from the static random access memory unit;

the bit line write transfer unit is used for writing data into the SRAM unit.

In the embodiment of the application, the writing and reading of data into and from the sram cell are realized by the bit line read and transfer unit and the bit line write and transfer unit.

In a second aspect, an embodiment of the present invention provides a sram control method, which is applied to the sram control circuit according to any one of the foregoing embodiments, where the sram control method includes:

performing a first phase of charging, the first phase of charging including charging the first bit line through the first peripheral precharge subunit into a peripheral logic power supply and charging the second bit line through the second peripheral precharge subunit into a peripheral logic power supply;

after the first-stage charging is finished, the first bit line is charged by accessing a storage array power supply through a first array pre-charging subunit, and the second bit line is charged by accessing a storage array power supply through a second array pre-charging subunit.

In the embodiment of the application, the peripheral logic power supply is used for charging the bit line, and then the memory array power supply is used for charging the bit line, so that the memory array power supply current in the bit line precharge stage can be reduced, and circuit failure caused by electromigration and voltage drop can be avoided.

In an alternative embodiment, the accessing the peripheral logic power supply through the first peripheral precharge subunit to charge the first bit line, and accessing the peripheral logic power supply through the second peripheral precharge subunit to charge the second bit line, includes:

the first bit line is charged to a specified voltage by accessing the peripheral logic power supply through the first peripheral precharge subunit, and the second bit line is charged to the specified voltage by accessing the peripheral logic power supply through the second peripheral precharge subunit.

In an alternative embodiment, said switching on the peripheral logic power supply to the first peripheral precharge subunit via the first peripheral precharge subunit charges the first bit line to a specified voltage, and switching on the peripheral logic power supply to the second peripheral precharge subunit via the second peripheral precharge subunit charges the second bit line to the specified voltage, comprising:

when the peripheral logic power supply voltage is greater than or equal to a voltage threshold determined by the memory array power supply voltage, charging the first bit line to the voltage threshold by accessing the peripheral logic power supply through the first peripheral precharge subunit, and charging the second bit line to the voltage threshold by accessing the peripheral logic power supply through the second peripheral precharge subunit;

And when the peripheral logic power supply voltage is smaller than a voltage threshold value determined by the memory array power supply voltage, the first peripheral pre-charging subunit is connected with the peripheral logic power supply to charge the first bit line to the peripheral logic power supply voltage, and the second peripheral pre-charging subunit is connected with the peripheral logic power supply to charge the second bit line to the peripheral logic power supply voltage.

In the embodiment of the application, by adopting different control logics according to the peripheral logic power supply and the peripheral logic power supply voltage, the requirements of different scenes can be met, so that the applicability of the control method in the embodiment of the application can be improved.

In a third aspect, an embodiment of the present invention provides a memory, including: the sram control circuit of any one of the preceding embodiments.

In a fourth aspect, an embodiment of the present invention provides a processor, including: the memory according to the foregoing embodiment.

In a fifth aspect, an embodiment of the present invention provides an electronic device, including: the processor of the foregoing embodiment.

The beneficial effects of the embodiment of the application are that: by arranging the first peripheral pre-charging subunit and the second peripheral pre-charging subunit, the current density of the memory array power supply can be reduced through the charging action of the peripheral logic power supply in the bit line pre-charging stage, so that circuit failure caused by electromigration and voltage drop is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of the read/write timing of a SRAM control circuit of a self-timed chip design.

Fig. 2 is a schematic diagram of read/write timing of a sram control circuit of a chip in a clock phase chip design.

FIG. 3 is a schematic diagram of internal timing of a SRAM control circuit of a chip in a clock phase chip design.

Fig. 4 is a circuit diagram of a sram control circuit according to an embodiment of the present application.

FIG. 5 is a schematic diagram of the precharge timing of the SRAM control circuit of the chip in the clock phase chip design.

Fig. 6 is a flowchart of a sram control method according to an embodiment of the present application.

Description of main reference numerals: m1-a first transistor; m2-a second transistor; m3-a third transistor; m4-fourth transistors; m5-fifth transistors; m6-sixth transistors; m7-seventh transistor; m8-eighth transistors; m9-balance tube; m10-tenth transistor; m11-eleventh transistors; m12-twelfth transistor; m13-thirteenth transistor; m14-fourteenth transistors; m15-fifteenth transistor; m16-sixteenth transistor; m17-seventeenth transistor; m18-eighteenth transistor; BL-first bit line; BLB-second bit line.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

The method and circuit provided by the embodiment of the application can be applied to Static Random-Access Memory (SRAM), and the current state of SRAM design is described below.

There are two common design methods for SRAM circuits, one is based on self-timing (self-timing) read-write design of clock pulses, and one is based on phase-timing (phase-timing) triggered read-write design.

As for self-timing design, as shown in fig. 1, fig. 1 shows a schematic diagram of read/write timing of a sram control circuit of a chip in a self-timing chip design. In this example, the preparation time of the memory ADDRESS (ADDRESS) is before the Clock (CLK) pulse active edge, which goes to the internal clock (internal CLK) of the post-trigger circuit to generate the word line clock, bit line select clock, reference array (reference signals) to turn on the clock and to turn off the clock of the data latches. The reference array has a self-resetting function, and after a read operation or a write operation is considered to be completed, the reference array turns off its own clock, resets all internal clocks, turns on the data latch clock, turns on a Sense Amplifier (SAEN) to read the differential voltage on the bit lines of the SRAM array, and restores the memory array to a state to be operated (e.g., turns off the word lines, precharges the bit lines, etc.). Thus, when a self-timed SRAM circuit is read, it can be considered as a flip-flop that triggers the data transmission by a single edge of the clock. To achieve proper writing and reading of data, self-timed SRAM circuits require proper setting of the speed (programeddelay) of the reference array, and the degree of matching to the working array. However, for an SRAM module already implemented on a System-on-a-Chip (SoC), these settings are all cured and cannot be changed with the peripheral voltage temperature, so that in an application scenario where the voltage temperature change is large, the self-timing design may fail to read and write.

The processor is a system chip which needs to work for a long time and frequently changes the voltage and the temperature. Thus, the cache therein may be designed using a clock phase approach. Fig. 2 is a schematic diagram of a read/write timing sequence of a sram control circuit of a chip of a clock phase chip design. In this example, the preparation of the memory ADDRESS (ADDRESS) occurs on one edge (e.g., rising edge) of the clock, while the data read (RdData) occurs on another edge (e.g., falling edge). When the rising edge of the clock arrives, a word line clock, a bit line selection clock and a clock for closing the data latch are generated. After the word line clock is asserted, the memory circuit begins a read or write operation. When the clock falling edge arrives, a sense amplifier enable signal (Sensitive amplifier enable signal, SAEN) is generated, the developed voltage difference on the bit line is discharged, the data for the given address is read out, and the memory array is restored to a state to be operated (e.g., the word line is turned off, the bit line is precharged, etc.). Thus, a clock phase SRAM circuit can be considered a flip-flop that grabs upstream data by one edge and transmits the data downstream by one edge during a read operation. Compared with the self-timing method, the clock phase method can cope with different voltage temperatures by adjusting the clock frequency so as to complete correct reading and writing and even complete over-frequency actions.

The inventors of the present embodiment studied the above two ways, and have found that for the design of the clock phase type SRAM applied in the processor, the operations such as over-clocking and idle running need to be performed in cooperation with the processor core. The over-frequency core needs to increase the peripheral logic power supply voltage of the SRAM circuit, the idle core needs to decrease the peripheral logic power supply voltage, and the power supply voltage of the storage array for supplying power to the SRAM unit is kept unchanged all the time so that the SRAM unit can keep correct data read-write operation. In order to ensure that all the signals of the operation bit lines and the word lines have good timing margin, and to ensure that the stability of the SRAM cell is maintained under the condition that the peripheral logic power supply voltage is greatly changed, the word lines, the bit lines and the SRAM cell can be hung on the power supply voltage domain of the storage array.

However, as the chip size becomes smaller (e.g., 7nm process), the resistance of the lower metal layer increases compared to the previous (e.g., 14nm process), so that the critical signal previously routed in the lower metal layer needs to be lifted up to the wiring level, and the higher metal lines are used. However, the high-level metal wiring has limited resources, and some power signals (such as memory array power supply) routed at the package layer need to give up resources to the critical signal, which in turn is generated by the on-chip linear regulator and uses the low-level metal wiring. Through the research of the inventor, as the line resistance of the low-layer metal wiring is larger, the circuit failure caused by electromigration and voltage drop can be avoided by reducing the current of the power supply of the low-layer metal wiring.

Further, the inventor studies the sram to know that the current pressure of the peripheral logic power supply is smaller than the current pressure of the memory array power supply during the read/write operation of the sram. Thus, designs for static random access memories can reduce the current of the memory array power supply during the bit line precharge phase by diverting some of the current of the memory array power supply to the peripheral logic power supply.

As shown in fig. 3, fig. 3 is a waveform diagram of the clock phase type SRAM design. When a read operation is performed on a clock phase type SRAM circuit, after a bit line (BL@VDDM) is precharged and closed by a clock rising edge, a word line (WL@VDDM) is opened to a row of SRAM cells to be read, and a transistor on the side 0 of the SRAM cells is stored to start pulling down the bit line selected by an address. And closing the word line and the bit line selection until the clock falling edge arrives, and precharging the bit line. The clock falling edge simultaneously generates a sense amplifier enable signal, grabs the developed voltage difference (DeltaV) on the bit line and outputs. The word line high phase (high-phase) duration, bit line precharge signal high phase duration and bit line pull-down duration are determined by the clock high Xiang Shichang, and when the high phase duration is performed, the bit line (BL@VDDM) can be pulled down to the ground potential, and the bit line voltage difference between the bit line and the other side of the SRAM cell for maintaining the precharge voltage reaches the power supply voltage value of the whole memory array. Such low voltage recharging is provided to the memory array power supply in preparation for the next cycle of read and write operations, the recharging requiring a large amount of charge to be pulled from the memory array power supply.

When writing operation is performed on the clock phase type SRAM circuit, after the bit line is precharged and closed by the clock rising edge, the word line is started to write the SRAM cell row, and the write driving unit starts to pull down the bit line selected by the address to the ground potential. And closing the word line and the bit line selection until the clock falling edge arrives, and precharging the bit line. The voltage difference between two bit lines of the SRAM cell reaches the memory array power supply, and the precharging of the bit lines pulled down to ground potential to the memory array power supply also requires a large amount of charge.

In this embodiment, since the resistance of the low-level metal lines used for the memory array power supply becomes large, the charge density on the memory array power supply must be reduced, and the memory array power supply current density is maximized when the SRAM cell bit lines are precharged. The peripheral logic circuit is considered to have smaller current pressure than the memory array power supply current pressure during SRAM read-write operation, so that part of charge can be born by the peripheral logic power supply under the condition of not changing bit lines and control signal voltage domains thereof, and the aim of reducing the memory array power supply current during precharge is fulfilled.

Based on the above study, the static random access memory control circuit, the static random access memory control method, the memory, the processor and the electronic device provided by the application can solve the problem of the above study.

Example 1

The embodiment of the application provides a sram control circuit, as shown in fig. 4, where the sram control circuit in the embodiment includes: a static random access memory cell, a first bit line BL, a second bit line BLB, and a precharge cell.

In this embodiment, the precharge unit may include a first precharge unit and a second precharge unit.

The first precharge unit is connected to the first bit line BL, and the second precharge unit is connected to the second bit line BLB.

The first precharge unit includes a first peripheral precharge subunit and a first array precharge subunit, which are respectively connected to the first bit line BL.

In this embodiment, the first peripheral precharge subunit is configured to charge the first bit line BL by a peripheral logic power supply, and the first array precharge subunit is configured to charge the first bit line BL by a memory array power supply.

In this embodiment, the second precharge unit includes a second peripheral precharge subunit and a second array precharge subunit, and the second peripheral precharge subunit and the second array precharge subunit are respectively connected to the second bit line BLB.

The second peripheral precharge subunit is configured to charge the second bit line BLB through the peripheral logic power supply, and the second array precharge subunit is configured to charge the second bit line BLB through the memory array power supply.

In this embodiment, the first bit line BL and the second bit line BLB can provide two opposite signals.

Wherein the first bit line BL corresponds to the QT point in the SRAM cell and the second bit line BLB corresponds to the QC point in the SRAM cell.

Illustratively, the QT point initial memory value and the QC point initial memory value may be two different values. For example, if the QT point initially stores a logical 0, then the QC point initially stores a logical 1.

Illustratively, as shown in fig. 4, the sram cell may include: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6.

The third transistor M3 and the fourth transistor M4 form a flip-flop, and the first transistor M1 and the second transistor M2 serve as load resistors of the fifth transistor M5 and the sixth transistor M6, respectively.

Alternatively, a state when the third transistor M3 is turned off and the fourth transistor M4 is turned on is referred to as "1". The state when the third transistor M3 is turned on and the fourth transistor M4 is turned off is referred to as "0".

Alternatively, the first transistor M1 and the second transistor M2 may be PMOS transistors.

Alternatively, the third transistor M3 and the fourth transistor M4 may be NMOS transistors.

Alternatively, the fifth transistor M5 and the sixth transistor M6 may be NMOS transistors.

In this embodiment, each byte in the sram cell is stored in two cross-coupled inverters formed by the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4.

The fifth transistor M5 and the sixth transistor M6 are control switches of the first bit line BL and the second bit line BLB.

Illustratively, the sram cell may include three states: idle state (standby), read data (reading), and write data (writing).

Illustratively, when the random access memory cell is in an idle state, if the word line is not selected to be high level, the fifth transistor M5 and the sixth transistor M6 as control switches handle off, thus isolating each of the static random access memory cells from the first bit line BL and the second bit line BLB.

For example, when data is required to be read from the random access memory cell, the word line is set to a high level, and the two switching transistors are turned on, so that the original information is outputted from the read/write line.

For example, when data needs to be written into the dram cell, the write data sets the level value of the first bit line BL to the value to be written (for example, when "1" is written, the first bit line BL is at a high level when "1" is written, the first bit line BL is at a low level when "0") and sets the select line to a high level, and then the flip-flop is set to the corresponding state (when "1" is written, the state is set to "1", that is, the third transistor M3 is turned off and the fourth transistor M4 is turned on). Obviously, whether the information held by the memory cell is "1" or "0", four transistors among the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are in an on state.

For example, as shown in fig. 4, the first array pre-charge subunit may include a seventh transistor M7, where a source of the seventh transistor M7 is connected to the memory array power supply voltage, and a drain of the seventh transistor M7 is connected to the first bit line BL.

Illustratively, the seventh transistor M7 is gated by the signal sw_vdd.

The seventh transistor M7 may be a transistor gated by the signal prch, for example. Wherein the prch represents a precharge (precharge) signal.

Illustratively, the eighth transistor M8 may be a prch-gated transistor.

Illustratively, as shown in fig. 4, the second array pre-charge subunit may include an eighth transistor M8, where a source of the eighth transistor M8 is connected to the memory array power supply voltage, and a drain of the eighth transistor M8 is connected to the second bit line BLB.

Illustratively, this eighth transistor M8 is gated by the signal sw_vdd.

The signal sw_vdd is a signal under the power domain of the memory array.

Alternatively, the seventh transistor M7 and the eighth transistor M8 may be PMOS transistors.

Optionally, the precharge unit further includes: and a balance pipe M9 connected between the first bit line BL and the second bit line BLB.

Alternatively, the balance tube M9 may be a PMOS tube.

Optionally, the sram control circuit further comprises: bit line read transfer units and bit line write transfer units.

The bit line read transfer unit is used for reading data from the SRAM cell.

The bit line write transfer unit is used for writing data into the SRAM cell.

As shown in fig. 4, the bit line read transfer unit includes: an eleventh transistor M11 and a twelfth transistor M12.

As shown in fig. 4, the bit line write transfer unit includes: a thirteenth transistor M13 and a fourteenth transistor M14.

Illustratively, as shown in fig. 4, the first peripheral pre-charge subunit may include: a fifteenth transistor M15 and a seventeenth transistor M17.

The source of the fifteenth transistor M15 is connected to the voltage of the peripheral logic power source, the drain of the fifteenth transistor M15 is connected to the drain of the seventeenth transistor M17, and the source of the seventeenth transistor M17 is connected to the first bit line BL.

Alternatively, the fifteenth transistor M15 may be a PMOS transistor, and the seventeenth transistor M17 may be an NMOS transistor.

Illustratively, the fifteenth transistor M15 may be gated by a signal sw_vdd and the seventeenth transistor M17 may be gated by a constant logic 1 signal of the memory array voltage domain. Illustratively, the constant logic 1 signal may be TIE1.

Illustratively, as shown in FIG. 4, the second peripheral pre-charge subunit comprises: a sixteenth transistor M16 and an eighteenth transistor M18.

The source of the sixteenth transistor M16 is connected to the voltage of the peripheral logic power source, the drain of the sixteenth transistor M16 is connected to the drain of the eighteenth transistor M18, and the source of the eighteenth transistor M18 is connected to the second bit line BLB.

Alternatively, the sixteenth transistor M16 may be a PMOS transistor and the eighteenth transistor M18 may be an NMOS transistor.

Illustratively, the sixteenth transistor M16 may be gated by a signal sw_vdd and the eighteenth transistor M18 may be gated by a constant logic 1 signal of the memory array voltage domain. Illustratively, the constant logic 1 signal may be TIE1.

Where signal sw_vdd is the signal of the peripheral logic power domain and signal TIE1 is the signal of the memory array power domain.

The fifteenth transistor M15 may be a transistor gated by the signal prch, for example.

The sixteenth transistor M16 may be a transistor gated by the signal prch, for example.

When the bit lines need to be precharged, the word lines become logic 0, the fifth transistor M5 and the sixth transistor M6 are turned off, the signal blpcx becomes logic 0, the balance tube M9 is turned on, the signal sw_vdd and the signal sw_vdd sequentially become logic 0 according to the precharge threshold value of the first bit line BL, the precharge unit is turned on, the two bit lines are charged to the power level of the memory array, and the charging current is completely supplied by the power supply of the memory array. During the precharge period, the fifth transistor M5, the sixth transistor M6, the bit line read transfer unit, and the bit line write transfer unit are all in an off state.

When it is desired to read the data in the sram cell, the signal blpcx turns to logic 1 to turn off the balance transistor M9, the signal sw_vdd turns off the precharge unit, the two bit lines float, then the word line WL turns to logic 1 to turn on the fifth transistor M5 and the sixth transistor M6 in the sram cell, and the signal RDColSel turns to 0 to turn on the eleventh transistor M11 and the twelfth transistor M12. In one example, suppose the initial value of QT in a sram cell is a logic 0, and qc is a logic 1 as opposed to QT. After the fifth transistor M5 and the sixth transistor M6 are turned on, the floating first bit line BL is pulled down by the logic 0 initially stored by QT, and its potential is slowly decreased; at the same time, the potential on the second bit line BLB remains at logic 1 all the time since there is no pull-down current path. The potential dropped on the first bit line BL and the potential "1" on the second bit line BLB pass through the eleventh transistor M11 and the twelfth transistor M12, are read as RdData and RdDataB, and are sent to the sense amplifier to amplify the voltage difference of the two signals, and the sense amplifier outputs a logic 0, indicating that the reading of the stored "0" is successful. After the reading is completed, the eleventh transistor M11, the twelfth transistor M12, the fifth transistor M5, and the sixth transistor M6 are turned back on, and the precharge unit is turned back on to precharge the bit line to the memory array power supply level.

When it is necessary to write data to the sram cell, the balance transistor M9 is turned off by the signal blpcx, the precharge unit is turned off by the signal sw_vdd, the two bit lines are floated, then the fifth transistor M5 and the sixth transistor M6 in the sram cell are turned on by the word line WL changing to logic 1, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned on by the signal WrColSel changing to 1. In one example, suppose the initial value of QT in a sram cell is a logic 0, and qc is instead a logic 1. The written data is clocked onto the bit line by two opposite logic WrData and WrDataB, e.g., wrDataB is 0 and WrData is 1, at which time the precharge potential of the second bit line BLB is pulled low by the 0 potential of WrDataB to logic 0, which logic 0 continues to be pulled low by M6 to initially store "1" of QC, and after QC becomes 0, the first transistor M1 is turned on, pulling QT up to 1. The "0" stored in the cell of the sram is rewritten to "1". After the data writing to the sram cell is completed, the thirteenth transistor M13, the fourteenth transistor M14, the fifth transistor M5 and the sixth transistor M6 are turned back on, and the precharge unit turns back on to precharge the bit line to the memory array power supply level.

The following describes the operation of the sram control circuit in the embodiments of the present application by way of an example.

Referring to fig. 5, in one example, the current first bit line BL is at ground potential and needs to be precharged to the memory array power supply. When the bit line precharge signal blpcx@vddm comes in a falling edge, it will generate a signal sw_vdd@vdd and a falling edge of signal sw_vdd@vddm, wherein signal sw_vdd@vdd falls earlier than signal sw_vdd@vddm. The falling edge of the signal sw_vdd@vdd turns on the fifteenth transistor M15 to charge the first bit line BL to a specified voltage value.

Illustratively, in the example shown in FIG. 5, "@ VDDM" represents the associated control signal for the VDDM power supply, and "@ VDD" represents the associated control signal for the VDD power supply.

When the first bit line BL is charged to the specified voltage value, the seventeenth transistor M17 starts to be turned off. The first bit line BL will remain around this specified voltage value and then be slowly pulled up by the subthreshold current from the peripheral logic power supply.

Illustratively, the above specified voltage values are represented as Vx, vx=min (VDDM-VTN, VDD). Wherein VTN represents the threshold voltage of the seventeenth transistor M17, VDD represents the peripheral logic power supply voltage, VDDM represents the memory array power supply voltage, and min (X, Y) represents a small value X, Y. The specified voltage value is equal to the voltage value that is smaller in value (VDDM-VTN) than VDD.

Then, the falling edge of the signal sw_vdd@vdd is subjected to a self-resetting operation after a delay tpulse, and the fifteenth transistor M15 is turned off after the falling edge is pulled up to the peripheral logic power supply voltage. The falling edge of the signal sw_vdd@vdd triggers the falling edge of the signal sw_vdd@vddm after a period of delay toffset, the falling edge of the signal sw_vdd@vddm in the waveform is turned on after the signal sw_vdd@vdd rises, at this time, the first bit line BL starts the seventh transistor M7 after the signal sw_vdd@vdd is charged to a specified voltage value, and waits for the signal sw_vdd@vddm falling edge, and finally the first bit line BL is charged to the storage array power supply voltage by the seventh transistor M7. The rising edge of the signal sw_vdd@vddm is generated by the rising edge of the signal blpcx@vddm to stop the charging of the first bit line BL, thereby bringing the sram cell into a read-write state.

In this embodiment, tpulse and toffset are derived from standard cell process evaluations, which may be matched in value to process drift; while tpulse and toffset may use the same value for read and write operations, different values may be used to accommodate different bit line precharge charges required for read and write states.

In this embodiment, the toffset value may be positive or negative, and in the example shown in fig. 5, the toffset value is positive. As shown in fig. 5, when the toffset value is negative, that is, the hazard mode (hazard) shown in fig. 5, there may be a dc path between VDD and VDDM, but the charging speed is faster. The toffset value is positive, i.e., the conservative mode (constant) shown in fig. 5, sacrificing the charging speed and avoiding the dc path between VDD and VDDM. Specifically, the selection may be made according to actual requirements, for example, the sensitivity of the chip system to VDD and VDDM paths may be selected accordingly.

The sram control circuit of the present embodiment is capable of supporting different differential states between the peripheral logic supply voltage and the memory array power supply.

Illustratively, when VDD > = VDDM-VTN, the seventeenth transistor M17 is turned off after the bit line is precharged to VDDM-VTN by using the peripheral logic power supply, the seventh transistor M7 is turned on by the signal sw_vddm to continue precharging the first bit line BL to the memory array power supply voltage.

Illustratively, when VDD < VDDM-VTN, the first bit line BL continues to be precharged to the memory array supply voltage by directly entering a wait state after precharging the bit line to VDD using the peripheral logic supply, waiting for sw_vddm to turn on the seventh transistor M7.

As shown in fig. 5, the first bit line precharge process includes: VDD precharge (VDD precharge) and VDDM precharge (VDDM precharge).

In the sram control circuit of the embodiment of the present application, by setting the first peripheral precharge subunit and the second peripheral precharge subunit, the current density of the storage array power supply may be reduced by the charging action of the peripheral logic power supply in the bit line precharge stage, so as to avoid the circuit caused by electromigration and voltage drop.

In the embodiment of the application, when the low-layer metal wire is used for the power supply signal, circuit failure caused by electromigration and voltage drop can be caused, so that the current density on the power supply signal wire can be reduced under the condition that the normal power supply of the power supply is ensured, the occurrence of electromigration is further reduced, and the instantaneous high-value voltage drop is reduced. Specifically, by arranging the first peripheral pre-charging subunit and the second peripheral pre-charging subunit, the current density of the memory array power supply can be reduced through the charging action of the peripheral logic power supply in the bit line pre-charging stage, so that circuit failure caused by electromigration and voltage drop is avoided.

Further, reducing SRAM array power supply current density during bitline precharge leaves more room for linear regulator design.

Further, the problem of wiring in the low-layer metal is solved, so that the power supply signal can be wired by the low-layer metal, more wiring positions in the high-layer metal can be provided, and the possibility that the VDDM high-layer metal wiring is yielded to other key signal implementations is improved.

Further, when VDD varies greatly with respect to VDDM, the bit line precharge still can be kept in normal operation, and when the process angle varies, the bit line precharge still can be kept in normal operation.

The sram control circuit of the present embodiment may be configured to perform the steps of the method provided in the embodiments of the present application. The implementation of the sram control method is described below by way of example.

Example two

Referring to fig. 6, a flowchart of a sram control method according to an embodiment of the present application is shown. The specific flow shown in fig. 6 will be described in detail.

Step 101, performing a first phase of charging, where the first phase of charging includes charging the first bit line through the first peripheral precharge subunit into the peripheral logic power supply, and charging the second bit line through the second peripheral precharge subunit into the peripheral logic power supply.

Optionally, step 101 may include: the first bit line BL is charged to a specified voltage by accessing the peripheral logic power supply through the first peripheral precharge subunit, and the second bit line BLB is charged to the specified voltage by accessing the peripheral logic power supply through the second peripheral precharge subunit.

In one embodiment, when the peripheral logic power supply voltage is greater than or equal to a voltage threshold determined by the memory array power supply voltage, the first bit line BL is charged to the voltage threshold by accessing the peripheral logic power supply through the first peripheral precharge subunit, and the second bit line BLB is charged to the voltage threshold by accessing the peripheral logic power supply through the second peripheral precharge subunit.

In another embodiment, when the peripheral logic power supply voltage is less than a voltage threshold determined by the memory array power supply voltage, the first bit line BL is charged to the peripheral logic power supply voltage by accessing the peripheral logic power supply through the first peripheral precharge subunit, and the second bit line BLB is charged to the peripheral logic power supply voltage by accessing the peripheral logic power supply through the second peripheral precharge subunit.

Alternatively, the above-described voltage threshold determined by the memory array power supply voltage may be expressed as a difference between the memory array power supply voltage and the threshold voltage of the seventeenth transistor M17.

Alternatively, the above-described voltage threshold determined by the memory array power supply voltage may be expressed as a difference between the memory array power supply voltage and the threshold voltage of the eighteenth transistor M18.

Step 102, after the first stage charging is completed, the first bit line is charged by accessing the memory array power supply through the first array pre-charging subunit, and the second bit line is charged by accessing the memory array power supply through the second array pre-charging subunit.

The sram control circuit used in the present embodiment can be referred to as the description in the first embodiment, and will not be described herein.

In addition, the embodiment of the application also provides a memory, which comprises a static random access memory control circuit.

For example, the sram control circuit is similar to the sram control circuit provided in embodiment one, and further details of the sram control circuit in this embodiment can be found in embodiment one, which is not described herein.

Embodiments of the present application may also provide a processor including a processor core and a memory.

Embodiments of the present application may also provide an electronic device, where the electronic device may include a processor.

By way of example, other components may also be included in the electronic device, such as an input-output unit, a display unit, a positioning unit, etc. Alternatively, the electronic device may also include more or fewer components. The components required for setting can be selected according to the use scene of the electronic device.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored on a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The above is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A static random access memory control circuit, comprising: a static random access memory cell, a first bit line, a second bit line, and a precharge cell;

The first precharge unit is connected with the first bit line;

the second precharge unit is connected with the second bit line;

2. The sram control circuit of claim 1, wherein said first peripheral precharge subunit comprises: a fifteenth transistor and a seventeenth transistor;

the source of the seventeenth transistor is connected to the first bit line.

3. The sram control circuit of claim 1, wherein said second peripheral precharge subunit comprises: a sixteenth transistor and an eighteenth transistor;

the source of the eighteenth transistor is connected to the second bit line.

4. The sram control circuit of claim 1, wherein said precharge unit further comprises: and a balance tube connected between the first bit line and the second bit line.

5. The sram control circuit of claim 1, further comprising: a bit line read transfer unit and a bit line write transfer unit;

The bit line write transfer unit is used for writing data into the SRAM unit.

6. A sram control method, applied to the sram control circuit of any one of claims 1-5, comprising:

performing a first phase of charging, the first phase of charging including charging the first bit line through the first peripheral precharge subunit accessing a peripheral logic power supply, and charging the second bit line through a second peripheral precharge subunit accessing the peripheral logic power supply;

after the first-stage charging is finished, the first bit line is charged by accessing the first array pre-charging subunit to the memory array power supply, and the second bit line is charged by accessing the second array pre-charging subunit to the memory array power supply.

7. The method of claim 6, wherein said accessing a peripheral logic power supply through the first peripheral precharge subunit to charge the first bit line and accessing a peripheral logic power supply through a second peripheral precharge subunit to charge the second bit line comprises:

8. The method of claim 7, wherein said accessing the peripheral logic power supply through the first peripheral precharge subunit to charge the first bit line to a specified voltage and accessing the peripheral logic power supply through a second peripheral precharge subunit to charge the second bit line to the specified voltage comprises:

9. A memory, comprising: the sram control circuit of any one of claims 1-8.

10. A processor, comprising: the memory of claim 9.

11. An electronic device, comprising: the processor of claim 10.