CN112099411A - Improved equipment data acquisition terminal based on FPGA and use method thereof - Google Patents
Improved equipment data acquisition terminal based on FPGA and use method thereof Download PDFInfo
- Publication number
- CN112099411A CN112099411A CN202011006254.6A CN202011006254A CN112099411A CN 112099411 A CN112099411 A CN 112099411A CN 202011006254 A CN202011006254 A CN 202011006254A CN 112099411 A CN112099411 A CN 112099411A
- Authority
- CN
- China
- Prior art keywords
- fpga
- board
- data acquisition
- data
- shell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Bus Control (AREA)
Abstract
The invention relates to the technical field of communication, and discloses an improved equipment data acquisition terminal based on FPGA (field programmable gate array), which comprises a shell, an integrated board which is detachably arranged in the shell, and a data acquisition processing board, an AD (analog-to-digital) data conversion board and a digital signal processing DSP (digital signal processor) board which are arranged in the shell, wherein the data acquisition processing board based on FPGA is used for sending an AD data acquisition conversion control time sequence, starting data acquisition by controlling the falling edge of FPGA and starting A/D (analog-to-digital) conversion by controlling the AD data conversion board by the rising edge of FPGA; the AD data conversion board is connected with the FPGA-based data acquisition and processing board and is used for converting the acquired data according to a conversion control instruction found by the FPGA-based data acquisition and processing board. The invention does not need exclusive operation, ensures the real-time of data acquisition and conversion to the maximum extent, reduces the overhead of other hardware of the system and facilitates the installation and the disassembly of the integrated board and the shell.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an improved equipment data acquisition terminal based on an FPGA (field programmable gate array).
Background
At present, in various industries of industrial production and scientific and technical research, various data are often required to be acquired, such as acquisition of information of liquid level, temperature, pressure, frequency and the like. In some fields such as image processing, transient signal detection, software radio and the like, a data acquisition technology with high speed, high precision and high real-time performance is required.
The data acquisition system is used for processing the analog signals output by the acquisition sensor and converting the analog signals into digital signals which can be identified by a computer, and the computer performs corresponding calculation and processing to meet different requirements and obtain required data. The performance of the data acquisition system is determined by its accuracy and speed. On the premise of ensuring the precision, the requirement of real-time acquisition, real-time processing and real-time control on the speed can be met only by using the acquisition speed as high as possible.
The existing acquisition module has the following problems:
first, the sampling rate is low. The data acquisition module adopts a 12-channel A/D serial acquisition method, is gated by a 38 decoder, is communicated with the singlechip in a port simulation SPI mode, and takes 1ms for single-channel acquisition, and the 12-channel cycle period is 12 ms.
Second, data access arbitration is slow. For example, when the CPU11 module and the single-ended SRAM are shared by the single-ended SRAM and the CPLD is used as the multiplexer, at least 14 instruction cycles are required for locking and releasing the bus for each access of the single-ended SRAM by the single-ended SRAM. Meanwhile, the modules use an interrupt mode to inform the CPU11 of bus occupation, so that the CPU11 is in an interrupt state for a long time and the response speed of the integrated controller is influenced.
Disclosure of Invention
The invention aims to provide an improved equipment data acquisition terminal based on an FPGA (field programmable gate array) so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
improved generation equipment data acquisition terminal based on FPGA, including the shell, can dismantle the integrated board of locating in the shell and install the data acquisition who is based on FPGA in the shell and handle the board, AD data conversion board, digital signal processing DSP board.
The FPGA-based data acquisition and processing board is used for sending an AD data acquisition and conversion control time sequence, controlling the data acquisition by the falling edge of the FPGA and controlling the AD data conversion board to start A/D conversion by the rising edge of the FPGA; and the system is also used for storing the acquired data into a double-port RAM realized in the FPGA.
The AD data conversion board is connected with the FPGA-based data acquisition and processing board and is used for converting the acquired data according to the conversion control instruction found by the FPGA-based data acquisition and processing board.
And the digital signal processing DSP board is connected with the FPGA-based data acquisition and processing board and is used for asynchronously reading the acquired data through the dual-port RAM, filtering the data and simultaneously returning the filtered data to the FPGA.
The shell comprises a fixed shell, an overturning shell and an end cover, the fixed shell, the overturning shell and the end cover form a rectangular box-shaped structure, a side plate of the fixed shell is provided with a notch, one side of the overturning shell is provided with a connecting part located in the notch, the connecting part and the inner wall of the notch are connected in a rotating mode through a pin shaft, and a driving gear is sleeved on the pin shaft in a rotating mode.
The integrated board is arranged in the fixed shell, and a positioning mechanism for fixing the integrated board is arranged in the fixed shell.
Positioning mechanism is including rotating the pivot of connection in the fixed casing, and fixed mounting is changeing epaxial driven gear, the winding is fixed with the haulage rope in the pivot, still is equipped with the fixed pulley in the fixed casing, and the fixed pulley is walked around to the one end of haulage rope and be connected with the reference column, one side fixed connection pole of reference column, the other end and the fixed shells inner wall sliding connection of connecting rod, set up on the integrated board with reference column complex constant head tank, the notch is seted up to one side of integrated board, and sliding connection has the extrusion piece that can stretch out the integrated board in the notch, and extrusion piece and notch inner wall pass through first spring coupling, and connecting rod and fixed shells inner wall pass through second spring coupling.
Further, the system further comprises: and the synchronous dynamic random access memory SDRAM board is connected with the digital signal processing DSP board and is used for dynamically storing relevant data of the DSP board.
Furthermore, the data acquisition processing board based on the FPGA is provided with a communication interface with an external CPU, and the communication interface is used for the CPU to read the filtered data in the data acquisition processing board.
Furthermore, the AD data conversion board is at least two 6-path PCB boards; the data acquisition processing board is a PCB board, and the FPGA on the board is used for generating a 12-channel AD data acquisition time sequence.
Further, the AD data conversion board is an AD7893 chip, and the cycle of the AD data acquisition conversion control time sequence is 12 us.
Further, the data acquisition and processing board based on the FPGA is divided into four areas, including: the device comprises an AD data acquisition and conversion time sequence control area, a VBUS bus interface communication area, a DSPEMIF bus interface communication area and a double-port RAM area.
The use method of the improved equipment data acquisition terminal based on the FPGA comprises the following steps: sending an AD data acquisition conversion control time sequence by the FPGA, controlling an AD chip by the rising edge of the FPGA to start A/D conversion, and controlling the falling edge of the FPGA in the FPGA to start data acquisition; and realizing double-port RAM by using residual resources in the FPGA, and asynchronously receiving AD data and processing the data.
The invention has the beneficial effects that:
according to the invention, by optimizing an acquisition time sequence, an AD data acquisition conversion control time sequence is sent by an FPGA, the AD chip is controlled by an FPGA rising edge to start A/D conversion, and the FPGA falling edge is controlled to start data acquisition; the dual-port RAM is realized by utilizing the residual resources in the FPGA, AD data receiving and data processing are asynchronously carried out, mutual exclusion operation is not needed, the real-time performance of data acquisition and conversion is ensured to the maximum extent, and meanwhile, the other hardware overhead of the system is reduced.
The terminal comprises a shell, a data acquisition processing board based on an FPGA, an AD data conversion board and a digital signal processing DSP board which are all arranged on an integrated board, and the integrated board can be automatically popped out through rotating and overturning a shell on the shell, so that the terminal is convenient to use and mount and dismount.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a functional block diagram of an FPGA-based AD data acquisition system of the present invention;
FIG. 2 is a functional block diagram internal to the FPGA of the present invention;
FIG. 3 is a front view of the internal structure of the housing of the present invention;
FIG. 4 is a top view of the housing structure of the present invention;
fig. 5 is an enlarged view of fig. 3 at a according to the present invention.
In the figure: the integrated board comprises an integrated board 1, a notch 101, a fixed shell 201, a turnover shell 202, a connecting part 21, an end cover 3, a driving gear 4, a rotating shaft 5, a driven gear 6, a traction rope 7, a fixed pulley 8, a connecting rod 9, a positioning column 10, a positioning groove 11, a notch 12, an extrusion block 13, a first spring 14 and a second spring 16.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
referring to fig. 1-5, the improved data acquisition terminal based on FPGA comprises a housing, an integrated board 1 detachably disposed in the housing, and a data acquisition processing board, an AD data conversion board, and a digital signal processing DSP board mounted in the housing and based on FPGA.
The FPGA-based data acquisition and processing board is used for sending an AD data acquisition and conversion control time sequence, controlling the data acquisition by the falling edge of the FPGA and controlling the AD data conversion board to start A/D conversion by the rising edge of the FPGA; and the system is also used for storing the acquired data into a double-port RAM realized in the FPGA.
The AD data conversion board is connected with the FPGA-based data acquisition and processing board and is used for converting the acquired data according to the conversion control instruction found by the FPGA-based data acquisition and processing board.
And the digital signal processing DSP board is connected with the FPGA-based data acquisition and processing board and is used for asynchronously reading the acquired data through the dual-port RAM, filtering the data and simultaneously returning the filtered data to the FPGA.
The shell includes fixed casing 201, upset casing 202 and end cover 3, and fixed casing 201 constitutes rectangle box-like structure with upset casing and end cover 3, and breach 101 is seted up to fixed casing 201's a curb plate, and one side of upset casing 202 has the connecting portion 21 that is located breach 101, and connecting portion 21 and breach 101 inner wall rotate through the round pin axle and connect, and the epaxial rotation of round pin has cup jointed driving gear 4.
The integrated board 1 is arranged in the fixed shell 201, and a positioning mechanism for fixing the integrated board 1 is arranged in the fixed shell 201.
Positioning mechanism is including rotating pivot 5 of connection in fixed casing 201, and fixed mounting is at the epaxial driven gear 6 of pivot 5, and driven gear 6 is connected with the meshing of driving gear 4, the winding is fixed with haulage rope 7 in the pivot 5, still is equipped with fixed pulley 8 in the fixed casing 201, and fixed pulley 8 is walked around to the one end of haulage rope 7 and is connected with reference column 10, one side fixed connection pole 9 of reference column 10, the other end and the fixed casing 201 inner wall sliding connection of connecting rod 9, set up on the integrated board 1 with reference column 10 complex constant head tank 11, notch 12 is seted up to one side of integrated board 1, and sliding connection has the extrusion piece 13 that can stretch out integrated board 1 in the notch 12, and extrusion piece 13 and notch 12 inner wall are connected through first spring 14, and connecting rod 9 and fixed casing 201 inner wall are connected through second spring 16.
Further, the system further comprises: and the synchronous dynamic random access memory SDRAM board is connected with the digital signal processing DSP board and is used for dynamically storing relevant data of the DSP board.
Furthermore, the data acquisition processing board based on the FPGA is provided with a communication interface with an external CPU, and the communication interface is used for the CPU to read the filtered data in the data acquisition processing board.
Furthermore, the AD data conversion board is at least two 6-path PCB boards; the data acquisition processing board is a PCB board, and the FPGA on the board is used for generating a 12-channel AD data acquisition time sequence.
Further, the AD data conversion board is an AD7893 chip, and the cycle of the AD data acquisition conversion control time sequence is 12 us.
Further, the data acquisition and processing board based on the FPGA is divided into four areas, including: the device comprises an AD data acquisition and conversion time sequence control area, a VBUS bus interface communication area, a DSPEMIF bus interface communication area and a double-port RAM area.
The use method of the improved equipment data acquisition terminal based on the FPGA comprises the following steps: sending an AD data acquisition conversion control time sequence by the FPGA, controlling an AD chip by the rising edge of the FPGA to start A/D conversion, and controlling the falling edge of the FPGA in the FPGA to start data acquisition; and realizing double-port RAM by using residual resources in the FPGA, and asynchronously receiving AD data and processing the data.
When the shell that this device provided is assembled with integrated board 1, it makes it turn up to rotate upset casing 202, driving gear 4 rotates along with the round pin axle, driving gear 4 drive driven gear 6 rotates, driven gear 6 drives pivot 5 and rotates, thereby make haulage rope 7 twine gradually and draw in on pivot 5, the terminal pulling reference column 10 of haulage rope 7 moves up, make reference column 10 and the separation of constant head tank 11 on the integrated board 1, and under the restoring force effect of first spring 14, the opening department that appears is opened from end cover 3 to the extrusion piece 13 promotion integrated board.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. The improved equipment data acquisition terminal based on the FPGA comprises a shell, an integrated board (1) which is detachably arranged in the shell, and a data acquisition processing board, an AD data conversion board and a digital signal processing DSP board which are arranged in the shell and are based on the FPGA;
wherein the content of the first and second substances,
the FPGA-based data acquisition and processing board is used for sending an AD data acquisition and conversion control time sequence, controlling the data acquisition by the falling edge of the FPGA and controlling the AD data conversion board to start A/D conversion by the rising edge of the FPGA; the system is also used for storing the acquired data into a double-port RAM realized in the FPGA;
the AD data conversion board is connected with the FPGA-based data acquisition and processing board and is used for converting the acquired data according to a conversion control instruction found by the FPGA-based data acquisition and processing board;
the digital signal processing DSP board is connected with the FPGA-based data acquisition and processing board and is used for asynchronously reading the acquired data through the dual-port RAM, filtering the data and simultaneously returning the filtered data to the FPGA;
the shell comprises a fixed shell (201), an overturning shell (202) and an end cover (3), the fixed shell (201), the overturning shell and the end cover (3) form a rectangular box-shaped structure, a notch (101) is formed in one side plate of the fixed shell (201), a connecting part (21) located in the notch (101) is arranged on one side of the overturning shell (202), the connecting part (21) is rotatably connected with the inner wall of the notch (101) through a pin shaft, and a driving gear (4) is rotatably sleeved on the pin shaft;
the integrated board (1) is arranged in the fixed shell (201), and a positioning mechanism for fixing the integrated board (1) is arranged in the fixed shell (201);
the positioning mechanism comprises a rotating shaft (5) rotatably connected in a fixed shell (201), and a driven gear (6) fixedly installed on the rotating shaft (5), wherein a traction rope (7) is wound and fixed on the rotating shaft (5), a fixed pulley (8) is further arranged in the fixed shell (201), one end of the traction rope (7) bypasses the fixed pulley (8) and is connected with a positioning column (10), a connecting rod (9) is fixed on one side of the positioning column (10), the other end of the connecting rod (9) is slidably connected with the inner wall of the fixed shell (201), a positioning groove (11) matched with the positioning column (10) is formed in the integrated plate (1), a notch (12) is formed in one side of the integrated plate (1), an extrusion block (13) capable of extending out the integrated plate (1) is slidably connected in the notch (12), and the extrusion block (13) is connected with the inner wall of the notch (12) through a first spring (, and the connecting rod (9) is connected with the inner wall of the fixed shell (201) through a second spring (16).
2. The FPGA-based AD data acquisition system of claim 1, further comprising: and the synchronous dynamic random access memory SDRAM board is connected with the digital signal processing DSP board and is used for dynamically storing relevant data of the DSP board.
3. The FPGA-based AD data collection system of claim 1, wherein the FPGA-based data collection processing board has a communication interface with an external CPU for the CPU to read the filtered data in the data collection processing board.
4. The FPGA-based AD data acquisition system of any one of claims 1-3, wherein the AD data conversion board is at least two 6-way PCB boards; the data acquisition processing board is a PCB board, and the FPGA on the board is used for generating a 12-channel AD data acquisition time sequence.
5. The FPGA-based AD data acquisition system of claim 6, wherein the AD data conversion board is an AD7893 chip, and the period of the AD data acquisition conversion control timing sequence is 12 us.
6. The FPGA-based AD data collection system of claim 1, wherein the FPGA-based data collection processing board is divided into four zones comprising: the device comprises an AD data acquisition and conversion time sequence control area, a VBUS bus interface communication area, a DSPEMIF bus interface communication area and a double-port RAM area.
7. The use method of the improved equipment data acquisition terminal based on the FPGA comprises the following steps: sending an AD data acquisition conversion control time sequence by the FPGA, controlling an AD chip by the rising edge of the FPGA to start A/D conversion, and controlling the falling edge of the FPGA in the FPGA to start data acquisition; and realizing double-port RAM by using residual resources in the FPGA, and asynchronously receiving AD data and processing the data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011006254.6A CN112099411B (en) | 2020-09-23 | 2020-09-23 | Improved equipment data acquisition terminal based on FPGA and use method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011006254.6A CN112099411B (en) | 2020-09-23 | 2020-09-23 | Improved equipment data acquisition terminal based on FPGA and use method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112099411A true CN112099411A (en) | 2020-12-18 |
| CN112099411B CN112099411B (en) | 2022-10-14 |
Family
ID=73755880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011006254.6A Active CN112099411B (en) | 2020-09-23 | 2020-09-23 | Improved equipment data acquisition terminal based on FPGA and use method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112099411B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060061048A1 (en) * | 2004-09-20 | 2006-03-23 | Daniel Puzio | Tool chuck with power take off feature |
| CN101397811A (en) * | 2008-10-08 | 2009-04-01 | 章建成 | Seat bowl with automatic plugging apparatus |
| CN101428666A (en) * | 2007-11-11 | 2009-05-13 | 戴伟 | Wire rope driven slide pedal drive type exercising cycle |
| CN101606817A (en) * | 2009-07-08 | 2009-12-23 | 徐丽琴 | A kind of window curtain lockset |
| CN101904683A (en) * | 2009-12-25 | 2010-12-08 | 黄介仁 | Curtain |
| CN107066200A (en) * | 2017-03-14 | 2017-08-18 | 北京航天自动控制研究所 | A kind of collecting method and data collecting system based on FPGA |
| CN207473479U (en) * | 2017-12-13 | 2018-06-08 | 江苏财会职业学院 | Data acquisition platform based on big data processing |
| CN108563051A (en) * | 2018-06-20 | 2018-09-21 | 湖州升谱电子科技有限公司 | A kind of automatic polarisation machine discharger |
| CN209168228U (en) * | 2019-02-19 | 2019-07-26 | 谭文全 | A kind of computer room identification gate control system with trigger architecture |
| CN111086804A (en) * | 2020-03-19 | 2020-05-01 | 刘庆 | Garbage can capable of sorting recyclable garbage |
-
2020
- 2020-09-23 CN CN202011006254.6A patent/CN112099411B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060061048A1 (en) * | 2004-09-20 | 2006-03-23 | Daniel Puzio | Tool chuck with power take off feature |
| CN101428666A (en) * | 2007-11-11 | 2009-05-13 | 戴伟 | Wire rope driven slide pedal drive type exercising cycle |
| CN101397811A (en) * | 2008-10-08 | 2009-04-01 | 章建成 | Seat bowl with automatic plugging apparatus |
| CN101606817A (en) * | 2009-07-08 | 2009-12-23 | 徐丽琴 | A kind of window curtain lockset |
| CN101904683A (en) * | 2009-12-25 | 2010-12-08 | 黄介仁 | Curtain |
| CN107066200A (en) * | 2017-03-14 | 2017-08-18 | 北京航天自动控制研究所 | A kind of collecting method and data collecting system based on FPGA |
| CN207473479U (en) * | 2017-12-13 | 2018-06-08 | 江苏财会职业学院 | Data acquisition platform based on big data processing |
| CN108563051A (en) * | 2018-06-20 | 2018-09-21 | 湖州升谱电子科技有限公司 | A kind of automatic polarisation machine discharger |
| CN209168228U (en) * | 2019-02-19 | 2019-07-26 | 谭文全 | A kind of computer room identification gate control system with trigger architecture |
| CN111086804A (en) * | 2020-03-19 | 2020-05-01 | 刘庆 | Garbage can capable of sorting recyclable garbage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112099411B (en) | 2022-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201194139Y (en) | Intellectualized robot platform with teaching and intelligent function | |
| CN102496294A (en) | Multifunctional vehicle-mounted monitoring and scheduling terminal based on third-generation (3G) network | |
| CN202502713U (en) | LED display screen controller based on SOPC | |
| CN112099411B (en) | Improved equipment data acquisition terminal based on FPGA and use method thereof | |
| CN211956463U (en) | I/O (input/output) bridge piece based on Feiteng processor | |
| CN101770420A (en) | System on chip (SOC) debugging structure and method for realizing output of debugging information | |
| WO2022027846A1 (en) | Soc chip structure applied to steering engine control system | |
| CN206146450U (en) | Measurement system of low -power consumption | |
| CN203376672U (en) | Portable integrated data processor | |
| CN102841878A (en) | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) | |
| CN209607117U (en) | A kind of Intelligent earthquake alarm | |
| CN203386342U (en) | Wireless data acquisition terminal | |
| CN201072511Y (en) | Industrial mainboard for supporting PCI-E based on PICMG1.0 | |
| CN112394770A (en) | Touch industrial computer with protection function | |
| CN202735722U (en) | ISA interface IP core of novel PLB bus | |
| CN206251226U (en) | Vehicle-mounted law enforcement recorder | |
| CN201935947U (en) | Control device for handheld digital oscilloscope | |
| CN208796061U (en) | A kind of vibration signal collector based on WiFi | |
| CN213584130U (en) | Large-scale short wave antenna slewing mechanism | |
| CN214177459U (en) | Violence abnormal behavior detection system | |
| CN214959976U (en) | Industrial instrument low-power consumption data wireless acquisition terminal | |
| CN213236797U (en) | Computer remote control device based on single chip microcomputer control | |
| CN103401660B (en) | The decoding system and method for orthogonal signalling based on Cortex kernel single-chip microcomputer | |
| CN104331046A (en) | Spectrometer signal acquisition system and acquisition method | |
| CN208635914U (en) | A kind of vibration signal collector based on Ethernet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |