CN112086437A - ESD protection packaging structure and manufacturing method thereof - Google Patents
ESD protection packaging structure and manufacturing method thereof Download PDFInfo
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- CN112086437A CN112086437A CN202010763742.5A CN202010763742A CN112086437A CN 112086437 A CN112086437 A CN 112086437A CN 202010763742 A CN202010763742 A CN 202010763742A CN 112086437 A CN112086437 A CN 112086437A
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- heat dissipation
- dissipation metal
- metal column
- esd protection
- rewiring layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to an ESD protection packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a first packaging body and a second packaging body, wherein the first packaging body is stacked on the second packaging body; the first packaging body comprises a first rewiring layer, a first radiating metal sheet is attached to the back of the first rewiring layer, a first radiating metal column is arranged in the first rewiring layer, and the lower end of the first radiating metal column is connected with the first radiating metal sheet; the second packaging body comprises a second rewiring layer, a second heat dissipation metal sheet is attached to the back of the second rewiring layer, a second heat dissipation metal column is arranged in the second rewiring layer, and the lower end of the second heat dissipation metal column is connected with the second heat dissipation metal sheet. According to the invention, the rewiring layer, the heat dissipation metal sheet and the LC circuit are integrated into a laminated packaging structure, so that the packaging thickness is reduced, the problems of ESD electricity and heat are solved, and the difficulty in chip design is reduced.
Description
Technical Field
The invention relates to an ESD protection packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging.
Background
At present, the integration level of electronic products is higher and higher, the sensitivity to ESD (Electro-Static discharge) is higher and higher, and the prevention of electrostatic damage is the first problem in all IC designs and manufactures. At present, most measures are to use a protection circuit or a module which is composed of a PN junction/diode, a triode, an MOS tube and the like. For a number of reasons, the ESD protection function inside an IC is somewhat compromised, and both silicon and metal are optimized for the core function of the IC and are not suitable for high current operation. In addition, the I/O cells with high current ESD protection occupy a considerable amount of space, thereby driving up IC cost. Also, the high frequency pins on the IC are often not available for attaching large sized ESD protection circuits because it creates capacitive loading. Meanwhile, in the process of electrostatic discharge, not only electricity but also heat are generated, which all have an influence. At present, the mainstream measure of the packaging end is to add an ESD protection device in a board level, so that the size and the occupied space are larger.
Disclosure of Invention
The invention aims to solve the technical problem of providing an ESD protection packaging structure and a manufacturing method thereof aiming at the prior art, wherein a rewiring layer, a heat dissipation metal sheet and an LC circuit are integrated into a laminated packaging structure, so that the packaging thickness is reduced, the problems of electrostatic discharge and heat dissipation are solved, and the difficulty of chip design is reduced.
The technical scheme adopted by the invention for solving the problems is as follows: an ESD protection packaging structure comprises a first packaging body and a second packaging body, wherein the first packaging body is stacked on the second packaging body;
the first packaging body comprises a first rewiring layer, a first heat dissipation metal sheet is attached to the back surface of the first rewiring layer, a first chip is attached to the front surface of the first rewiring layer, and a first plastic packaging material is encapsulated on the periphery of the first chip;
the second packaging body comprises a second rewiring layer, a second heat dissipation metal sheet is attached to the back of the second rewiring layer, a second chip is attached to the front of the second rewiring layer, a second plastic package material is wrapped on the periphery of the second chip, a second heat dissipation metal column is arranged in the second rewiring layer, the lower end of the second heat dissipation metal column is connected with the second heat dissipation metal sheet, and the upper end of the second heat dissipation metal column penetrates through the whole second plastic package material and then is connected with the first heat dissipation metal sheet.
Optionally, an electrical metal pillar is arranged in the second plastic package material, and the first redistribution layer and the second redistribution layer are electrically connected through the electrical metal pillar.
Optionally, the upper surface of the second chip is exposed out of the second molding compound and is in contact with the first heat dissipation metal sheet.
Optionally, the first redistribution layer includes a first redistribution layer, a first insulating material is coated on the periphery of the first redistribution layer, a first heat dissipation metal hole is formed in the first insulating material, and the first heat dissipation metal column is disposed in the first heat dissipation metal hole; the first radiating metal sheet is provided with a first opening, the back surface of the first rewiring is provided with a first outer contact point, the position of the first outer contact point corresponds to the position of the first opening, and the first outer contact point is exposed out of the first opening.
Optionally, the second redistribution layer includes a second redistribution, a second insulating material is coated on the periphery of the second redistribution, a second heat dissipation metal hole is formed in the second insulating material, and the second heat dissipation metal column is disposed in the second heat dissipation metal hole; the second heat dissipation metal sheet is provided with a second opening, the back of the second rewiring is provided with a second external contact point, the position of the second external contact point corresponds to the position of the second opening, and the second external contact point is exposed out of the second opening.
Optionally, a solder ball is disposed on the second outer contact.
Optionally, an LC circuit unit is further attached to the front surface of the second redistribution layer, and one end of the LC circuit unit is connected to the second heat dissipation metal column.
Optionally, the LC circuit unit is directly produced by using a thin film passive device process.
Optionally, a first heat dissipation metal column is arranged in the first redistribution layer, and the lower end of the first heat dissipation metal column is connected with the first heat dissipation metal sheet
A method of manufacturing an ESD protection package structure, the method comprising:
step one, taking a carrier plate, and mounting a second heat dissipation metal sheet on the carrier plate, wherein the second heat dissipation metal sheet is provided with a second opening;
forming an under-ball metal layer at the second opening, wherein the under-ball metal layer is not connected with the second heat dissipation metal sheet;
thirdly, preparing a second rewiring and the lower part of a second heat dissipation metal column on the second heat dissipation metal sheet and the under-ball metal layer, wherein a second insulating material is coated on the periphery of the lower parts of the second rewiring and the second heat dissipation metal column to form a second rewiring layer;
forming an electrical metal column and the upper part of a second heat dissipation metal column on the second rewiring layer, forming a complete second metal column on the upper part of the second heat dissipation metal column and the lower part of the second heat dissipation metal column, and attaching a second chip and an LC circuit unit to corresponding positions on the second rewiring layer;
step five, plastic packaging is carried out on the upper portion of the second rewiring layer by adopting a second plastic packaging material to form a second packaging body, and the upper surfaces of the electrically-conductive metal columns and the second heat-dissipation metal columns are exposed out of the second plastic packaging material after the plastic packaging;
removing the carrier plate, and mounting the first packaging body on the second packaging body, wherein the first packaging body is electrically connected with the second packaging body through the electric metal column;
and step seven, carrying out ball planting on the back of the second packaging body.
Optionally, in the fourth step, one end of the LC circuit unit is connected to the second heat dissipation metal pillar.
Optionally, after plastic packaging in the fifth step, the upper surface of the second chip is exposed out of the second plastic packaging material.
Optionally, in the sixth step, a first heat dissipation metal sheet is disposed at the bottom of the first package body, and the first heat dissipation metal sheet is connected to the upper surface of the second heat dissipation metal column in the second package body.
Compared with the prior art, the invention has the advantages that:
1. the invention uses the rewiring layer as a bearing structure, thereby reducing the thickness of the stacked package;
2. the invention can rapidly conduct heat generated by static electricity by adding the mutually communicated heat dissipation metal sheet and the heat dissipation metal column and connecting the heat dissipation metal sheet and the heat dissipation metal column with the internal circuit, thereby enhancing the heat dissipation capability, the current drainage capability and the structural stability of the packaging structure;
3. the mutually communicated heat dissipation metal columns and the heat dissipation metal sheets can be used as grounding ends, so that the static electricity leading-out path is increased, and the electrical property can be improved;
4. according to the invention, the LC circuit is independently arranged outside the chip, so that the ESD protection part which needs to be integrated inside the chip originally can be reduced, the size and the design difficulty of the chip are reduced, and the yield of the chip is increased.
Drawings
Fig. 1 is a schematic diagram of an ESD protection package structure according to the present invention.
Fig. 2 to fig. 8 are schematic views illustrating process flows of a method for manufacturing an ESD protection package structure according to the present invention.
Fig. 9 is a schematic diagram of the LC circuit.
Fig. 10 is a schematic plan view of an LC circuit.
Wherein:
First rewiring layer 11
First rewiring 11.1
First insulating material 11.2
First heat dissipation metal hole 11.3
First outer contact point 11.4
First heat dissipation metal sheet 12
First opening 12.1
First heat dissipation metal column 15
Second rewiring layer 21
Second redistribution line 21.1
Second insulating material 21.2
Second heat dissipation metal hole 21.3
Second outer contact point 21.4
Second heat sink metal sheet 22
Second opening 22.1
Second heat-dissipating metal post 25
And (3) solder balls.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
As shown in fig. 1, the ESD protection package structure according to the present invention includes a first package 1 and a second package 2, wherein the first package 1 is stacked on the second package 2;
the first package body 1 comprises a first redistribution layer 11, a first heat dissipation metal sheet 12 is attached to the back surface of the first redistribution layer 11, a first chip 13 is attached to the front surface of the first redistribution layer 11, a first plastic package material 14 is encapsulated on the periphery of the first chip 13, a first heat dissipation metal column 15 is arranged in the first redistribution layer 11, and the lower end of the first heat dissipation metal column 15 is connected with the first heat dissipation metal sheet 12;
the second package body 2 comprises a second rewiring layer 21, a second heat dissipation metal sheet 22 is attached to the back surface of the second rewiring layer 21, a second chip 23 is attached to the front surface of the second rewiring layer 21, a second plastic package material 24 is encapsulated on the periphery of the second chip 23, a second heat dissipation metal column 25 is arranged in the second rewiring layer 21, the lower end of the second heat dissipation metal column 25 is connected with the second heat dissipation metal sheet 22, and the upper end of the second heat dissipation metal column 25 penetrates through the whole second plastic package material 24 and then is connected with the first heat dissipation metal sheet 12;
an electrical metal post 26 is arranged in the second plastic package material 24, and the first redistribution layer 11 and the second redistribution layer 21 are electrically connected through the electrical metal post 26;
the upper surface of the second chip 23 is exposed out of the second molding compound 24 and is in contact with the first heat dissipation metal sheet 12;
the first rewiring layer 11 comprises a plurality of layers of first rewirings 11.1 and a first insulating material 11.2, first heat dissipation metal holes 11.3 are formed in the first insulating material 11.2, and first heat dissipation metal columns 15 are arranged in the first heat dissipation metal holes 11.3;
a first opening 12.1 is formed in the first heat dissipation metal sheet 12, a first external contact point 11.4 is arranged on the back surface of the first redistribution layer 11.1, the position of the first external contact point 11.4 corresponds to the position of the first opening 12.1, and the first external contact point 11.4 is exposed out of the first opening 12.1;
the second redistribution layer 21 includes a plurality of layers of second redistribution lines 21.1 and a second insulating material 21.2, a second heat dissipation metal hole 21.3 is formed in the second insulating material 21.2, and the second heat dissipation metal column 25 is disposed in the second heat dissipation metal hole 21.3;
a second opening 22.1 is formed in the second heat dissipation metal sheet 22, a second external contact point 21.4 is formed on the back surface of the second redistribution line 21.1, the position of the second external contact point 21.4 corresponds to the position of the second opening 22.1, and the second external contact point 21.4 is exposed from the position of the second opening 22.1;
the upper end and the lower end of the electric metal column 26 are respectively connected with the first redistribution line 11.1 and the second redistribution line 21.1;
the second outer contact point 21.4 is connected with a solder ball 3;
the front surface of the second redistribution layer 21 is further attached with an LC circuit unit 27, and one end of the LC circuit unit 27 is connected with the second heat dissipation metal column 25.
The manufacturing method comprises the following steps:
step one, referring to fig. 2, a carrier plate is taken, and a second heat dissipation metal sheet is attached to the carrier plate, wherein the second heat dissipation metal sheet is provided with a second opening;
step two, referring to fig. 3, photoresist is coated at the second opening position, an under-ball metal layer (i.e., a second external contact point) is formed by photoetching, electroplating and sputtering, and the under-ball metal layer is not connected with the second heat dissipation metal sheet;
step three, referring to fig. 4, coating PI (polyimide) as a redistributed polymer layer on the second heat dissipation metal sheet and the under-ball metal layer, and performing photolithography and electroplating to prepare a plurality of layers of second redistribution lines, the lower portions of the second heat dissipation metal columns and a second insulating material, thereby forming a second redistribution layer;
step four, referring to fig. 5, forming an electrical metal column and an upper portion of a second heat dissipation metal column (the upper portion of the second heat dissipation metal column and the lower portion of the second heat dissipation metal column form a complete second metal column) on the second redistribution layer by photolithography and electroplating, and attaching a second chip and an LC circuit unit to corresponding positions on the second redistribution layer, wherein one end of the LC circuit unit is connected with the second heat dissipation metal column;
step five, referring to fig. 6, plastic packaging is performed on the upper portion of the second rewiring layer by using a second plastic packaging material to form a second packaging body, and the upper surfaces of the second chip, the electrical metal column and the second heat dissipation metal column are exposed out of the second plastic packaging material after the plastic packaging;
sixthly, referring to fig. 7, removing the carrier plate, and mounting the first package body on the second package body, wherein the first package body is electrically connected with the second package body through the electrical metal column;
the first packaging body comprises a first rewiring layer, a first chip is attached to the front side of the first rewiring layer, a first plastic packaging material is packaged on the periphery of the first chip, a first heat dissipation metal sheet is attached to the back side of the first rewiring layer, a first opening is formed in the first heat dissipation metal sheet, a first heat dissipation metal column is arranged in the first rewiring layer, the lower end of the first heat dissipation metal column is connected with the first heat dissipation metal sheet, and a first external contact point of the first rewiring layer is connected with a second rewiring layer through an electric metal column;
step seven, referring to fig. 8, the ball is planted on the under-ball metal layer on the back of the second package body.
As shown in fig. 9 and 10, the LC circuit unit in step four is formed by connecting an LC circuit in parallel between IUPUT (input terminal) and OUTPUT (OUTPUT terminal), and blocking and draining the static electricity by the filtering action of the inductor and the capacitor, so as to greatly reduce the energy of the static electricity. The LC circuit unit can be directly produced by a thin film passive device process, and is attached to the surface of the second redistribution layer in a surface mount manner, and one end of the LC circuit unit is connected to the second heat dissipation metal column, so that a grounding function is realized, as shown in fig. 5. Although the module can be integrated in the rewiring layer, the rewiring area and difficulty are increased, and therefore the module is separately made into a component for mounting, and the space can be reasonably utilized.
In addition, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the protection scope of the claims of the present invention.
Claims (13)
1. An ESD protection packaging structure is characterized in that: the packaging structure comprises a first packaging body (1) and a second packaging body (2), wherein the first packaging body (1) is stacked on the second packaging body (2);
the first packaging body (1) comprises a first rewiring layer (11), a first heat dissipation metal sheet (12) is attached to the back surface of the first rewiring layer (11), a first chip (13) is attached to the front surface of the first rewiring layer (11), and a first plastic packaging material (14) is encapsulated on the periphery of the first chip (13);
the second packaging body (2) comprises a second rewiring layer (21), a second heat dissipation metal sheet (22) is attached to the back surface of the second rewiring layer (21), a second chip (23) is attached to the front surface of the second rewiring layer (21), a second plastic packaging material (24) is packaged on the periphery of the second chip (23), a second heat dissipation metal column (25) is arranged in the second rewiring layer (21), the lower end of the second heat dissipation metal column (25) is connected with the second heat dissipation metal sheet (22), and the upper end of the second heat dissipation metal column (25) penetrates through the whole second plastic packaging material (24) and then is connected with the first heat dissipation metal sheet (12).
2. The ESD protection package structure of claim 1, wherein: an electric metal column (26) is arranged in the second plastic packaging material (24), and the first redistribution layer (11) is electrically connected with the second redistribution layer (21) through the electric metal column (26).
3. The ESD protection package structure of claim 1, wherein: the upper surface of the second chip (23) is exposed out of the second molding compound (24) and is in contact with the first heat dissipation metal sheet (12).
4. The ESD protection package structure of claim 1, wherein: the first rewiring layer (11) comprises a plurality of layers of first rewirings (11.1) and a first insulating material (11.2), a first heat dissipation metal hole (11.3) is formed in the first insulating material (11.2), and the first heat dissipation metal column (15) is arranged in the first heat dissipation metal hole (11.3); the first radiating metal sheet (12) is provided with a first opening (12.1), the back of the first rewiring (11.1) is provided with a first outer contact point (11.4), the position of the first outer contact point (11.4) corresponds to the position of the first opening (12.1), and the first outer contact point (11.4) is exposed out of the position of the first opening (12.1).
5. The ESD protection package structure of claim 1, wherein: the second rewiring layer (21) comprises a plurality of layers of second rewirings (21.1) and a second insulating material (21.2), a second heat dissipation metal hole (21.3) is formed in the second insulating material (21.2), and the second heat dissipation metal column (25) is arranged in the second heat dissipation metal hole (21.3); the second heat dissipation metal sheet (22) is provided with a second opening (22.1), the back of the second rewiring (21.1) is provided with a second external contact point (21.4), the position of the second external contact point (21.4) corresponds to the position of the second opening (22.1), and the second external contact point (21.4) is exposed out of the second opening (22.1).
6. The ESD protection package structure according to claim 5, wherein: and a solder ball (3) is arranged on the second outer contact point (21.4).
7. The ESD protection package structure of claim 1, wherein: and an LC circuit unit (27) is further attached to the front surface of the second rewiring layer (21), and one end of the LC circuit unit (27) is connected with the second heat dissipation metal column (25).
8. The ESD protection package structure of claim 7, wherein: the LC circuit unit (27) is directly produced by adopting a thin film passive device process.
9. The ESD protection package structure according to claim 1, wherein a first heat dissipation metal pillar (15) is disposed in the first redistribution layer (11), and a lower end of the first heat dissipation metal pillar (15) is connected to the first heat dissipation metal sheet (12).
10. A manufacturing method of an ESD protection packaging structure is characterized by comprising the following steps:
step one, taking a carrier plate, and mounting a second heat dissipation metal sheet on the carrier plate, wherein the second heat dissipation metal sheet is provided with a second opening;
forming an under-ball metal layer at the second opening, wherein the under-ball metal layer is not connected with the second heat dissipation metal sheet;
thirdly, preparing a second rewiring and the lower part of a second heat dissipation metal column on the second heat dissipation metal sheet and the under-ball metal layer, wherein a second insulating material is coated on the periphery of the lower parts of the second rewiring and the second heat dissipation metal column to form a second rewiring layer;
forming an electrical metal column and the upper part of a second heat dissipation metal column on the second rewiring layer, forming a complete second metal column on the upper part of the second heat dissipation metal column and the lower part of the second heat dissipation metal column, and attaching a second chip and an LC circuit unit to corresponding positions on the second rewiring layer;
step five, plastic packaging is carried out on the upper portion of the second rewiring layer by adopting a second plastic packaging material to form a second packaging body, and the upper surfaces of the electrically-conductive metal columns and the second heat-dissipation metal columns are exposed out of the second plastic packaging material after the plastic packaging;
removing the carrier plate, and mounting the prefabricated first packaging body on a second packaging body, wherein the first packaging body is electrically connected with the second packaging body through an electric metal column;
and step seven, carrying out ball planting on the back of the second packaging body.
11. The method of claim 10, wherein the ESD protection package structure further comprises: in the fourth step, one end of the LC circuit unit is connected with the second heat dissipation metal column.
12. The method of claim 10, wherein the ESD protection package structure further comprises: and exposing the upper surface of the second chip out of the second plastic package material after plastic package in the step five.
13. The method of claim 10, wherein the ESD protection package structure further comprises: and step six, arranging a first radiating fin at the bottom of the first packaging body, and connecting the first radiating fin with the upper part of a second radiating metal column in the second plastic packaging body.
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| DE102021130924A1 (en) | 2021-11-25 | 2023-05-25 | Infineon Technologies Ag | Protection against electrostatic discharge of an electronic component embedded in the laminate of a printed circuit board |
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