CN112086399A - Semiconductor structure and preparation method - Google Patents
Semiconductor structure and preparation method Download PDFInfo
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- CN112086399A CN112086399A CN201910511416.2A CN201910511416A CN112086399A CN 112086399 A CN112086399 A CN 112086399A CN 201910511416 A CN201910511416 A CN 201910511416A CN 112086399 A CN112086399 A CN 112086399A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 301
- 229910052751 metal Inorganic materials 0.000 claims abstract description 163
- 239000002184 metal Substances 0.000 claims abstract description 163
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 239000011241 protective layer Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 229910052715 tantalum Inorganic materials 0.000 claims description 12
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- 230000003667 anti-reflective effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a through hole which is opened on the surface of the substrate in the substrate; forming a first metal layer in the through hole, wherein the through hole is filled with the first metal; forming a protective layer on the substrate and the first metal layer, wherein the protective layer covers a contact area of the first metal layer positioned at the top of the through hole and the substrate; forming a second metal layer on the substrate, the protective layer, and the first metal layer. According to the invention, the protective layer covers the top area of the through hole, so that the first metal layer and the second metal layer are further isolated, and the second metal layer is prevented from intruding and diffusing in the first metal layer, thereby improving the reliability of the device and the product yield.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
With the continuous development of integrated circuit processes, copper interconnection processes are becoming the preferred interconnection scheme for advanced integrated circuit processes due to their advantages of low resistivity, low signal delay and strong via filling capability compared to aluminum interconnection processes.
At present, in the existing copper interconnection process, in order to prevent copper in the copper metal layer from diffusing in other structural layers and further affecting the device performance, a diffusion barrier layer is often required to be introduced between the copper metal layer and other structural layers to inhibit copper diffusion. For example, in a Through Silicon Via (TSV) process, when a copper material is used to fill a TSV hole, a barrier layer needs to be disposed between the TSV hole and an adjacent aluminum metal wiring layer to prevent copper diffusion in the aluminum metal layer. However, in practical processes, after high temperature annealing and other processes, the copper at the top boundary of the via hole often damages and penetrates the barrier layer on the macro structure and intrudes into the aluminum metal layer, which seriously affects the device reliability and product yield.
Therefore, it is desirable to provide a new semiconductor structure and a method for fabricating the same, which solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which are used to solve the problem of the intrusion diffusion between different metal layers on the top of the via structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
forming a through hole which is opened on the surface of the substrate in the substrate;
forming a first metal layer in the through hole, wherein the through hole is filled with the first metal;
forming a protective layer on the substrate and the first metal layer, wherein the protective layer covers a contact area of the first metal layer positioned at the top of the through hole and the substrate;
forming a second metal layer on the substrate, the protective layer, and the first metal layer.
As a preferable aspect of the present invention, the first metal layer includes a copper metal layer; the second metal layer includes an aluminum metal layer.
In a preferred embodiment of the present invention, the protective layer includes one or more of a silicon dioxide layer, a silicon oxynitride layer, a tantalum nitride layer, and a tantalum layer.
As a preferable mode of the present invention, the substrate includes a silicon substrate on which a semiconductor device has been formed, and the through-hole includes a through-silicon-via.
As a preferred embodiment of the present invention, a first barrier layer is further formed between the first metal layer and the substrate; and a second barrier layer is also formed among the second metal layer, the substrate, the protective layer and the first metal layer.
As a preferable aspect of the present invention, the process of forming the protective layer includes the steps of:
depositing a layer of protective material over the substrate and the first metal layer;
and carrying out photoetching and etching processes on the protective material layer to form the protective layer covering the contact area between the first metal layer positioned at the top of the through hole and the substrate.
The present invention also provides a semiconductor structure comprising:
a substrate;
a via formed in the substrate and opening at the substrate surface;
the first metal layer is positioned in the through hole and fills the through hole;
the protective layer is positioned on the substrate and the first metal layer and covers a contact area of the first metal layer positioned at the top of the through hole and the substrate;
a second metal layer on the substrate, the protective layer, and the first metal layer.
As a preferable aspect of the present invention, the first metal layer includes a copper metal layer; the second metal layer includes an aluminum metal layer.
In a preferred embodiment of the present invention, the protective layer includes one or more of a silicon dioxide layer, a silicon oxynitride layer, a tantalum nitride layer, and a tantalum layer.
As a preferable mode of the present invention, the substrate includes a silicon substrate on which a semiconductor device has been formed, and the through-hole includes a through-silicon-via.
As a preferred embodiment of the present invention, a first barrier layer is further formed between the first metal layer and the substrate; and a second barrier layer is also formed among the second metal layer, the substrate, the protective layer and the first metal layer.
As described above, the present invention provides a semiconductor structure and a manufacturing method thereof, wherein a protective layer is covered on a top region of the through hole to further isolate the first metal layer from the second metal layer, so as to prevent the second metal layer from intruding and diffusing in the first metal layer, thereby improving reliability and product yield of the device.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a substrate provided in a first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a substrate after forming a via hole thereon according to a first embodiment of the invention.
Fig. 4 is a schematic cross-sectional view illustrating a first metal layer deposited on the surface of the etching mask layer and in the through hole according to the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view illustrating the etching mask layer and a portion of the first metal on the surface of the interlayer dielectric layer are removed by chemical mechanical polishing according to the first embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view illustrating a protective material layer and an anti-reflective layer deposited on the interlayer dielectric layer and the first metal layer according to a first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view illustrating a patterned photoresist layer formed on the anti-reflective layer by a photolithography process according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of the antireflection layer and the protective material layer after dry etching according to the first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a second barrier layer and a second metal layer after being formed according to a first embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a second metal layer after performing a chemical mechanical polishing process according to a first embodiment of the invention.
Description of the element reference numerals
101 substrate
101a silicon substrate
101b shallow trench isolation structure
101c gate oxide layer
101d grid
101e gate sidewall spacer
101f interlayer dielectric layer
101g contact hole plug
Etching mask layer for 101h
102 through hole
103 first metal layer
103a first barrier layer
104 protective layer
104a protective material layer
104b anti-reflection layer
104c photoresist layer
105 second metal layer
105a second barrier layer
S1-S5 Steps 1) -5)
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 10, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:
1) providing a substrate 101;
2) forming a through hole 102 opened on the surface of the substrate in the substrate 101;
3) forming a first metal layer 103 in the via hole 102, wherein the via hole 102 is filled with the first metal layer 103;
4) forming a protective layer 104 on the substrate 101 and the first metal layer 103, wherein the protective layer 104 covers a contact area between the first metal layer 103 and the substrate 101 at the top of the through hole 102;
5) a second metal layer 105 is formed on the substrate 101, the protection layer 104, and the first metal layer 103.
In step 1), referring to step S1 of fig. 1 and fig. 2, a substrate 101 is provided. Alternatively, the substrate 101 includes a silicon substrate 101a on which various semiconductor device structures have been formed. Specifically, a shallow trench isolation structure 101b, a gate oxide layer 101c, a gate 101d, a gate sidewall 101e, an interlayer dielectric layer 101f, a contact hole plug 101g, an etching mask layer 101h and other semiconductor device structures are sequentially formed on the silicon substrate 101 a. Optionally, the material forming the shallow trench isolation structure 101b includes silicon dioxide, the material forming the gate 101d includes polysilicon, the material forming the gate sidewall 101e includes silicon dioxide or silicon nitride, the material forming the interlayer dielectric layer 101f includes silicon dioxide, the material forming the contact hole plug 101g includes tungsten, and the material forming the etching mask layer 101h includes silicon dioxide. The semiconductor device structure formed on the surface of the silicon substrate 101a in this embodiment has been described above, but the present invention is not limited to the specific structure and layout of the semiconductor device structure. For example, the present embodiment shows only a case where a metal wiring layer is formed on an active region, but in other embodiments of the present invention, multiple metal wiring layers may be introduced, and the multiple metal wiring layers are connected by via plugs and separated by multiple interlayer dielectric layers. In other embodiments of the present invention, other possible structures may be formed according to device design requirements, or the silicon substrate 101a may be replaced by another possible substrate such as a silicon germanium substrate or a silicon carbide substrate.
In step 2), referring to step S2 of fig. 1 and fig. 3, a via 102 opened on the surface of the substrate is formed in the substrate 101. In fig. 3, a patterned etching mask layer 101h is formed by performing photolithography and etching processes on the etching mask layer 101h, and the silicon substrate 101a thereunder is subjected to deep silicon etching with the etching mask layer 101h as an etching mask. Specifically, after a patterned photoresist layer is formed on the surface of the etching mask layer 101h, the interlayer dielectric layer 101f and the shallow trench isolation structure 101b are sequentially etched by using the photoresist layer as an etching mask through a dry etching process of a dielectric layer, and the silicon substrate 101a is exposed. Then, with the etching mask layer 101h as an etching mask, deep silicon etching is performed on the silicon substrate 101a, and the through hole 102 is formed. It should be noted that, in the drawings of the present embodiment, in order to clearly show the structures in the substrate 101, there are large differences between the illustrated proportions and the actual sizes. For example, the thickness of the silicon substrate 101a is typically 725 μm in an 8-inch wafer, and the total thickness of the other semiconductor structures on the silicon substrate 101a is typically not more than 10 μm. The through hole 102 penetrates through the etching mask layer 101h, the interlayer dielectric layer 101f and the shallow trench isolation structure 101b, and stops in the silicon substrate 101 a. The Through-hole 102 has a depth in the Silicon substrate 101a in a range of typically several hundred μm, and is formed by a Through-Silicon Via (TSV) process. The etching process of the silicon through hole comprises bosch etching, namely a deep silicon etching process consisting of a plurality of polymer passivation processes and repeated and cyclic etching processes. It should be noted that, in the present embodiment, the through hole 102 is a Through Silicon Via (TSV), but in other embodiments of the present invention, the through hole 102 may also be a via (via) between metal wiring layers or a contact (contact) between an active region and a metal wiring layer, which does not affect the implementation purpose and the implementation effect of the present invention.
In step 3), referring to step S3 of fig. 1 and fig. 4 to 5, a first metal layer 103 is formed in the via hole 102, and the via hole 102 is filled with the first metal 103. Specifically, in fig. 4, a first metal layer 103 is deposited on the surface of the etching mask layer 101h and in the through hole 102. Optionally, the first metal layer 103 includes a copper metal layer, and the method for depositing the first metal layer 103 includes a chemical vapor deposition or electroplating process. A first barrier layer 103a is further formed between the first metal layer 103 and the substrate 101, wherein the first barrier layer 103a includes a tantalum nitride/tantalum composite layer, which can prevent copper in the first metal layer 103 from diffusing into other structures, and the thickness of the first barrier layer is generally equal to that of the copper in the first metal layer 103
And left and right, may be formed by chemical vapor deposition. In fig. 5, the etching mask layer 101h and a portion of the first metal 103 on the surface of the interlayer dielectric layer 101f are removed by chemical mechanical polishing, and only the first metal layer 103 in the through hole 102 is left.
In step 4), please refer to step S4 of fig. 1 and fig. 6 to 8, a protection layer 104 is formed on the substrate 101 and the first metal layer 103, wherein the protection layer 104 covers a contact area between the first metal layer 103 and the substrate 101 at the top of the via 102. Optionally, the protection layer 104 includes one or more of a silicon dioxide layer, a silicon oxynitride layer, a tantalum nitride layer, or a tantalum layer. In this embodiment, the protective layer 104 is a silicon dioxide layer, and the dense silicon dioxide layer has a higher hardness, so that different metal layers can be effectively isolated from each other structurally, and copper metal can be prevented from invading other metal layers. It should be noted that the region covered by the protection layer 104 is the contact region of the first metal layer 103 and the substrate 101 at the top of the through hole 102. This region is a weak area between different structural layers that is prone to structural damage and intrusion of copper metal into other metal layers.
As an example, as shown in fig. 6 to 8, the process of forming the protective layer 104 includes the steps of:
depositing a layer of protective material 104a on the substrate 101 and the first metal layer 103;
and carrying out photoetching and etching processes on the protective material layer 104a to form the protective layer 104 covering the contact area of the first metal layer 103 positioned at the top of the through hole 102 and the substrate 101.
In fig. 6, a protective material layer 104a is deposited on the interlayer dielectric layer 101f and the first metal layer 103. Optionally, an anti-reflective layer 104b (arc) is further formed on the protection material layer 104 a. The material forming the anti-reflection layer 104b includes a silicon oxynitride layer.
In fig. 7, a patterned photoresist layer 104c is formed on the anti-reflection layer 104b through a photolithography process. The patterning of the photoresist layer 104c will be more accurately controllable due to the presence of the underlying antireflective layer 104 b.
In fig. 7 to 8, the patterned photoresist layer 104c is used as an etching mask to dry-etch the anti-reflection layer 104b and the protective material layer 104 a. After the dry etching is finished, the photoresist layer 104c is removed by ashing to remove photoresist, and wet cleaning is performed. In the present embodiment, since the anti-reflection layer 104b is formed of a silicon oxynitride layer, it can be retained as an additional structural layer. In other embodiments of the present invention, the anti-reflective layer 104b, if made of organic material, may be removed along with the photoresist layer 104 c.
In step 5), referring to step S5 of fig. 1 and fig. 9 to 10, a second metal layer 105 is formed on the substrate 101, the protection layer 104 and the first metal layer 103. Optionally, a second barrier layer 105a is further formed between the second metal layer 105 and the substrate 101, the protection layer 104, and the first metal layer 103. The second metal layer 105 includes an aluminum metal layer. The second barrier layer 105a comprises a tantalum nitride/tantalum composite layer. Although the second barrier layer 105a made of tantalum nitride/tantalum can prevent the copper metal from having atomic-level micro diffusion, the tantalum nitride/tantalum layer is soft, and at some structural weak points, under the action of thermal effect or electrical effect, the copper metal may be damaged on the macrostructure and invade into other metal layers, which greatly reduces the reliability and yield of the device. It should be noted that the second barrier layer 105a is introduced to prevent the micro diffusion of copper in the aluminum metal layer in this embodiment, and the protection layer 104 is introduced to prevent the damage of the macro structure. Therefore, in other embodiments of the present invention, if there is no risk of micro diffusion between different metals, the barrier layer may not be formed, but only the protective layer may be formed to protect the macro structure and prevent the intrusion phenomenon between different metals.
As shown in fig. 10, the second metal layer 105 covers the surfaces of the substrate 101, the passivation layer 104 and the first metal layer 103. Since the second metal layer 105 made of aluminum is separated from the first metal layer 103 made of copper by the protective layer 104, the structures of the respective layers are structurally stabilized, and intrusion of copper metal into the aluminum metal layer is prevented.
As shown in fig. 9 to 10, the process of forming the second metal layer 105 includes the steps of:
in fig. 9, the second barrier layer 105a made of a tantalum nitride/tantalum layer is formed on the surfaces of the interlayer dielectric layer 101f, the protective layer 104, and the first metal layer 103 by chemical vapor deposition or the like, and the second metal layer 105 made of aluminum is formed on the surface of the second barrier layer 105a by physical vapor deposition or the like.
In fig. 10, a chemical mechanical polishing process is performed on the second metal layer 105, and the second metal layer 105 with a flat surface is obtained.
As an example, after step 5) is completed, other process steps such as forming other device structures such as a dielectric layer and a metal layer on the second metal layer 105, performing back grinding and thinning on the silicon substrate 101a, and forming a back metal layer may be further included.
Example two
As shown in fig. 10, the present invention also provides a semiconductor structure comprising:
a substrate 101;
a through hole 102, the through hole 102 being formed in the substrate 101 and being opened at the surface of the substrate 101;
a first metal layer 103 located in the via hole 102 and filling the via hole 102;
a protective layer 104, wherein the protective layer 104 is located on the substrate 101 and the first metal layer 103, and covers a contact area between the first metal layer 103 and the substrate 101, which is located on the top of the through hole 102;
a second metal layer 105, the second metal layer 105 being located on the substrate 101, the protection layer 104 and the first metal layer 103.
As an example, in fig. 10, the substrate 101 includes a silicon substrate 101a on which various semiconductor device structures have been formed. Specifically, a shallow trench isolation structure 101b, a gate oxide layer 101c, a gate 101d, a gate sidewall 101e, an interlayer dielectric layer 101f, a contact hole plug 101g, an etching mask layer 101h and other semiconductor device structures are sequentially formed on the silicon substrate 101 a. The Through holes 102 include Through Silicon Vias (TSVs). It should be noted that in other embodiments of the present invention, other possible structures may be formed according to device design requirements, or the silicon substrate 101a may be replaced by another possible substrate such as a silicon germanium substrate or a silicon carbide substrate; the via hole 102 may also be a via hole (via) between metal wiring layers, or a contact hole (contact) between an active region and a metal wiring layer.
As an example, in fig. 10, the first metal layer 103 includes a copper metal layer; the second metal layer 105 includes an aluminum metal layer. A first barrier layer 103a is further formed between the first metal layer 103 and the substrate 101; a second barrier layer 105a is further formed between the second metal layer 105 and the substrate 101, the protection layer 104, and the first metal layer 103. The first barrier layer 103a and the second barrier layer 105a comprise a tantalum nitride/tantalum composite layer that prevents the microscopic diffusion of copper metal at the atomic level into other structural layers.
As an example, in fig. 10, the protective layer 104 includes one or a combination of silicon dioxide layer, silicon oxynitride layer, tantalum nitride layer, or tantalum layer. In this embodiment, the protective layer 104 is a silicon dioxide layer, and the dense silicon dioxide layer has a higher hardness, so that different metal layers can be effectively isolated from each other structurally, and copper metal can be prevented from invading other metal layers.
In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, wherein the method for manufacturing the semiconductor structure includes the following steps: providing a substrate; forming a through hole which is opened on the surface of the substrate in the substrate; forming a first metal layer in the through hole, wherein the through hole is filled with the first metal; forming a protective layer on the substrate and the first metal layer, wherein the protective layer covers a contact area of the first metal layer positioned at the top of the through hole and the substrate; forming a second metal layer on the substrate, the protective layer, and the first metal layer. The semiconductor structure includes: a substrate; a via formed in the substrate and opening at the substrate surface; the first metal layer is positioned in the through hole and fills the through hole; the protective layer is positioned on the substrate and the first metal layer and covers a contact area of the first metal layer positioned at the top of the through hole and the substrate; a second metal layer on the substrate, the protective layer, and the first metal layer. According to the invention, the protective layer covers the top area of the through hole, so that the first metal layer and the second metal layer are further isolated, and the second metal layer is prevented from intruding and diffusing in the first metal layer, thereby improving the reliability of the device and the product yield.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A method for manufacturing a semiconductor structure, comprising the steps of:
providing a substrate;
forming a through hole which is opened on the surface of the substrate in the substrate;
forming a first metal layer in the through hole, wherein the through hole is filled with the first metal;
forming a protective layer on the substrate and the first metal layer, wherein the protective layer covers a contact area of the first metal layer positioned at the top of the through hole and the substrate;
forming a second metal layer on the substrate, the protective layer, and the first metal layer.
2. The method of claim 1, wherein: the first metal layer comprises a copper metal layer; the second metal layer includes an aluminum metal layer.
3. The method of claim 1, wherein: the protective layer comprises one or more of a silicon dioxide layer, a silicon oxynitride layer, a tantalum nitride layer or a tantalum layer.
4. The method of claim 1, wherein: the substrate comprises a silicon substrate on which semiconductor devices have been formed, and the through-holes comprise through-silicon-vias.
5. The method of claim 1, wherein: a first barrier layer is further formed between the first metal layer and the substrate; and a second barrier layer is also formed among the second metal layer, the substrate, the protective layer and the first metal layer.
6. The method of claim 1, wherein: the process of forming the protective layer includes the steps of:
depositing a layer of protective material over the substrate and the first metal layer;
and carrying out photoetching and etching processes on the protective material layer to form the protective layer covering the contact area between the first metal layer positioned at the top of the through hole and the substrate.
7. A semiconductor structure, comprising:
a substrate;
a via formed in the substrate and opening at the substrate surface;
the first metal layer is positioned in the through hole and fills the through hole;
the protective layer is positioned on the substrate and the first metal layer and covers a contact area of the first metal layer positioned at the top of the through hole and the substrate;
a second metal layer on the substrate, the protective layer, and the first metal layer.
8. The semiconductor structure of claim 7, wherein: the first metal layer comprises a copper metal layer; the second metal layer includes an aluminum metal layer.
9. The semiconductor structure of claim 7, wherein: the protective layer comprises one or more of a silicon dioxide layer, a silicon oxynitride layer, a tantalum nitride layer or a tantalum layer.
10. The semiconductor structure of claim 7, wherein: the substrate comprises a silicon substrate on which semiconductor devices have been formed, and the through-holes comprise through-silicon-vias.
11. The semiconductor structure of claim 7, wherein: a first barrier layer is further formed between the first metal layer and the substrate; and a second barrier layer is also formed among the second metal layer, the substrate, the protective layer and the first metal layer.
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