CN112082661B - Infrared detector structure based on pixel combination and combination method thereof - Google Patents

Infrared detector structure based on pixel combination and combination method thereof Download PDF

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CN112082661B
CN112082661B CN202010731223.0A CN202010731223A CN112082661B CN 112082661 B CN112082661 B CN 112082661B CN 202010731223 A CN202010731223 A CN 202010731223A CN 112082661 B CN112082661 B CN 112082661B
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pixel
row
column
switches
combined
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CN112082661A (en
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康晓旭
陈寿面
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Shanghai IC R&D Center Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01JMEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02Constructional details
    • G01J5/08Optical arrangements
    • G01J5/0893Arrangements to attach devices to a pyrometer, i.e. attaching an optical interface; Spatial relative arrangement of optical elements, e.g. folded beam path

Abstract

An infrared detector structure based on pixel combination and a combination method thereof comprise a pixel array and a control unit, wherein the pixel array comprises M x N pixels and blind elements which are in one-to-one correspondence with the pixels, and the control unit comprises a blind element connecting switch, a row selection switch, a column selection switch, a transmission switch, a combination switch, an amplification unit and a capacitor thereof; wherein, M and N are more than or equal to 2, the number of the blind pixel connecting switches, the row selecting switches and the column selecting switches is M × N, the number of the transmission switches is N, and the merging switches are N-1; when at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is closed, and the other transmission switches are opened, so that output data of all pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.

Description

Infrared detector structure based on pixel combination and combination method thereof
Technical Field
The invention relates to the field of design of integrated circuits and logic circuits, in particular to an infrared detector structure based on pixel combination and a combination method thereof.
Background
The infrared detector is a core component of a thermal imaging system, is a key for detecting, identifying and analyzing object infrared information, and has wide application in various industries such as military, industry, traffic, security monitoring, meteorology, medicine and the like. The infrared detector has the advantages of high sensitivity, capability of distinguishing more subtle temperature difference, long detection distance, and main application to high-end military equipment, and has the advantages of small volume, light weight, low power consumption, long service life, low cost, quick start and the like. In recent years, with the continuous progress of the infrared focal plane detector technology and the gradual reduction of the manufacturing cost, the cost performance of the infrared focal plane detector is rapidly improved, and good conditions are created for promoting the large-scale market application of the infrared detector.
The infrared detector is mainly based on a heat sensor prepared by micro-electro-mechanical systems (MEMS), the array scale of the infrared detector is continuously increased, the pixel size is continuously reduced, and a new technical development trend appears in the aspects of a detector unit structure, an optimized design, a reading circuit design, a packaging form and the like.
The infrared detector has the working principle that thermal radiation from a target is focused on a detector plane pixel array through an infrared optical system, the temperature of the infrared absorption layer of each pixel on the pixel array changes after absorbing infrared energy, different pixels receive the thermal radiation with different energy, the thermal radiation is converted into an electric signal through a reading gating circuit in the detector and output, and a visual electronic image reflecting the temperature distribution condition of the target is finally obtained through a signal acquisition and data processing circuit outside the detector.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a working principle of a pixel array of an infrared detector in the prior art. As shown, the infrared detector includes a pixel array N × M and a control unit; specifically, the pixel array comprises N × M pixel elements (Active pixels), M first blind pixels (blank pixels 1), a row selection module, a column selection module, a readout gating module, an amplification output module and the like, wherein M +1 is selected from any integer from 2 to M, M is a positive integer, N +1 is selected from any integer from 2 to N, and N is a positive integer. In the prior art, in the Row selection step, the Row selection module selects the pixels in a certain Row (such as Row: n rows) to be turned on, at this time, the pixels in Row: n +1 and the pixels in other rows are turned off, the readout gating module is turned on, and then, the output signals are amplified and output through the amplification output module through the difference between the pixels and the first blind pixels in each Row of Row: n rows; similarly, in the column selection step, the column selection module selects the pixels (such as column of Colum: n) of a certain column to be conducted, at this time, the column of Colum: n +1 and other columns are disconnected, the read-out gating module is conducted, and then, the output signals are amplified and output through the amplification output module through the difference between the pixels and the first blind pixels in each row of the column of Colum: n.
However, the application of the current infrared detector has the following problems and requirements:
firstly, the size of an array of an infrared detector determines the size of a pixel of image output, the pixel surface is smaller and smaller as the array is larger, and although the size of the dot matrix output of the image pixel is greatly increased, the response rate/sensitivity of a single pixel is reduced;
secondly, aiming at the requirement of multifunctional multiplexing proposed by the market, namely the product is required to output the effects of large array and medium sensitivity/response rate, and simultaneously the output effects of medium array/high sensitivity/response rate are required to be output, so that different output effects can be obtained in the same scene, and the requirements of different applications can be met.
Therefore, how to meet the above market demand has become an important consideration for the design of infrared detector products in the industry.
Disclosure of Invention
The invention aims to provide an infrared detector structure based on pixel combination and a combination method thereof, which can output the effect of large array and medium sensitivity/response rate, and simultaneously can output the effect of medium array/high sensitivity/response rate through pixel combination.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an infrared detector structure based on pixel combination comprises a pixel array and a control unit, wherein the pixel array comprises M x N pixels and blind elements which are in one-to-one correspondence with the pixels, and the control unit comprises a blind element connecting switch, a row selecting switch, a column selecting switch, a transmission switch, a combination switch, an amplifying unit and capacitors thereof; each pixel is connected with the corresponding blind pixel through the blind pixel connecting switch, and the joint of the pixel and the corresponding blind pixel is connected with the input end of the amplifying unit through the transmission switch; the row selection switch is connected between the pixel and a power supply, the column selection switch is connected between the blind pixel and a grounding terminal, one amplifier unit is shared by the same column in the pixel array, and the transmission switches of the amplifying units in adjacent columns are connected through the merging switch; the number of the blind pixel connecting switches, the number of the row selecting switches and the number of the column selecting switches are M x N, the number of the transmission switches is N, and the number of the merging switches is N-1;
when at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a formed region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is closed, and the rest transmission switches are opened, so that output data of all the pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.
Further, M is an integer multiple of X, and N is an integer multiple of Y, preferably, X is equal to Y.
Further, if M is an integer multiple of X, and N is not an integer multiple of Y; the integer of N divided by Y is A, and the remainder is B; when the pixel arrays need to perform X row Y column combination, M rows A Y column parts are combined according to X rows Y columns, and M rows remainder (B is N-A Y) columns are combined according to X rows 1 columns.
Further, if M is not an integer multiple of X, and N is an integer multiple of Y; m takes the integer of X as A and the remainder as B; when the pixel arrays need to perform X row Y column combination, A row X column part is combined according to X row Y column, and the remainder (B is M-A X) row N column is combined according to 1 row Y column.
Furthermore, the pixels and the blind pixels are in one-to-one correspondence, and the blind pixels are arranged below the corresponding pixel structures.
Further, when merging is not required, one of the operation modes is: and switching off all the merging switches, and reading out data row by row through a row selection column reading mode.
Further, when the merging is not needed, the second working mode is: and switching off all the merging switches, only setting one blind pixel switch in the same column to be closed, and switching off the rest blind pixel switches to realize a mode that the same column shares one blind pixel, and reading data row by row through a row selection column reading mode.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a merging method adopting the infrared detector structure based on pixel merging comprises the following steps:
when at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a formed region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is closed, and the rest transmission switches are opened, so that output data of all the pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.
According to the technical scheme, the infrared detector structure provided by the invention realizes the pixel combination function on the detector framework, namely, the effect of large array and medium sensitivity/response rate can be output, and the output effect of medium array/high sensitivity/response rate is output through pixel combination, namely, the sensitivity/response rate of a single pixel is improved through pixel combination.
Drawings
FIG. 1 is a schematic view of an infrared detector in the prior art
FIG. 2 is a schematic diagram of an infrared detector structure based on pixel combination according to a preferred embodiment of the present invention
Detailed Description
The following describes the present invention in further detail with reference to fig. 2.
According to the infrared detector structure, under the condition that the size of a pixel array is not changed, the pixels are combined to enhance an output signal by adding some blind elements, so that the output effect of outputting a medium array/high sensitivity/response rate is achieved, namely the sensitivity/response rate of a single pixel is improved by combining the pixels. In addition, the invention can also obtain the sensitivity/response rate of a single pixel meeting the requirements of customers by selecting different blind pixel numbers.
It should be noted that the pixel merging in the embodiment of the present invention is to perform row merging and column merging on an M × M pixel array, and in the embodiment of the present invention, the M × N pixel array is exemplarily illustrated by adding a blind element, a connection switch, and an output gating switch.
Specifically, the infrared detector structure based on pixel combination comprises a pixel array and a control unit, wherein the pixel array comprises M x N pixels and blind elements which are in one-to-one correspondence with the pixels, and the control unit comprises a blind element connecting switch, a row selecting switch, a column selecting switch, a transmission switch, a combination switch, an amplifying unit and a capacitor of the amplifying unit; each pixel is connected with the corresponding blind pixel through the blind pixel connecting switch, and the joint of the pixel and the corresponding blind pixel is connected with the input end of the amplifying unit through the transmission switch; the row selection switch is connected between the pixel and a power supply, the column selection switch is connected between the blind pixel and a grounding terminal, in the pixel array, the same column shares one amplifier unit, and the transmission switches of the amplifying units in adjacent columns are connected through the merging switch; the number of the blind pixel connecting switches, the number of the row selecting switches and the number of the column selecting switches are M x N, the number of the transmission switches is N, and the number of the merging switches is N-1.
When at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a formed region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is closed, and the rest transmission switches are opened, so that output data of all the pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.
That is, the present invention can meet the requirement of multi-function multiplexing proposed by the market, that is, the product is required to output the effect of large array and medium sensitivity/corresponding rate, and simultaneously the output effect of medium array/high sensitivity/corresponding rate is required to be output, so as to obtain different output effects in the same scene and meet the requirements of different applications. That is, the present invention can satisfy the sensitivity/response ratio by adjusting the size and combination of X and Y.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a structure of an infrared detector based on pixel binning according to a preferred embodiment of the present invention. As shown in the figure, when column pixels are merged, the merging is performed according to a region to be merged composed of X × Y pixels, and at a certain time, one or more X × Y regions to be merged in an M × N pixel array are merged at the same time.
The following is an exemplary description of the case when all M × N pixel arrays need to perform merging at the same time, and other cases are included in the scope of the present invention and will not be described herein again.
Example 1
In the embodiment of the invention, M is an integer multiple of X, and N is an integer multiple of Y, that is, at the same time, the M × N pixel array is completely covered by the region to be merged composed of a plurality of X × Y pixels, so that the synchronous merging of the whole M × N pixel array can be realized, i.e., the effect of medium array/high sensitivity/response rate can be output. Preferably, X is equal to Y, and at this time, the merging of small arrays such as 2 × 2, 3 × 3, and 4 × 4 in the pixel array can be realized.
Hereinafter, the description will be given by merging 2 × 2 small arrays in the pixel array M × N (where M and N are both integers of 2), and other cases are the same as the merging principle, and will not be described again.
As shown in fig. 2, the region to be merged is 4 pixels where the m-th row and the m + 1-th row intersect with the n-th column and the n + 1-th column, the 4 pixels have 4 blind pixels corresponding to the pixels one by one, and further include a blind pixel connection switch, a row selection switch, a column selection switch, a transmission switch, a merging switch, an amplifying unit and a capacitor thereof; each pixel is connected with a corresponding blind pixel through the blind pixel connecting switch, and the joint of the pixel and the corresponding blind pixel is connected with the input end of the amplifying unit through the transmission switch; the row selection switch is connected between the pixel and a power supply, the column selection switch is connected between the blind pixel and a grounding terminal, one amplifier unit is shared by the same column in the pixel array, and the transmission switches of the amplifying units in adjacent columns are connected through the merging switch; the number of the blind pixel connecting switches, the row selecting switches and the column selecting switches is 4, the number of the transmission switches is 2, and the number of the merging switches is 1.
When merging is carried out, 4 row selection switches and 4 column selection switches are simultaneously closed, 4 blind pixel connecting switches of the areas needing to be merged are all closed, the merging switch of the areas needing to be merged is closed, one transmission switch of 2 transmission switches of the areas needing to be merged is turned on, and the other transmission switches are turned off, so that the output data of all the pixels of the areas needing to be merged are output through the amplifiers corresponding to the closed transmission switches.
As shown in fig. 2, finally, the pixel signals of 2 × 2 arrays corresponding to m columns of n rows and n +1 rows and m +1 columns are respectively connected to respective blind pixels, and are transmitted to the amplifier unit through the transmission switch for processing and outputting. The scheme achieves the effect of outputting a large array and medium sensitivity/response rate.
Example 2
In an embodiment of the present invention, if M is an integer multiple of X, and N is not an integer multiple of Y; when the pixel arrays need to perform merging, the portions, which need to be merged, of N divided by the integral multiple of Y are merged according to adjacent X rows and Y columns, and the portions of the rest (N-A X Y) columns are merged according to adjacent X rows and 1 columns.
Assuming that the pixel array is 4 × 5, the pixel array is processed in the same manner as in example 1, and the remaining columns are merged during the merging period at the same time, i.e., merging of the 4 × 1 arrays is performed.
Example 3
If M is not an integer multiple of X and N is an integer multiple of Y; when the pixel arrays need to perform merging, M is divided by integral multiple of X, B merging parts are merged according to adjacent X rows and Y columns, and the rest (M-B X) columns are merged according to 1 row and Y columns.
Assuming that the pixel array is 5 × 4, the pixel array is processed in the same manner as in example 1 in the portion 4 × 4, and the remaining one row is merged with 1 row × Y column, i.e., the merging of 1 × 4 arrays is performed simultaneously during the merging period.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (10)

1. An infrared detector structure based on pixel combination is characterized by comprising a pixel array and a control unit, wherein the pixel array comprises M x N pixels and blind pixels which are in one-to-one correspondence with the pixels, and the control unit comprises a blind pixel connecting switch, a row selecting switch, a column selecting switch, a transmission switch, a combination switch, an amplifying unit and a capacitor of the amplifying unit; each pixel is connected with the corresponding blind pixel through the blind pixel connecting switch, and the joint of the pixel and the corresponding blind pixel is connected with the input end of the amplifying unit through the transmission switch; the row selection switch is connected between the pixel and a power supply, the column selection switch is connected between the blind pixel and a grounding terminal, one amplification unit is shared by the same column in the pixel array, the transmission switches of the amplification units in adjacent columns are connected through the merging switch, and two connecting positions of the merging switch and the transmission switch are both positioned between the transmission switches and the pixel; the number of the blind pixel connecting switches, the number of the row selecting switches and the number of the column selecting switches are M x N, the number of the transmission switches is N, and the number of the merging switches is N-1;
when at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a formed region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is gated to be closed, and the other transmission switches are opened, so that output data of all pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.
2. A pixel merging-based infrared detector structure as claimed in claim 1, wherein M is an integer multiple of X and N is an integer multiple of Y.
3. A pixel merging-based infrared detector structure as claimed in claim 2, wherein X equals Y.
4. A pixel combination-based infrared detector structure according to claim 1, wherein if M is an integer multiple of X and N is not an integer multiple of Y, the integer of N divided by Y is a and the remainder is B; when the pixel arrays need to perform X row Y column combination, M rows A Y column parts are combined according to X rows Y columns, and M rows remainder (B is N-A Y) columns are combined according to X rows 1 columns.
5. A pixel merging based infrared detector structure as claimed in claim 1, wherein if M is not an integer multiple of X and N is an integer multiple of Y; the integer of M divided by X is A, and the remainder is B; when the pixel arrays need to perform X row Y column combination, A row X column part is combined according to X row Y column, and the remainder (B is M-A X) row N column is combined according to 1 row Y column.
6. A pixel combination-based infrared detector structure according to claim 1, wherein the pixels and the blind pixels are in one-to-one correspondence, and the blind pixels are disposed under the corresponding pixel structure.
7. A pixel merging based infrared detector architecture as claimed in claim 1, wherein when merging is not required, one of its operating modes is: and switching off all the merging switches, and reading out data row by row through a row selection column reading mode.
8. A pixel combination based infrared detector structure according to claim 1, characterized in that when no combination is required, the second mode of operation is: and switching off all the merging switches, only setting one blind pixel switch in the same column to be closed, switching off the rest blind pixel switches, realizing a mode of sharing one blind pixel in the same column, and reading out data row by row through a row selection column reading mode.
9. A merging method using the pixel merging based infrared detector structure of claim 1, comprising the steps of:
when at least one adjacent X row, Y column and the like are needed to be combined, a row selection switch and a column selection switch of a formed region needing to be combined are simultaneously closed, blind element connecting switches of the region needing to be combined are all closed, combining switches of the region needing to be combined are all closed, a transmission switch of the region needing to be combined is gated to be closed, and the other transmission switches are opened, so that output data of all pixels of the region needing to be combined are output through amplifiers corresponding to the closed transmission switches; wherein X is less than or equal to M, and Y is less than or equal to N.
10. The merging method of claim 9,
if M is an integer multiple of X, and N is not an integer multiple of Y; the integer of N divided by Y is A, and the remainder is B; when the pixel arrays need to perform X row by Y column combination, M row A by Y column parts are combined according to X row by Y column, and M row remainder (B is N-A by Y) columns are combined according to X row 1 column;
if M is not an integer multiple of X and N is an integer multiple of Y; m takes the integer of X as A, and the remainder as B; when the pixel arrays need to perform X row Y column combination, A row X column part is combined according to X row Y column, and the remainder (B is M-A X) row N column is combined according to 1 row Y column.
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