CN112073354A

CN112073354A - High-speed mobile wireless communication system based on FPGA

Info

Publication number: CN112073354A
Application number: CN202010940778.6A
Authority: CN
Inventors: 张瑞; 史故臣; 蒋维; 陈秋霞
Original assignee: Zhejiang Shuren University
Current assignee: Zhejiang Shuren University
Priority date: 2020-09-09
Filing date: 2020-09-09
Publication date: 2020-12-11
Anticipated expiration: 2040-09-09
Also published as: CN112073354B

Abstract

The invention discloses a high-speed mobile wireless communication system based on FPGA, which is characterized in that base stations are arranged along an optical fiber at intervals of a preset distance, 2.5G synchronous ring networks are formed among the base stations and are connected with a monitoring center, and a mobile terminal and the base stations carry out broadband communication; timing and carrier synchronization are realized between the mobile terminal and the base station, the uplink rate and the downlink rate adopt an asymmetric mode capable of configuring the ratio of the uplink rate to the downlink rate, and the communication rate is automatically configured according to the number of the mobile terminals simultaneously accessed to the base station; the base station coordinates with the adjacent base station to determine the communication mode of a downlink channel and an uplink channel, and the smooth switching of the mobile terminal between different base stations is realized; both the base station and the mobile terminal include a modem. By the technical scheme of the invention, the asymmetric rate of the upper channel and the lower channel is realized, and the base station can automatically adjust the communication rate of each terminal according to the number of the terminals which can be accessed, thereby solving the problem of seamless switching of the mobile terminal in the process of high-speed mobile communication.

Description

High-speed mobile wireless communication system based on FPGA

Technical Field

The invention relates to the technical field of communication systems, in particular to a high-speed mobile wireless communication system based on an FPGA (field programmable gate array).

Background

In recent years, with rapid development of science and technology and economy, traffic construction in China develops rapidly, so that more and more people select high-speed rails or automobiles as a travel mode, and the frequency of mobile terminals in a scene of high-speed movement is increased day by day. Because the mobile terminal will cause doppler shift in the state of high-speed movement, the difficulty of synchronous reception of the ofdm (orthogonal Frequency Division multiplexing) system is increased, and the quality of the communication link cannot be ensured.

At present, some scholars focus on using redundant information of cyclic prefix to realize synchronization, consider defects of cyclic prefix, and use sampling in an intersymbol interference-free interval to provide a new timing measurement function and a new detection function. In order to improve the anti-interference capability under low signal-to-noise ratio, a time offset blind estimation algorithm based on distance measurement is provided by combining a truncated CP (content provider) technology. However, the algorithm is complex and is not suitable for mobile terminals with real-time requirements. Therefore, some scholars have proposed a preamble symbol composed of ZC (Zadoff-Chu) sequence to implement synchronization of OFDM system by combining pilot or preamble symbol. The training sequence with the conjugate repetition relation structure is constructed to ensure that the synchronization result is not influenced by frequency. In order to avoid the problems of timing ambiguity and the like, a weighting (Constant Amplitude Zero Auto-Correlation, CAZAC) training sequence is provided, and a synchronization algorithm for joint estimation of symbol timing and carrier frequency offset is provided on the basis. Through fewer auxiliary sequences, an Auto Correlation Estimation (ACE) time-frequency synchronization algorithm is provided, and frequency offset Estimation is completed by combining an autocorrelation function and a weighted average idea. In order to determine the symbol synchronization point, a Schmidl & Cox algorithm is adopted to determine a symbol synchronization range, and then a Park algorithm is combined to determine the symbol synchronization point. Although synchronization algorithms incorporating pilot or preamble symbols enable synchronization of OFDM systems, they are algorithmically verified by simulation systems primarily and not actually tested in conjunction with specific hardware devices.

Disclosure of Invention

In order to solve the problems, the invention provides a high-speed mobile wireless communication system based on an FPGA (field programmable gate array), which designs a downlink channel, an uplink channel and a modem system aiming at the communication process between a mobile terminal and a base station on the basis of PN (pseudo-noise) synchronization by utilizing FPGA and OFDM (orthogonal frequency division multiplexing) technologies, realizes the asymmetric rate of the uplink channel and the downlink channel, can automatically adjust the communication rate of each terminal according to the number of terminals which can be accessed, has more advantages than a low-gain omnidirectional antenna under the two conditions of moving towards the base station and moving away from the base station, and can more accurately reflect the fading depth than a bandwidth signal by using a single-tone signal.

In order to achieve the above object, the present invention provides a high-speed mobile wireless communication system based on FPGA, comprising: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network; arranging base stations at intervals of a preset distance along an optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with the monitoring center, and carrying out broadband communication between the mobile terminal and the base stations; timing synchronization and carrier synchronization are realized between the mobile terminal and the base station, the uplink rate and the downlink rate between the mobile terminal and the base station adopt an asymmetric mode with configurable uplink-downlink rate ratio, and the communication rate of each mobile terminal is automatically configured according to the number of the mobile terminals simultaneously accessed to the base station; the base station and the adjacent base station coordinate to determine the communication mode of a downlink channel and an uplink channel between the base station and the mobile terminal, so that the mobile terminal can be smoothly switched among different base stations; the base station and the mobile terminal both comprise a modem, the modem of the base station is connected with external equipment through an IP exchanger, and the modem of the mobile terminal is connected with the external equipment through a WiFi module.

In the above technical solution, preferably, base stations with odd numbers are defined as odd base stations and base stations with even numbers are defined as even base stations according to the order from near to far between the base stations and the monitoring center; the data format of the downlink channel comprises a synchronization head, a control 0 bit, a control 1 bit, a type 1 channel and a type 2 channel, the synchronization head is used for realizing the timing synchronization and the carrier synchronization between the mobile terminal and the base station, the even base station utilizes the control 0 bit time slot to send control information and controls the 1 bit time slot to be idle, and the odd base station utilizes the control 1 bit time slot to send control information and controls the 0 bit time slot to be idle; all time slots of the 1-type channels can be utilized by the base station, the even base station can only use the even-sequence time slots and the odd-sequence time slots of the 2-type channels to be vacant, and the odd base station can only use the odd-sequence time slots and the even-sequence time slots of the 2-type channels to be vacant.

In the above technical solution, preferably, the monitoring center sends a reset command to all base stations, the monitoring center and the base stations start counting with a standard clock, the monitoring center sends a message to a base station when counting to a preset time, the base station records the count of the self counter at this time as an uplink count when receiving the message, the base station sends a message to the monitoring center when counting to the preset time, the monitoring center records the count of the self counter at this time as a downlink count when receiving the message, and sends the downlink count to a corresponding base station, the base station adjusts the base number of the self counter according to a difference between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, thereby achieving time calibration of the current base station.

In the above technical solution, preferably, the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through a synchronization header of the downlink channel, and after synchronization is completed, the mobile terminal controls an instruction of an uplink channel through a clock counter synchronized with the base station to perform a corresponding action at a corresponding time; according to the difference of the distance between the mobile terminal and the base station, when the mobile terminal is in a type 1 area, the mobile terminal sends data to the base station through a type 1 channel which does not need to avoid a mobile terminal time slot connected with an adjacent base station in an uplink channel, and when the mobile terminal is in a type 2 area, the mobile terminal sends data to the base station through a type 2 channel which needs to avoid the mobile terminal time slot connected with the adjacent base station in the uplink channel; the uplink channel starts with a network access application channel, and the time slot occupied by the network access application channel can be removed from the uplink channel when one base station and the adjacent base station do not accept the network access application of a new mobile terminal any more.

In the above technical solution, preferably, the modem includes an ARM CPU, an address attribute controller, a transmission timeslot controller, a reception timeslot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module; the ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller governs the ownership of the memory, the ARM CPU stores the received data in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, and the digital modulator performs OFDM modulation on the received data and sends the modulated data to the radio frequency module; the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out through the digital demodulator, the demodulated data are stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger.

In the above technical solution, preferably, the digital modulator includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, an FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;

when the transmitting time slot controller executes a TxPN instruction, the PN Generator module generates synchronous header information, otherwise, the PN Generator module is in an idle state, the Mapper module loads Tx _ Data onto a modulation signal according to the requirement of Tx _ Mod, the Carrier Control module determines whether to insert a PILOT subcarrier according to whether the value of SUB _ CAR in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differenceial Encoder module is a Differential Encoder of a Differential OFDM system, the iFFT module is used for inverse fast Fourier transform and is responsible for converting a frequency domain signal to a time domain to form an OFDM symbol, the CP module is responsible for adding a cyclic prefix of the OFDM symbol, when the instruction is the TxPN instruction, the MUX module selects the Data of the synchronous header circuit to be transmitted to a rear module, when the instruction is an OFDM or PILOT instruction, the FIR HB Filter module is used for increasing the Data sampling rate from 76MHz to 152MHz, the Farrow Filter module is used for interpolating and up-sampling a 152MHz clock sampling signal to 156.25MHz sampling rate, the DUC module is used for up-converting a baseband signal to an intermediate frequency signal, and finally the Gain module adjusts the Gain of a transmitting signal.

In the above technical solution, preferably, the digital demodulator includes an AGC module, a DCC module, a Farrow Filter module, an FIR HB Filter module, a DeMUX1 module, a PN corrector module, a PLL module, a corrector module, an FFT module, a DeMUX2 module, a Differential Decoder module, a Channel & Carrier Estimation module, an Equalizer module, a PHASOR module, a DeMapper module, a Post Proc module, and a Pilot Drop module;

the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a received signal to a preset amplitude, the DCC module is used for shifting the received signal from an intermediate frequency to a base frequency, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and down-sampling a clock sampling signal of 156.25MHz to a sampling rate of 152MHz and reducing a data sampling rate from 152MHz to 76MHz, the DeMUX1 module selects different processing circuits according to an accepted instruction, if the instruction is RxPN Start and RxPN Stop, the received data are transmitted to a PN processing circuit, when the instruction is OFDM or PILOT, the OFDM processing circuit is selected, and in the PN processing circuit, the PN corelate module is mainly responsible for synchronous head searching, and when the receiving time slot controller executes the RxPN Start or RxPN Stop instruction, the module starts or ends synchronous head searching; the PLL module provides a working clock close to the system, the PN Correlator module synchronizes the working clock with the working clock of the base station in the later period, and the Correlator module in the OFDM circuit carries out correlation operation aiming at the first pilot frequency symbol of the differential OFDM, thereby eliminating the ambiguity in the OFDM signal; the FFT module converts the OFDM signal in the time domain into the frequency domain, the DeMUX2 module and the Differential Decoder module respectively complete the difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes the PILOT, the Channel & Carrier Estimation module is selected to complete the Channel and Carrier frequency Estimation, but when the module executes the OFDM instruction, the Equalizer module is selected to complete the Channel equalization; considering that a certain carrier frequency deviation exists in a signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to a constellation point of a modulation signal and extract frequency offset information according to the phase difference of the data before and after judgment, and finally the Pilot Drop module determines the insertion position of a Pilot subcarrier according to whether the SUB _ CAR value in a received instruction is the same as the setting of an effective subcarrier number register.

In the above technical solution, preferably, the specific process of performing clock synchronization and carrier frequency synchronization by the synchronization head includes a search process and a tracking process; in the searching process, before the position of the synchronization head is locked, the period of a frame length counter is set in a software setting mode, when the amplitude of a related peak is larger than a preset threshold, the position of the maximum related peak and the amplitude of the corresponding related peak are recorded, an interrupt request is sent to an ARM CPU, and after the ARM CPU receives the interrupt request, a zero clearing point of the frame length counter is set to be the sum position of the time intervals of the maximum related peak and the end point of the synchronization head and the end point of the frame; when the frame length counter reaches a clear point, an interrupt request is sent to the ARM CPU, and the ARM CPU sets the period of the frame length counter after receiving the interrupt request, so that the clear point of the frame length counter is positioned at the position of a frame end point;

the tracking process comprises timing tracking and carrier frequency tracking, wherein in the timing tracking process, a main correlation peak and correlation peaks at two sides are obtained through a PN correlator, the timing error of a system clock is obtained through calculation, and the timing error is corrected through NCO adjustment; in the carrier frequency tracking process, carrier frequency offset information is detected through a PN correlator, the offset is calculated according to the carrier frequency offset information, and the correction quantity is set back to a hardware circuit so as to correct carrier frequency deviation.

Compared with the prior art, the invention has the beneficial effects that: by utilizing FPGA and OFDM technology, on the basis of PN synchronization, aiming at the communication process between a mobile terminal and a base station, a downlink channel, an uplink channel and a modem system are designed, so that the asymmetric rate of the uplink channel and the downlink channel is realized, the base station can automatically adjust the communication rate of each terminal according to the number of terminals which can be accessed, and under the two conditions of moving towards the base station and moving away from the base station, a high-gain omnidirectional antenna has more advantages than a low-gain omnidirectional antenna, a single-tone signal can more accurately reflect fading depth than a bandwidth signal, and the problem of seamless switching of the mobile terminal in the high-speed mobile communication process is solved.

Drawings

Fig. 1 is a schematic overall structure diagram of a high-speed mobile wireless communication system based on an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a data format of a downlink channel according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a data format of an uplink channel according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a frame format of an uplink channel according to an embodiment of the present invention;

FIG. 5 is a system diagram of a modem according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a basic structure of a digital modulator according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a basic structure of a digital demodulator according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a synchronization head according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a correlation peak of the disclosed system according to one embodiment of the present invention;

fig. 10 is a schematic position diagram of test points of an external field base station and a mobile terminal according to an embodiment of the present invention;

fig. 11 is a schematic diagram of RSSI values of a mobile terminal moving towards a base station according to an embodiment of the present invention;

fig. 12 is a schematic diagram of RSSI values of a mobile terminal moving away from a base station according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a base station side RSSI value moving towards a base station according to an embodiment of the present invention;

fig. 14 is a schematic diagram of a base station side RSSI value moving away from a base station according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

The invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, the high-speed mobile wireless communication system based on FPGA according to the present invention includes: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network; arranging a base station at intervals of a preset distance along the optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with a monitoring center, and carrying out broadband communication between the mobile terminal and the base stations; timing synchronization and carrier synchronization are realized between the mobile terminal and the base station, the uplink rate and the downlink rate between the mobile terminal and the base station adopt an asymmetric mode capable of configuring the ratio of the uplink rate to the downlink rate, and the communication rate of each mobile terminal is automatically configured according to the number of the mobile terminals simultaneously accessed to the base station; the base station and the adjacent base station coordinate to determine the communication mode of a downlink channel and an uplink channel between the base station and the mobile terminal, so that the mobile terminal can be smoothly switched among different base stations; the base station and the mobile terminal both comprise a modem, the modem of the base station is connected with the external equipment through an IP exchanger, and the modem of the mobile terminal is connected with the external equipment through a WiFi module.

In the embodiment, taking a highway as a typical case, an FPGA-based high-speed mobile wireless communication system is designed by utilizing FPGA and OFDM technologies. The system specially designs a downlink channel, an uplink channel and a modem system aiming at the communication process between the mobile terminal and the base station on the basis of PN synchronization, realizes the asymmetric rate of the uplink and downlink channels, and the base station can automatically adjust the communication rate of each terminal according to the number of terminals which can be accessed.

Preferably, one wireless access device, i.e. base station, is located every 2 km along the deployment scenario. The base stations form a 2.5G synchronous ring network through optical fibers and are connected with the road section monitoring center, each base station can simultaneously carry out broadband communication with a plurality of mobile terminals, and the mobile terminals can carry out seamless switching among coverage areas of base station equipment in the process of high-speed movement. The communication between the mobile terminal and the base station adopts a 5.8G frequency band. The uplink (from the terminal to the base station) rate and the downlink (from the base station to the terminal) rate adopt an asymmetric mode, the uplink is low, the downlink is high, and the uplink and downlink rate ratio can be configured. The number of terminals that can be simultaneously accessed by each base station is at most N, where N can be configured to be 32, 64, 128, etc., and the communication rate with each terminal can be automatically adjusted according to the number of terminals that can be simultaneously accessed.

In the above embodiment, preferably, the base stations with odd numbers are odd base stations and the base stations with even numbers are even base stations, which are defined according to the order from near to far between the base stations and the monitoring center. As shown in fig. 2, the data format of the downlink channel includes a synchronization header, a control 0 bit, a control 1 bit, a class 1 channel, and a class 2 channel, and first, the synchronization header is used to achieve timing synchronization and carrier synchronization between the mobile terminal and the base station, and the control 0 bit and the control 1 bit not only indicate at what position of the downlink channel the corresponding mobile terminal should extract data, but also indicate at what position of the uplink channel the corresponding mobile terminal should transmit data. Specifically, the even base station uses the control 0 bit time slot to send control information and controls the 1 bit time slot to be idle, and the odd base station uses the control 1 bit time slot to send control information and controls the 0 bit time slot to be idle. If the mobile terminal is connected with the even base station, the control information for controlling the 0-bit time slot is required to be extracted, and meanwhile, the 1-bit time slot is monitored so as to determine whether the mobile terminal enters the range of the next base station. The mobile terminals connected to the odd base stations are connected to the even base stations in the same way as described above. All time slots of the 1-type channels can be utilized by the base station, the even base station can only use the even-order time slots and the odd-order time slots of the 2-type channels to be vacant, and the odd base station can only use the odd-order time slots and the even-order time slots of the 2-type channels to be vacant. Each base station therefore coordinates with the two adjacent base stations on the left and right to determine its allocation of class 1 and class 2 channels.

In the above embodiment, preferably, to achieve smooth handover of the mobile terminal between different base stations, good time synchronization needs to be maintained between the base stations, and the time calibration process is as follows: the monitoring center sends a reset command to all base stations, the monitoring center and the base stations start to count by a standard clock, the monitoring center sends a message to the base stations when counting for 20 milliseconds, the base stations record the count of the self counters at the moment as an uplink count when receiving the message, the base stations send the message to the monitoring center when counting for 20 milliseconds, the monitoring center records the count of the self counters at the moment as a downlink count when receiving the message, the downlink count is sent to the corresponding base stations, the base stations adjust the base numbers of the self counters according to the difference value between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, and time calibration of the current base station is achieved. The base station having completed the time alignment can transmit data through the downlink channel.

In the above embodiment, preferably, before sending data through the uplink channel, the mobile terminal needs to perform clock synchronization and carrier frequency synchronization with the base station through a synchronization header of the downlink channel, and after the synchronization is completed, the mobile terminal controls an instruction of the uplink channel through a clock counter synchronized with a frame period of the base station to perform a corresponding action at a corresponding time; according to the difference of the distance between the mobile terminal and the base station, the time delay of receiving the base station information is different, so the base station needs to reserve an interval of 6.7us when formulating the uplink channel time slots of different mobile terminals. Similar to the type 1 channel and the type 2 channel of the downlink channel, the uplink channel can also be divided into two types: when a mobile terminal is in a class 1 region, it can transmit data to the base station using a class 1 channel, i.e., a timeslot for which it does not need to avoid mobile terminals connected to neighboring base stations. When a mobile terminal is in a class 2 area, it must transmit data to the base station using a class 2 channel, i.e. a timeslot whose timeslot needs to avoid mobile terminals connected to neighboring base stations.

The data format of the uplink channel is shown in fig. 3, because the time for the data sent by each mobile terminal to reach the base station may be different, the uplink channel of each mobile terminal needs to have a synchronization header as a start, and the base station can lock the position of the data segment by the synchronization header. The frame format of the uplink channel is shown in fig. 4, the uplink channel starts with a network access application channel, and when one base station and its neighboring base stations do not accept the network access application of a new mobile terminal any more, the time slot occupied by the network access application channel can be removed from the uplink channel. The information carried by a frame of uplink channel is completely determined by the control information of the downlink channel and includes uplink data of at most 64 ues.

As shown in fig. 5, in the above embodiment, preferably, the modem includes an ARM CPU, an address attribute controller, a transmission slot controller, a reception slot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module; the ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller governs the ownership of the memory, the ARM CPU stores data received through the 2.5G network in a certain position in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, the digital modulator carries out OFDM modulation on the received data, sends the modulated data to the radio frequency module and emits the data through an antenna; the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out through the digital demodulator, the demodulated data are stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger. The action commands followed by the transmission time slot controller and the receiving time slot controller are firstly put into a specific position of the memory by the ARM CPU. The transmit and receive slot controllers then sequentially read the instructions from memory and execute them. The transmitting time slot controller sends data to the digital modulator and then to the antenna through the radio frequency module. And the receiving time slot controller receives the data demodulated by the digital demodulator, and then sends the data to the IP switching module through the ARM CPU.

The difference from the modem of the mobile terminal is that the modem of the base station is connected with an IP switch, and the modem of the mobile terminal is connected with a WIFI device. The standard clock of the base station end is provided by the 2.5G network, and the working clock of the mobile terminal is generated by the modem, adjusted according to the received synchronization head of the downlink channel and finally synchronized to the standard clock of the base station. The IP exchange module (the mobile terminal is a WIFI module) and the modem are connected together through the ARM CPU through the bus.

As shown in fig. 6, in the above-described embodiment, preferably, the digital modulator includes a PN Generator module, a Mapper module, a Carrier Control module, a Differential Encoder module, an iFFT module, a CP module, a MUX module, an FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;

when the transmitting time slot controller executes a TxPN instruction, the PN Generator module generates synchronous head information, otherwise, the PN Generator module is in an idle state, the Mapper module loads Tx _ Data onto a modulation signal according to the requirement of Tx _ Mod, the Carrier Control module determines whether to insert PILOT subcarriers according to the condition that the value of SUB _ CAR in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differencel Encoder module is a Differential Encoder of a Differential OFDM system, the iFFT module is used for fast Fourier inversion and is responsible for converting frequency domain signals to time domain to form OFDM symbols, the CP module is responsible for adding cyclic prefixes of the OFDM symbols, when the instruction is the TxPN instruction, the MUX module selects the Data of the synchronous head circuit to be transmitted to the rear module, when the instruction is the OFDM or PILOT instruction, the FIR Filler module is used for increasing the sampling rate of the Data from 76MHz to 152MHz, the Farrow Filter module is used for interpolating and up-sampling the 152MHz clock sampling signal to 156.25MHz sampling rate, the DUC module is used for up-converting the baseband signal to an intermediate frequency signal, and finally the Gain of the transmitting signal is adjusted by the Gain module.

As shown in fig. 7, in the above embodiment, preferably, the digital demodulator includes an AGC module, a DCC module, a Farrow Filter module, an FIR HB Filter module, a DeMUX1 module, a PN correct module, a PLL module, a corrector module, an FFT module, a DeMUX2 module, a Differential Decoder module, a Channel & Carrier Estimation module, an equalzer module, a phaser module, a DeMapper module, a Post Proc module, and a Pilot Drop module;

the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a received signal to a preset amplitude, the DCC module is used for shifting the received signal from an intermediate frequency to a base frequency, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and down-sampling an 156.25MHz clock sampling signal to a 152MHz sampling rate and reducing a data sampling rate from 152MHz to 76MHz, the DeMUX1 module selects different processing circuits according to an accepted instruction, if the instruction is RxPN Start and RxPN Stop, the received data are transmitted to the PN processing circuit, when the instruction is OFDM or PILOT, the OFDM processing circuit is selected, in the PN processing circuit, the PN corelate module is mainly responsible for synchronous head searching, and when the RxPN Start or RxPN Stop instruction is executed by a receiving time slot controller, the module starts or ends the synchronous head searching; modules such as PLL (phase locked loop) and the like provide a near working clock for a system, a later PN corrector module synchronizes the working clock with a working clock of a base station, and a corrector module in an OFDM (orthogonal frequency division multiplexing) circuit carries out correlation operation aiming at a first pilot frequency symbol of differential OFDM, so that the ambiguity in an OFDM signal is eliminated; the OFDM signal on a time domain is converted into a frequency domain by an FFT module, a DeMUX2 module and a Differential Decoder module respectively finish the difference and decoding of the OFDM signal, a DeMUX3 module is a data separation controller, when the PILOT is executed by the module, a Channel & Carrier Estimation module is selected to finish Channel and Carrier frequency Estimation, but when the OFDM instruction is executed by the module, an Equalizer module is selected to finish Channel equalization; considering that a certain carrier frequency deviation exists in the signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to a constellation point of a modulation signal and extract frequency offset information according to the phase difference of the data before and after judgment, and finally the Pilot Drop module determines the insertion position of a Pilot subcarrier according to whether the SUB _ CAR value in a received instruction is the same as the setting of an effective subcarrier number register.

In the above embodiment, preferably, the specific processes of clock synchronization and carrier frequency synchronization by the synchronization head include a search process and a tracking process.

Fig. 8 is a schematic diagram of a 20ms (1520000 clock widths) long frame structure based on a 76MHz clock. The data frame takes a PN synchronous head as a starting mark. The counter for the frame period 76MHz clock counts from 0 to 1519999.

As shown in fig. 8, the time interval between the end point of the PN sync header and the end point of one frame is d 1519999-. In order to ensure that the hardware will encounter a PN sync header within a period of time, the period of the frame length counter is set to 30ms by software setting before the position of the PN sync header is locked. When the hardware judges that the amplitude of the correlation peak is larger than the preset threshold, the hardware records the position x of the maximum correlation peak and the amplitude of the corresponding correlation peak and sends an interrupt request to the ARM CPU, and the ARM CPU sets a zero clearing point of a frame length counter to be the sum value position of the time interval between the maximum correlation peak and the end point of the synchronization head and the end point of the frame, namely x + d, after receiving the interrupt request. When the frame length counter reaches the clear point, an interrupt request is sent to the ARM CPU, and after receiving the interrupt request, the ARM CPU sets the period of the frame length counter to 20ms, that is, the clear point of the frame length counter is set at the position of the frame end point 1519999, so that the PN synchronization header has the structure shown in fig. 8.

The tracking process comprises timing tracking and carrier frequency tracking, and the purpose of the timing tracking is to synchronize the working clock of the mobile terminal with the working clock of the base station; the purpose of carrier frequency tracking is to synchronize the carrier frequency of the mobile terminal with the operating carrier frequency of the base station.

A schematic diagram of the correlation peak of the system during timing tracking is shown in fig. 9. Two non-zero points are respectively arranged at two sides of the main correlation peak, wherein the main correlation peak is a point P (pure); the correlation peak earlier than point P is point e (early); the correlation peak later than the point P is the point L (late). The correlation peak at point P, E, L is first obtained by the PN correlator and is recorded in the corresponding register. The timing error of the system clock is calculated, and if the correlation peaks of the three points are denoted as Punc _ Corr, Early _ Corr and Late _ Corr, respectively, the timing error Terr of the system clock can be expressed as:

the timing error of the system clock can be converted to Hertz _ hz as follows:

Terr_hz＝Terr×(1/TF)×(RS/FS) (2)

where TF represents the frame period, RS represents the PN sequence symbol rate, and FS represents the system clock frequency. Upon detection of a timing error, the software can correct for system bias by adjusting the NCO.

In the carrier frequency tracking process, firstly, the carrier frequency offset information is detected through a PN correlator, then, software calculates the offset according to the carrier frequency offset information, and the correction amount is set back to a hardware circuit so as to correct the carrier frequency offset. The software calculation process is as follows:

suppose that

And

then

Thus, the phase difference α is

For small angle cases, the phase difference calculation can be approximated as

Assuming Δ f is the carrier frequency offset, Rs is the PN symbol rate, and Δ p is the phase per PN symbol, then

Since Lpn is the total length of the PN sequence and α is

The phase difference of the PN symbol accumulations, and thus the carrier frequency offset can be calculated as follows:

in view of the fact that α needs not to exceed a certain level of accuracy for the estimation of the carrier frequency offset

Thus, it is possible to provide

In order to verify the reliability of the FPGA-based high-speed mobile wireless communication system proposed in the above embodiment, the base station is erected on the top of a building, and the antenna is aligned with the preselected terminal test point at 500m, the position of the terminal test point is shown in fig. 10. And the mobile cabinet terminal equipment, the antenna, the monitoring computer and the battery are placed on the bicycle to form a mobile test platform. Firstly, antenna static alignment debugging is carried out on a preset test point, the direction of the maximum gain of the base station antenna is aligned to the preset terminal test point, then dynamic test is carried out, namely, a tester winds back and forth along the edge of a bicycle ridden on a road, and meanwhile, in the process of winding, the base station and the terminal respectively continuously print RSSI values (the RSSI value is taken at intervals not more than 0.1 ms). In the test environment, the RSSI analysis is performed on the gain antenna and the signal of the terminal.

The antenna is set as a high-gain omnidirectional antenna, meanwhile, fading depth test is carried out under the excitation of bandwidth signals, and analysis is carried out by combining the two conditions of moving towards the base station and moving away from the base station.

As shown in fig. 11 and 12, when analyzing the data at the mobile terminal side, the RSSI value is gradually increasing in the linear trend when moving towards the base station, and gradually decreasing when moving away from the base station, while the back motion is larger than the forward motion in terms of the standard deviation and the maximum swing, and the back motion is smaller than the forward motion in terms of the average.

As shown in fig. 13 and 14, the data trend of the data on the base station side is analyzed to be basically consistent with that of the data on the mobile terminal side in fig. 11 and 12, but the RSSI data in the operation turning process exists in fig. 14, so that the data has a relatively large average value recess.

In order to analyze the influence caused by the gain antenna of the terminal, the high-gain omnidirectional antenna and the low-gain omnidirectional antenna are selected for comparison under the condition of ensuring the excitation of the bandwidth signal, and the result is shown in the following table 1. In the aspect of average value, the signal intensity is larger in the direction of moving back to the base station than in the direction of moving towards the base station, and the difference is obvious, and the main reason is caused by the difference of included angles between the maximum gain direction of the antenna and the incoming wave direction. In terms of standard deviation and swing amplitude, the value of the backward movement direction is larger than that of the movement direction towards the base station, and the main reason is that when the omnidirectional antenna moves towards the base station, the included angle between the maximum gain direction of the omnidirectional antenna and the line-of-sight incoming wave direction is small, the gain obtained by the line-of-sight incoming wave signals is high, and multipath scattered waves in other directions are inhibited. The energy of the line-of-sight wave is much stronger than that of the multipath scattered wave, so that the strong fluctuation of the signal caused by fast fading is smaller. When the omnidirectional antenna moves back to the base station, the included angle between the maximum gain direction of the omnidirectional antenna and the incoming wave direction is larger, the included angle deviates from the maximum gain direction, the gain is reduced, and the total signal intensity of the heat dissipation path is increased due to the fact that part of the heat dissipation path is in the maximum gain direction. Compared with the movement towards the base station, the main signal intensity of the line-of-sight incoming wave is reduced, the signal of the heat dissipation path is enhanced, the strong difference between the main signal and the signal of the scattering path is reduced, and the fluctuation of the signal intensity of the fast fading is increased. In contrast, in the case of the two types of antennas, when moving toward the base station, the standard deviation of the high-gain antenna used in the base station side is slightly larger than that of the low-gain antenna, but the standard deviation of the low-gain antenna used in the terminal side is significantly larger than that of the high-gain antenna. In the case of movement away from the base station, the standard deviation of the two types of antennas on the base station side is not much different, but the standard deviation of the low-gain antenna on the terminal side is significantly larger than that of the high-gain antenna. Therefore, in summary, the high gain antenna is slightly superior to the low gain antenna, and the main reason is that the swing of the antenna during the movement causes the angle change to be severe, and the gain change caused by the angle change is added, thereby causing the received energy change.

TABLE 1 comparison of dynamic RSSI for different gain antennas

In order to analyze the influence of the signal selection of the terminal, a bandwidth signal is selected to be compared with a bass signal under the condition of ensuring a low-gain antenna, and the result is shown in the following table 2. In terms of standard deviation and swing, the value of the backward movement direction is larger than that of the movement direction towards the base station, for the specific reason, see the above analysis of the gain antenna for the mobile terminal. The maximum swing and standard deviation of the single-tone signal are both larger than the maximum swing and standard deviation of the bandwidth signal, so that the actual fading depth can be measured by the single-tone signal. The main reason for this is that for a bandwidth signal, different frequency fading is different at a certain time. While RSSI is the energy in the statistical band (the density product of all frequency components in the band) and thus masks the actual frequency selective fading depth. However, compared with wide tone signals, single tone signals are more concentrated in energy, and therefore once the frequency point deep fading occurs, the RSSI can be accurately reflected.

TABLE 2 comparison of single-tone bandwidth signal RSSI

According to the high-speed mobile wireless communication system based on the FPGA provided in the above embodiment, it can be known from the above test that not only can simultaneous access of a plurality of terminals be realized, but also the communication rate of the terminal can be automatically adjusted according to the number of the accessed terminals. In the system test stage, the maximum swing amplitude, the standard deviation and the average value of the two conditions of the movement of the terminal towards the base station and the movement of the terminal away from the base station are analyzed, and the RSSI is compared, so that the problem of seamless switching of the mobile terminal in the high-speed mobile communication process is solved.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed mobile wireless communication system based on an FPGA, comprising: the system comprises a base station, a mobile terminal, a monitoring center and an optical fiber ring network;

arranging base stations at intervals of a preset distance along an optical fiber, forming a 2.5G synchronous ring network between the base stations through the optical fiber, connecting the base stations with the monitoring center, and carrying out broadband communication between the mobile terminal and the base stations;

timing synchronization and carrier synchronization are realized between the mobile terminal and the base station, the uplink rate and the downlink rate between the mobile terminal and the base station adopt an asymmetric mode with configurable uplink-downlink rate ratio, and the communication rate of each mobile terminal is automatically configured according to the number of the mobile terminals simultaneously accessed to the base station;

the base station and the adjacent base station coordinate to determine the communication mode of a downlink channel and an uplink channel between the base station and the mobile terminal, so that the mobile terminal can be smoothly switched among different base stations;

the base station and the mobile terminal both comprise a modem, the modem of the base station is connected with external equipment through an IP exchanger, and the modem of the mobile terminal is connected with the external equipment through a WiFi module.

2. The FPGA-based high-speed mobile wireless communication system of claim 1, wherein base stations with odd numbers are defined as odd base stations and base stations with even numbers are defined as even base stations according to the sequence from near to far between the base stations and the monitoring center;

the data format of the downlink channel comprises a synchronization head, a control 0 bit, a control 1 bit, a type 1 channel and a type 2 channel, the synchronization head is used for realizing the timing synchronization and the carrier synchronization between the mobile terminal and the base station, the even base station utilizes the control 0 bit time slot to send control information and controls the 1 bit time slot to be idle, and the odd base station utilizes the control 1 bit time slot to send control information and controls the 0 bit time slot to be idle;

all time slots of the 1-type channels can be utilized by the base station, the even base station can only use the even-sequence time slots and the odd-sequence time slots of the 2-type channels to be vacant, and the odd base station can only use the odd-sequence time slots and the even-sequence time slots of the 2-type channels to be vacant.

3. The FPGA-based high-speed mobile wireless communication system according to claim 1 or 2, wherein the monitoring center issues a reset command to all base stations, the monitoring center and the base stations start counting with a standard clock, the monitoring center sends a message to a base station when counting to a preset time, the base station records the count of the own counter at the time as an uplink count when receiving the message, the base station sends the message to the monitoring center when counting to the preset time, the monitoring center records the count of the own counter at the time as a downlink count when receiving the message, and sends the downlink count to the corresponding base station, the base station adjusts the base number of the own counter according to the difference between the uplink count and the downlink count until the downlink count and the uplink count reach the same value, and realizing the time calibration of the current base station.

4. The FPGA-based high-speed mobile wireless communication system of claim 3, wherein the mobile terminal performs clock synchronization and carrier frequency synchronization with the base station through a synchronization header of the downlink channel, and after the synchronization is completed, the mobile terminal controls an instruction of an uplink channel through a clock counter synchronized with the base station to perform a corresponding action at a corresponding time;

according to the difference of the distance between the mobile terminal and the base station, when the mobile terminal is in a type 1 area, the mobile terminal sends data to the base station through a type 1 channel which does not need to avoid a mobile terminal time slot connected with an adjacent base station in an uplink channel, and when the mobile terminal is in a type 2 area, the mobile terminal sends data to the base station through a type 2 channel which needs to avoid the mobile terminal time slot connected with the adjacent base station in the uplink channel;

the uplink channel starts with a network access application channel, and the time slot occupied by the network access application channel can be removed from the uplink channel when one base station and the adjacent base station do not accept the network access application of a new mobile terminal any more.

5. The FPGA-based high speed mobile wireless communication system of claim 1 wherein the modem comprises an ARM CPU, an address attribute controller, a transmit slot controller, a receive slot controller, a control register, a memory, a digital modulator, a digital demodulator, and a radio frequency module;

the ARM CPU, the transmitting time slot controller, the receiving time slot controller and the control register are connected with the memory through a data bus, the address attribute controller governs the ownership of the memory, the ARM CPU stores the received data in the memory, the transmitting time slot controller reads the data from the memory at a specific moment and sends the data to the digital modulator, and the digital modulator performs OFDM modulation on the received data and sends the modulated data to the radio frequency module;

the receiving time slot controller sends the data received by the radio frequency module to the digital demodulator, OFDM demodulation is carried out through the digital demodulator, the demodulated data are stored in the memory, and the ARM CPU reads the data from the memory and sends the data to the IP exchanger.

6. The FPGA-based high-speed mobile wireless communication system of claim 5, wherein the digital modulator comprises a PN Generator module, a Mapper module, a Carrier Control module, a Differenceial Encoder module, an iFFT module, a CP module, a MUX module, a FIR HB Filter module, a Farrow Filter module, a DUC module, and a Gain module;

when the transmitting time slot controller executes a TxPN instruction, the PN Generator module generates synchronous header information, otherwise, the PN Generator module is in an idle state, the Mapper module loads Tx _ Data Data to a modulation signal according to the requirement of Tx _ Mod, the Carrier Control module determines whether to insert a pilot subcarrier according to the condition that the SUB _ CAR value in the transmitting instruction is the same as the setting of an effective subcarrier number register, the Differenceial Encoder module is a Differential Encoder of a Differential OFDM system, and the iFFT module is used for inverse fast Fourier transform and is responsible for converting a frequency domain signal to a time domain to form an OFDM symbol;

the CP module is responsible for adding a cyclic prefix of an OFDM symbol, when the instruction is a TxPN instruction, the MUX module selects the data of the synchronous head circuit to be transmitted to the rear module, and when the instruction is an OFDM or PILOT instruction, the data of the OFDM circuit is selected;

the FIR HB Filter module is used for increasing the data sampling rate from 76MHz to 152MHz, the Farrow Filter module is used for interpolating and up-sampling a 152MHz clock sampling signal to 156.25MHz sampling rate, the DUC module is used for up-converting a baseband signal to an intermediate frequency signal, and finally the Gain module adjusts the Gain of a transmitting signal.

7. The FPGA-based high-speed mobile wireless communication system of claim 5, wherein the digital demodulator comprises an AGC module, a DCC module, a Farrow Filter module, a FIR HB Filter module, a DeMUX1 module, a PN Correlator module, a PLL module, a Correlator module, an FFT module, a DeMUX2 module, a Differencential Decoder module, a Channel & Carrier Estimation module, an Equalizer module, a PHASOR module, a DeMapper module, a Post Proc module, and a Pilot Drop module;

the AGC module is a pulse width modulation generating circuit and is used for providing gain automatic control for a radio frequency receiving amplifier and adjusting a received signal to a preset amplitude, the DCC module is used for shifting the received signal from an intermediate frequency to a base frequency, the Farrow Filter module and the FIR HB Filter module are respectively used for interpolating and down-sampling a clock sampling signal of 156.25MHz to a sampling rate of 152MHz and reducing a data sampling rate from 152MHz to 76MHz, the DeMUX1 module selects different processing circuits according to an accepted instruction, if the instruction is RxPN Start and RxPN Stop, the received data are transmitted to a PN processing circuit, when the instruction is OFDM or PILOT, the OFDM processing circuit is selected, and in the PN processing circuit, the PN corelate module is mainly responsible for synchronous head searching, and when the receiving time slot controller executes the RxPN Start or RxPN Stop instruction, the module starts or ends synchronous head searching;

the PLL module provides a working clock close to the system, the PN Correlator module synchronizes the working clock with the working clock of the base station in the later period, and the Correlator module in the OFDM circuit carries out correlation operation aiming at the first pilot frequency symbol of the differential OFDM, thereby eliminating the ambiguity in the OFDM signal;

the FFT module converts the OFDM signal in the time domain into the frequency domain, the DeMUX2 module and the Differential Decoder module respectively complete the difference and decoding of the OFDM signal, the DeMUX3 module is a data separation controller, when the module executes the PILOT, the Channel & Carrier Estimation module is selected to complete the Channel and Carrier frequency Estimation, but when the module executes the OFDM instruction, the Equalizer module is selected to complete the Channel equalization;

considering that a certain carrier frequency deviation exists in a signal, the PHASOR module, the DeMapper module and the Post Proc module respectively complete phase rotation, judge received data to a constellation point of a modulation signal and extract frequency offset information according to the phase difference of the data before and after judgment, and finally the Pilot Drop module determines the insertion position of a Pilot subcarrier according to whether the SUB _ CAR value in a received instruction is the same as the setting of an effective subcarrier number register.

8. The FPGA-based high-speed mobile wireless communication system as claimed in claim 2 or 4, wherein the specific processes of clock synchronization and carrier frequency synchronization by the synchronization head include a search process and a tracking process;

in the searching process, before the position of the synchronization head is locked, the period of a frame length counter is set in a software setting mode, when the amplitude of a related peak is larger than a preset threshold, the position of the maximum related peak and the amplitude of the corresponding related peak are recorded, an interrupt request is sent to an ARM CPU, and after the ARM CPU receives the interrupt request, a zero clearing point of the frame length counter is set to be the sum position of the time intervals of the maximum related peak and the end point of the synchronization head and the end point of the frame;

when the frame length counter reaches a clear point, an interrupt request is sent to the ARM CPU, and the ARM CPU sets the period of the frame length counter after receiving the interrupt request, so that the clear point of the frame length counter is positioned at the position of a frame end point;

the tracking process comprises timing tracking and carrier frequency tracking, wherein in the timing tracking process, a main correlation peak and correlation peaks at two sides are obtained through a PN correlator, the timing error of a system clock is obtained through calculation, and the timing error is corrected through NCO adjustment;

in the carrier frequency tracking process, carrier frequency offset information is detected through a PN correlator, the offset is calculated according to the carrier frequency offset information, and the correction quantity is set back to a hardware circuit so as to correct carrier frequency deviation.