CN112073342A - Deadlock avoidance method for equalizer self-adaptive state machine - Google Patents

Abstract

The invention discloses a deadlock avoidance method for an equalizer self-adaptive state machine, which relates to the integrated circuit technology and comprises the following steps: 1) reading the current link state; 2) waiting for a predetermined time; 3) inquiring and judging: a. whether an out-of-position warning exists or not is judged, if yes, A is equal to 1, and if not, A is equal to 0; b. whether LOS warning exists or not, if yes, B is equal to 1, and otherwise, B is equal to 0; c. if a service alarm exists, if so, C is 1, otherwise, C is 0; and entering the subsequent steps according to the situation; 4) judging whether the last link state is link down; 5) restarting the state machine, setting the link state as link up, and then ending; 6) judging whether the last link state is link up; 7) and stopping the state machine, setting the link state to link down, and then ending. The invention can avoid the situation that the self-adaptive state machine of the equalizer enters a deadlock state due to the abnormal received signal and other reasons in time.

Description

Deadlock avoidance method for equalizer self-adaptive state machine

Technical Field

The present invention relates to integrated circuit technology.

Background

An Equalizer (EQ) is a circuit that can adjust the amount of signal amplification of different frequency components, and compensates the attenuation of a channel for different frequencies, such as high frequency, intermediate frequency, and low frequency, by compensating the signals of different frequencies in different magnitudes.

A Continuous Time Linear Equalizer (CTLE) and a Decision Feedback Equalizer (DFE) are two circuit implementations of an Equalizer at a receiving end.

The adjustment of the equalizer parameters usually adopts two ways of fixed configuration values and adaptive configuration.

When adaptive configuration is used, the adaptive state machine may be a logic state machine that is fixed as digital circuitry or a logic state machine that is modifiable by software controlled operation.

The adaptive state machine reads the signal quality information by adjusting the register configuration of the equalizer and judges the process operation of the next adjusting direction.

When signal loss, short circuits to dc levels, and other abnormal conditions occur, the adaptive algorithm cannot achieve the desired signal quality whether it adjusts the equalizer parameters up or down, may adjust the equalizer parameters to extreme values, and may not recover.

Therefore, no matter which mode is adopted by the adaptive state machine of the equalizer in the running process, if the received signal is abnormal, the adaptive state machine can possibly enter a deadlock state.

The out-of-place alarm signal is usually triggered by the physical mechanism of the single board or the optical module. When the single board or the optical module is inserted, the physical mechanism triggers the signal, and the out-of-position alarm signal is false (or represented by logic '0'); when the single board or optical module is pulled out, the physical mechanism will trigger the signal, and the out-of-position alarm signal is true (or represented by logic "1").

Loss of signal (LOS alarm) is an alarm for determining whether a received signal is lost, and usually, a Serializer-deserializer (Serdes) circuit of an optical module or a physical layer can provide an LOS alarm signal.

The serializer circuit is part of the physical layer of the communication system.

The equalizer circuit is part of a serializer circuit.

An equalizer adaptation state machine is used in conjunction with the equalizer circuit.

The Link state refers to a state of whether a service given by a data Link layer of a communication service is on (Link up) or off (Link down).

The service alarm refers to a service alarm given by a physical coding sublayer, a data link layer and the like of the communication service. Such as a Loss of frame Alarm (Loss of frame, LOF Alarm for short), a Loss of multi-frame Alarm (LOM Alarm for short), an opposite end fault Alarm (AIS Alarm for short), etc.

The equalizer self-adaptive algorithm reads the signal quality after equalization to judge the equalization effect and then obtains the direction of the next equalization adjustment.

When signal loss, short circuits to dc levels, and other abnormal conditions occur, the adaptive algorithm cannot achieve the desired signal quality whether it adjusts the equalizer parameters up or down, may adjust the equalizer parameters to extreme values, and may not recover.

When the signal returns from new to normal, the traffic cannot return to normal because the equalizer adaptation state machine is still in a deadlock state (otherwise referred to as a hang-up state).

Disclosure of Invention

The technical problem to be solved by the invention is to provide an equalizer adaptive state machine deadlock avoiding method which can timely remove deadlock and restore normal communication service.

The technical scheme adopted by the invention for solving the technical problem is that the deadlock avoidance method of the equalizer self-adaptive state machine is characterized by comprising the following steps:

1) reading the current link state;

2) waiting for a predetermined time;

3) inquiring and judging:

a. whether an out-of-position warning exists or not is judged, if yes, A is equal to 1, and if not, A is equal to 0;

b. whether LOS warning exists or not, if yes, B is equal to 1, and otherwise, B is equal to 0;

c. if a service alarm exists, if so, C is 1, otherwise, C is 0; (ii) a

If a is 0 and B is 0 and C is 0, returning to step 2);

if a is 0 and B is 0 and C is 1, proceed to step 4);

if a is 1 and B + C is 1 by logical addition, go to step 6);

4) judging whether the last link state is link down, if so, entering a step 5); if not, returning to the step 1);

5) restarting the state machine, setting the link state as link up, and then ending;

6) judging whether the last link state is link up, if so, entering a step 7); if not, returning to the step 1);

7) and stopping the state machine, setting the link state to link down, and then ending.

Further, the step 1) is as follows: reading the current link state, and setting the count value m of the counter to be 0;

the step 2) is as follows: if M is smaller than the preset value M, entering the step 3 after waiting for a preset time, otherwise ending;

the step 3) is as follows:

3) inquiring and judging:

a. whether an out-of-position warning exists or not is judged, if yes, A is equal to 1, and if not, A is equal to 0;

b. whether LOS warning exists or not, if yes, B is equal to 1, and otherwise, B is equal to 0;

c. if a service alarm exists, if so, C is 1, otherwise, C is 0; (ii) a

If a is 0 and B is 0 and C is 1, proceed to step 4);

if a is 0 and B is 0 and C is 1, then m is added together and returned to step 2);

if a is 1 and B + C is 1 by logical addition, the process proceeds to step 6).

The logical addition operation is to follow the following rule: if there is 1 in both (either one or both of 1) then the operation result is 1, and if both of 0 then the operation result is 0.

The invention is very suitable for the serial deserializing circuit with the self-adaptive equalization function in the communication service.

The invention can avoid the problem that the equalizer self-adaptive state machine enters a deadlock state due to the received signal abnormality and the like, and the equalizer function cannot be recovered even if the received signal is recovered to be normal.

Drawings

FIG. 1 is a flow chart of the present invention.

Detailed Description

The state machine of the present invention is referred to as CTLE or DFE adaptive state machine.

As shown in fig. 1.

In the initial state 101, the counter m is set to 0, and the current link state is read.

The Link states may be Link up and Link down.

Then, the waiting state 102 is entered, and the waiting time length can be set, wherein the waiting time is 200ms for example. The purpose of entering the waiting state is to reduce the frequency of inquiry, reduce the resource waste of the system and reduce the power consumption.

Then, the inquiry state 103 is entered, and 3 kinds of alarm signals are inquired: 1. whether there is an out-of-position alarm, 2, whether there is an LOS alarm, and 3, whether there is a service alarm signal.

The service alarm signal may select different alarms according to different protocols of the communication service, such as a frame loss alarm (LOF alarm), a multi-frame loss alarm (LOM alarm), an opposite end fault alarm (AIS alarm), and the like.

Generally, different alarm signals form an alarm tree according to the logical relationship, according to the requirements of the communication service protocol.

To reduce complexity, the traffic alarm signal may typically select one of the primary alarms or the final result of the alarm tree.

When the inquiry state 103 inquires that no alarm exists in the 3 alarm signals, the counter accumulation state 104 is entered. At this time, the counter m is m +1, and the standby state 102 is entered again.

The upper limit M of the counter M depends on different protocols and applications. The query can be circularly inquired among states 102, 103 and 104 all the time; or jumping out of the inquiry state after the counter M is larger than M, and entering the evasion process to end 111.

When the inquiry state 103 inquires about 3 alarm signals with alarms, the following processing is performed according to the difference of the alarm signals (in conjunction with fig. 1):

serial number	Out-of-place alarm (A)	LOS alarm (B)	Business alarm (C)	Treatment step
					a	0	0	0	104
b	0	0	1	107
					c	0	1	0	101
d	0	1	1	107
					e	1	0	0	109
f	1	0	1	109
					g	1	1	0	109
h	1	1	1	109

In actual operation, three cases of cde are very rare, so that they are listed as "others" in fig. 1, if they occur, they can be processed according to the above table, and if there is a state that is not listed in the above table, they are directly returned to 101.

After entering the state 105, the Link reading state 107 is entered, and it is determined whether the previous Link state is the Link down state.

If not, indicating that the current Link is normal, and re-entering the initial state 101.

If the Link down indicates that the current Link is abnormal, the restart state 108 is entered.

The restart state 108 resets the equalizer's CTLE and DFE parameters to initial values, the equalizer adaptation state machine restarts, and the Link state is set to Link up.

After the restart state 108 is completed, the current evasion procedure is ended, i.e., state 111.

After entering the state 106, the Link reading state 109 is entered, and whether the last Link state is the Link up state is determined.

If not, the Link up indicates that the current Link is abnormal, and the initial state 101 is entered from the beginning.

If the Link up is detected, it indicates that the current Link state conflicts with the alarm signal obtained from the query state 103.

Because the alarm signal queried by the query state 103, the out-of-position alarm and the LOS alarm are closer to the physical layer, i.e. the bottom layer of the communication protocol, and are more reliable, the current link is still judged to be abnormal.

The stop adaptation state 110 is entered, the CTLE and DFE adaptation of the equalizer is stopped, and the Link state register is changed to the Link down state.

After the adaptive stop state 110 is completed, the current avoidance procedure is ended, that is, the state 111.

The equalizer adaptation state machines of the present invention may comprise CTLE and DFE adaptation state machines.

The deadlock avoidance process of the self-adaptive state machine can be simultaneously applied to the CTLE and DFE self-adaptive state machines, and can also be applied to only one of the CTLE and DFE self-adaptive state machines.

The waiting time may be set to different values according to different protocol requirements of the communication service. The length of the waiting time is not limited.

All alarms specified by the communication service protocol fall within the possible scope of service alarms.

Claims (2)

1. The deadlock avoidance method of the equalizer self-adaptive state machine is characterized by comprising the following steps:

1) reading the current link state;

2) waiting for a predetermined time;

3) inquiring and judging:

a. whether an out-of-position warning exists or not is judged, if yes, A is equal to 1, and if not, A is equal to 0;

b. whether LOS warning exists or not, if yes, B is equal to 1, and otherwise, B is equal to 0;

c. if a service alarm exists, if so, C is 1, otherwise, C is 0;

if a is 0 and B is 0 and C is 0, returning to step 2);

if a is 0 and B is 0 and C is 1, proceed to step 4);

if a is 1 and B + C is 1 by logical addition, go to step 6);

4) judging whether the last link state is link down, if so, entering a step 5); if not, returning to the step 1);

5) restarting the state machine, setting the link state as link up, and then ending;

6) judging whether the last link state is link up, if so, entering a step 7); if not, returning to the step 1);

7) and stopping the state machine, setting the link state to link down, and then ending.

2. The equalizer adaptive state machine deadlock avoidance method of claim 1,

the step 1) is as follows: reading the current link state, and setting the count value m of the counter to be 0;

the step 2) is as follows: if M is smaller than the preset value M, entering the step 3 after waiting for a preset time, otherwise ending;

the step 3) is as follows:

3) inquiring and judging:

a. whether an out-of-position warning exists or not is judged, if yes, A is equal to 1, and if not, A is equal to 0;

b. whether LOS warning exists or not, if yes, B is equal to 1, and otherwise, B is equal to 0;

c. if a service alarm exists, if so, C is 1, otherwise, C is 0; (ii) a

If a is 0 and B is 0 and C is 1, proceed to step 4);

if a is 0 and B is 0 and C is 1, then m is added together and returned to step 2);

if a is 1 and B + C is 1 by logical addition, the process proceeds to step 6).

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