CN112073140A - CDR debugging method and device - Google Patents
CDR debugging method and device Download PDFInfo
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Abstract
The invention discloses a CDR debugging method and equipment, wherein the method is characterized in that a single disk and a master control exchange disk are powered on simultaneously, and clock data recovery CDR initialization is carried out on the single disk and the master control exchange disk; when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus; the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished; the self-adaptive CDR mode can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
Description
Technical Field
The invention relates to the field of embedded hardware, in particular to a CDR debugging method and equipment.
Background
In recent years, along with the popularization of 4G and 5G technologies and the rapid development of industrial networks such as smart cities and smart power grids, the Data volume increases in geometric level, the exchange capacity of an IP (IP Radio Access Network, IPRAN) router board card of a wireless Access Network is larger and larger, the rapid increase of the exchange capacity directly leads to the continuous increase of the bandwidth of a backboard of router equipment, the current mainstream supports a centralized IPRAN router of 5G communication, the backboard rate is generally 10Gbit/s and 25Gbit/s, after an electric signal with the 25Gbit/s rate passes through the backboard, the signal quality is obviously attenuated, and if Clock Data Recovery (CDR) is not increased at the receiving end of the board card, the situation of continuous error codes of the backboard is easily caused.
The existing centralized IPRAN router is interconnected by signals and generally comprises a backboard, a daughter card and a master control switch card, wherein an optical signal received by the daughter card 1 is sent to the master control switch card through the backboard, and the master control switch card transmits the signal to the daughter card 2 through the backboard according to a routing signal; in the whole interaction process, 25G signals pass through the backboard for multiple times, because the 25G signals are transmitted through the connector and the backboard, the signal quality can be obviously attenuated, and if the CDR is not added at the receiving end of the daughter card for signal compensation, Cyclic Redundancy Check (CRC) error codes can usually appear on the backboard.
Disclosure of Invention
The invention mainly aims to provide a CDR debugging method and equipment, and aims to solve the technical problem that CRC error codes are easy to occur on a centralized router back plate in the prior art.
In a first aspect, the present invention further provides a CDR debugging method, where the CDR debugging method includes:
simultaneously electrifying a single disk and a master control exchange disk, and carrying out Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk;
when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus;
and the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished.
Optionally, after the master switch board sends an initialization completion notification to the single board according to a preset custom bus when the master switch board completes initialization, the CDR debugging method further includes:
acquiring master control initialization completion time of the master control exchange disk, master control insertion time of the master control exchange disk into target exchange equipment and single disk insertion time of the single disk into the target exchange equipment;
and judging whether to inform the single disk to carry out CDR initialization again according to the master control initialization completion time, the master control insertion time and the single disk insertion time.
Optionally, the determining whether to notify the single disk to perform CDR initialization again according to the master initialization completion time, the master insertion time, and the single disk insertion time includes:
determining the sequence of the master control exchange disk and the single disk inserted into the target exchange device according to the master control insertion time and the single disk insertion time;
and judging whether to inform the single disk to carry out CDR initialization again according to the sequence and the main control initialization completion time.
Optionally, the determining whether to notify the single disk to perform CDR initialization again according to the sequence and the master initialization completion time includes:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, whether the single disk is informed to carry out CDR initialization again is judged according to the single disk insertion time and the master control initialization completion time;
and when the sequence is that the single disk is inserted first and the master control exchange disk is inserted later, informing the single disk to carry out CDR initialization again.
Optionally, when the order is that the master control exchange disk is inserted first and the single disk is inserted later, determining whether to notify the single disk to perform CDR initialization again according to the single disk insertion time and the master control initialization completion time includes:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, comparing the single disk insertion time with the master control initialization completion time;
when the single disk insertion time is before the master control initialization completion time, informing the single disk to perform CDR initialization again;
and when the single disk insertion time is after the master initialization completion time, informing the single disk not to perform CDR initialization again.
Optionally, the powering on the single disk and the master switch disk simultaneously and performing CDR initialization for clock data recovery on the single disk and the master switch disk include:
simultaneously powering on the single disk and the master control exchange disk;
in a first bit field of a preset custom bus, the master control exchange disk receives open source framework SSM data of a backboard;
the master control exchange disk sends master control configuration data to the preset custom bus;
in a second bit domain of the preset custom bus, the master control exchange disk synchronizes the single disk in a time domain;
and after the time domain synchronization, performing Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk.
Optionally, the synchronizing, by the master switch disk, the single disk in the second bit field of the preset custom bus in the time domain includes:
receiving time data information of the master control exchange disk through an RS-422 interface in a second bit field of the preset custom bus;
converting the time data information into an international atomic time format, adding preset time information, and generating time data to be transmitted;
after the rising edge of the next second pulse arrives, sending the time data to be transmitted to the preset custom bus;
the preset custom bus adds the preset time information to the time data to be transmitted, converts the time data to GPS time data in a GPS time format, and sends the GPS time data to the single disk;
and synchronizing the time domain of the master control exchange disk and the single disk according to a preset time synchronization source and the GPS time data.
Optionally, the synchronizing the time domain of the master switch disk and the single disk according to the preset time synchronization source and the GPS time data includes:
acquiring a preset time synchronization source of the single disc and a slot position second pulse of a synchronization source slot position of the preset time synchronization source, bridging the slot position second pulse to other slot positions of the single disc,
and the master control exchange disk bridges the slot second pulse to all signal lines outputting the second pulse, and the master control exchange disk and the single disk are synchronized by external time second pulse according to the GPS time data.
Optionally, after the single disk and the master switch disk are powered on simultaneously and the single disk and the master switch disk are subjected to CDR initialization for clock data recovery, the CDR debugging method further includes:
the single disk sends an on-position detection signal to the master control exchange disk, and the master control exchange disk determines the on-position state of the single disk according to the on-position detection signal;
and when the in-place state is not in, forwarding the current service to a standby single disk for processing.
In a second aspect, the present invention further provides a CDR debugging apparatus, where the CDR debugging apparatus includes the CDR debugging method described above.
According to the CDR debugging method provided by the invention, a single disk and a master control exchange disk are simultaneously electrified, and clock data recovery CDR initialization is carried out on the single disk and the master control exchange disk; when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus; the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished; the self-adaptive CDR mode can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
Drawings
FIG. 1 is a flowchart illustrating a CDR debugging method according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a CDR debugging method according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a CDR debugging method according to a third embodiment of the present invention;
FIG. 4 is a flowchart illustrating a CDR debugging method according to a fourth embodiment of the present invention;
FIG. 5 is a flowchart illustrating a CDR debugging method according to a fifth embodiment of the present invention;
FIG. 6 is a block diagram of the internal components of the main control switch board in the CDR debugging method of the present invention;
FIG. 7 is a block diagram of the internal components of a single disk in the CDR debugging method of the present invention;
FIG. 8 is a flowchart illustrating a CDR debugging method according to a sixth embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating an application of a default bus in the CDR debugging method of the present invention;
fig. 10 is a schematic structural diagram of a CDR debugging device in a hardware operating environment according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The solution of the embodiment of the invention is mainly as follows: performing Clock Data Recovery (CDR) initialization on a single disk and a master control exchange disk by simultaneously electrifying the single disk and the master control exchange disk; when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus; the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished; the self-adaptive CDR mode can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, meanwhile, the reliability and stability of the centralized IPRAN router equipment are also improved, and the technical problem that CRC error codes are prone to occurring on the backboard of the centralized router in the prior art is solved.
Referring to fig. 1, fig. 1 is a flowchart illustrating a CDR debugging method according to a first embodiment of the present invention.
In a first embodiment, the CDR debugging method includes the steps of:
step S10, the single disk and the master control exchange disk are powered on simultaneously, and the single disk and the master control exchange disk are initialized by the clock data recovery CDR.
It should be noted that the single disk is a tributary disk or a daughter card, and after the single disk and the master control exchange disk are powered on simultaneously, CDR initialization may be performed on the single disk and the master control exchange disk, and after CDR initialization is performed on the single disk and the master control exchange disk, preparation may be made for subsequent CDR speed adjustment.
Step S20, when the initialization of the master switch board is completed, the master switch board sends an initialization completion notification to the single board according to a preset custom bus.
It should be understood that the preset custom bus is a preset backplane bus, data transmission can be performed through the preset custom bus when the single disk and the master control exchange disk perform data interaction with the backplane, and when the master control exchange disk is initialized, the master control exchange disk can transmit an initialization completion notification to the single disk through the preset custom bus, so that the single disk determines that the master control exchange disk is initialized.
Step S30, the single disk performs CDR initialization again, and notifies the master switch disk after initialization is completed.
It can be understood that, after the single disk determines that the master switch disk has been initialized, the single disk CDR initialization is performed again, which can avoid CRC error code and improve the flexibility of CDR application.
In a specific implementation, the initialization completion time of the master control switch card of the centralized ip ran router device is generally about 3-6 minutes, while the initialization completion time of the daughter card is generally about 2 minutes, in this case, if the CDR initialization is not specially processed, the CDR is likely to lock the Serdes signal when the switch chip in the master control switch disk does not work normally, and at this time, the locked signal is incorrect, and the CRC error is likely to occur during communication.
According to the scheme, the single disk and the master control exchange disk are powered on simultaneously, and clock data recovery CDR initialization is carried out on the single disk and the master control exchange disk; when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus; the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished; the self-adaptive CDR mode can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
Further, fig. 2 is a schematic flowchart of a CDR debugging method according to a second embodiment of the present invention, and as shown in fig. 2, the CDR debugging method according to the second embodiment of the present invention is proposed based on the first embodiment, and in this embodiment, after step S20, the CDR debugging method further includes the following steps:
step S01, obtaining the master initialization completion time of the master switch disk, the master insertion time of the master switch disk into the target switch device, and the single disk insertion time of the single disk into the target switch device.
It should be noted that the master control initialization completion time is time taken by the master control switch disk from initialization start to initialization completion, the master control insertion time is insertion or embedding time when the master control switch disk is inserted into the target switch device, and the single disk insertion time is insertion or embedding time when the single disk is inserted into the target switch device.
In a specific implementation, the single-disk insertion time, the master insertion time, and the master initialization completion time of the master switch disk may be recorded by power supply clocks set in the single disk and the master switch disk, or may be recorded by an external clock, which is not limited in this embodiment.
Step S02, determining whether to notify the single disk to perform CDR initialization again according to the master initialization completion time, the master insertion time, and the single disk insertion time.
It can be understood that, according to the master initialization completion time, the master insertion time, and the single disk insertion time, it can be determined whether the single disk is inserted before the master switch disk initialization is completed or after the master switch disk initialization is completed, so as to determine whether to notify the single disk to perform CDR initialization again.
In this embodiment, by the above scheme, the master initialization completion time of the master switch board, the master insertion time of the master switch board into the target switch device, and the single-board insertion time of the single board into the target switch device are obtained; whether the single disk is informed to carry out CDR initialization again is judged according to the master control initialization completion time, the master control insertion time and the single disk insertion time, a self-adaptive mode of CDR can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
Further, fig. 3 is a flowchart illustrating a third embodiment of the CDR debugging method of the present invention, and as shown in fig. 3, the third embodiment of the CDR debugging method of the present invention is proposed based on the second embodiment, in this embodiment, the step S02 includes the following steps:
step S021, determining the sequence of the master control exchange disk and the single disk to be inserted into the target exchange device according to the master control insertion time and the single disk insertion time.
It should be noted that, by comparing the master control insertion time with the single disk insertion time, the sequence of inserting the master control switching disk and the single disk into the target switching device can be determined according to the comparison result, that is, whether the master control switching disk is inserted first or the single disk is inserted first into the target switching device, where the target switching device may be a centralized ip ran router device, may also be a switch device, and of course, may also be other types of switching devices, which is not limited in this embodiment.
And S022, judging whether to inform the single disk to carry out CDR initialization again according to the sequence and the main control initialization completion time.
It should be understood that whether to notify the single disk to perform CDR initialization again can be determined by the precedence order and the master initialization completion time, and the difference in precedence order determines whether to notify the single disk to perform CDR initialization again.
In this embodiment, by using the above scheme, the sequence of the master switch board and the single board being inserted into the target switch device is determined according to the master insertion time and the single board insertion time; whether the sub-card is informed to carry out CDR initialization again is judged according to the sequence and the master control initialization completion time, whether the sub-card is informed to carry out CDR initialization can be further accurately judged, the self-adaptive mode of CDR is realized, the problem that a backboard of a centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router device are also improved.
Further, fig. 4 is a schematic flowchart of a fourth embodiment of the CDR debugging method of the present invention, and as shown in fig. 4, the fourth embodiment of the CDR debugging method of the present invention is proposed based on the third embodiment, in this embodiment, the step S022 includes the following steps:
and S0221, judging whether to inform the single disk to carry out CDR initialization again according to the single disk insertion time and the master control initialization completion time when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later.
It should be noted that, when the sequence is that the master switch disk is inserted first and the single disk is inserted later, the single disk insertion time and the master initialization completion time are compared, and whether to notify the single disk to perform CDR initialization is determined according to a comparison result between the single disk insertion time and the master initialization completion time.
Further, the step S0221 specifically includes the following steps:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, comparing the single disk insertion time with the master control initialization completion time;
when the single disk insertion time is before the master control initialization completion time, informing the single disk to perform CDR initialization again;
and when the single disk insertion time is after the master initialization completion time, informing the single disk not to perform CDR initialization again.
It can be understood that, when the single disc insertion time is before the master control initialization completion time, that is, the single disc is already inserted before master control initialization, since the master control switch disc has not yet completed initialization, and the switch chip in the master control switch disc does not work normally, it is easy to lock the Serdes signal at this time, and the locked Serdes signal is incorrect, so that CRC errors are easily generated, and in order to avoid CRC errors, it is necessary to notify the single disc to perform CDR initialization again, so that the single disc performs CDR initialization; and when the single disk insertion time is after the main control initialization completion time, the single disk is inserted after the main control initialization is completed, and at this time, a CRC error code is not generated, so that the single disk is notified that CDR initialization is not to be performed again, that is, the single disk is not to be subjected to CDR initialization operation again.
And S0222, when the sequence is that the single disk is inserted first and the master control exchange disk is inserted later, informing the single disk to carry out CDR initialization again.
It should be understood that when the single disk is inserted first and the master switch disk is inserted later, the initialization of the single disk must be performed before the initialization of the master switch disk, and in this case, in order to avoid CRC errors during communication, the single disk is notified to perform CDR initialization again.
According to the scheme, when the main control exchange disk is inserted first and the single disk is inserted later, whether the single disk is notified to perform CDR initialization again is judged according to the single disk insertion time and the main control initialization completion time; when the single disks are inserted first and the master control exchange disk is inserted later, the single disks are informed to carry out CDR initialization again, whether the single disks are informed or not can be further accurately judged, the single disks are enabled to carry out CDR initialization, the self-adaptive mode of CDR is realized, the problem that a backboard of a centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
Further, fig. 5 is a flowchart illustrating a fifth embodiment of the CDR debugging method of the present invention, and as shown in fig. 5, the fifth embodiment of the CDR debugging method of the present invention is proposed based on the first embodiment, in this embodiment, the step S10 includes the following steps:
and step S11, powering on the single disk and the master switch disk simultaneously.
It can be understood that the single disk and the master switch disk are powered on simultaneously, that is, the single disk and the master switch disk are powered on simultaneously, so that clock synchronization is ensured, and preparation is made for subsequently judging whether the single disk is subjected to CDR initialization or not.
Step S12, in the first bit field of the preset custom bus, the master switch board receives the SSM data of the open source framework of the backplane.
It should be noted that the open source framework SSM data is a framework set data integrated by two open source frameworks, namely Spring and MyBatis, and the first bit field is a first memory length occupied by a bit in the preset custom bus, and the definition of the first bit field may be: each bus processes 2 slot positions, and each slot position processes 2 lines; each slot (16 slots in total from 0x10 to 0x1F, including the master switch disk slot) can select 1 and 2 SSMs participating in system processing from all ports of a single disk, the bus format and definition are shown in the following table:
the M1 field is a first bit field of the preset custom bus, the M2 field is a second bit field of the preset custom bus, and the transmission sequence of bytes in the first bit field on the bus is b7 … b 0; the 5 bytes in each line are defined as shown in the table below, with the direction being the single disk to master switch disk direction.
The 10 bytes in each slot are defined as shown in the following table, and the direction is from the master control exchange disk to the single disk;
it should be noted that, a single disk with multiple optical ports, such as a group branch disk or a daughter card, returns the corresponding relationship between the optical ports and the line 8kHz to the master control switch disk, if the selected optical port is used as a system source for locking, the master control switch disk sends out a 0Fh block in the direction of the single disk, otherwise, the selected optical port sends out a system SSM, that is, after the system locks the source, the system sends out 0Fh, which indicates that the system is active and does not lock other sources; the single disk sends the corresponding line alarm type to the master control exchange disk as a reference for judging the clock grade by the clock module; the BYT1 and BYT4 of the preset custom bus from the master control exchange disk to the single disk control the branch disk to send Reference clock (RFP) source selection of the backboard, so that the single disk of the preset custom bus selects the RFP source according to the two bytes, and the single disk of the preset custom bus is not selected through network management.
And step S13, the master control exchange disk sends the master control configuration data to the preset custom bus.
It can be understood that the master control switch board completes data exchange between the master control switch board and the backplane bus in the first bit Field of the preset custom bus through a Field Programmable Gate Array (FPGA), that is, data exchange between the master control switch board and the preset custom bus, and specifically, the master control switch board reports SSM data from the backplane to the master control, that is, the master control switch board receives SSM data of an open source framework of the backplane, and sends master control configuration data of the master control switch board to the preset custom bus.
And step S14, in the second bit field of the preset custom bus, the master control exchange disk synchronizes the single disk in the time field.
It should be noted that the second bit field is a second memory length occupied by bits in the preset custom bus, the first bit field and the second bit field are separated by 1 byte, and in the second bit field, the master switch board is responsible for processing synchronization of the external time synchronization interface and 3 sub-time fields in the node.
In a specific implementation, the structure of the master switch board is shown in fig. 6, where fig. 6 is a block diagram of internal components of the master switch board in the CDR debugging method of the present invention, and as shown in fig. 6, the master switch board includes: FPGA, main control chip, power clock, CPU, exchange chip and backplate seat, the inside mutual flow of main control exchange dish does: downloading an FPGA program, carrying out clock configuration on a power supply clock, and loading the drive of a main control chip and a switching chip, wherein the main control chip mainly completes the processing of a data packet, and the switching chip completes the data exchange, namely, the data is exchanged from one single disk to another single disk.
Accordingly, the structure of the single disk is shown in fig. 7, fig. 7 is a block diagram of the internal components of the single disk in the CDR debugging method of the present invention, and as shown in fig. 7, the single disk includes: the system comprises an FPGA, a 25G optical module, a power supply clock, an equalizer CDR and a back plate base, wherein the 25G optical module is an optical data exchange module coming out from a physical layer chip, can be converted from 4 paths of 10G into 1 path of 25G or from 1 path of 25G to 25G, and channels are selected by a space division cross chip generally.
It can be understood that, in the second bit field of the preset custom bus, the master switch board synchronizes the time domain of the single board, and the synchronization is performed to make time information of each board and different devices on the device consistent, and the implementation may be to perform time domain synchronization by using a power clock, or certainly, to implement time synchronization between the master switch board and the single board by using other manners, which is not limited in this embodiment.
Further, the step S14 specifically includes the following steps:
receiving time data information of the master control exchange disk through an RS-422 interface in a second bit field of the preset custom bus;
converting the time data information into an international atomic time format, adding preset time information, and generating time data to be transmitted;
after the rising edge of the next second pulse arrives, sending the time data to be transmitted to the preset custom bus;
the preset custom bus adds the preset time information to the time data to be transmitted, converts the time data to GPS time data in a GPS time format, and sends the GPS time data to the single disk;
and synchronizing the time domain of the master control exchange disk and the single disk according to a preset time synchronization source and the GPS time data.
In specific implementation, RS-422 interface communication can be generally completed in a main control switch disk FPGA, and the baud rate is as follows: 9600, N-8-1 (baud rate: 9600, parity bit: none, data bit: 8, stop bit: 1); time Data (TOD) of an external Time interface adopts a GPS Time format, while the internal of the node equipment adopts an International Atomic Time (TAI) format, and the FPGA needs to realize the conversion of the two formats; TOD information always occurs after the rising edge of the second pulse, regardless of the external time interface direction; after receiving TOD information from the RS-422 interface and converting the TOD information into a TAI format, adding 1, namely adding 1 transmission time information every 1 second, and sending the TOD information on a preset custom bus after the rising edge of the next pulse per second 1PPS arrives; when TOD information is received from a preset custom bus, the TOD information needs to be sent out on the preset custom bus after the rising edge of the next pulse per second 1PPS arrives, and at the moment, 1 is added to the TOD value; meanwhile, TOD after adding 1 should be converted into GPS time format and sent out on RS-422 interface.
Further, the step of synchronizing the time domain of the master control exchange disk and the single disk according to a preset time synchronization source and the GPS time data specifically includes the following steps:
acquiring a preset time synchronization source of the single disc and a slot position second pulse of a synchronization source slot position of the preset time synchronization source, bridging the slot position second pulse to other slot positions of the single disc,
and the master control exchange disk bridges the slot second pulse to all signal lines outputting the second pulse, and the master control exchange disk and the single disk are synchronized by external time second pulse according to the GPS time data.
It should be noted that, when the network manager statically designates the time synchronization source of the node device, the data bus, that is, the preset custom bus, is used to send out the working state of the tributary disk (daughter card) of each slot; meanwhile, 1PPS output from the synchronous source slot branch disk (daughter card) needs to be bridged to 1PPS of other slot (region) and external time synchronization (for the master control exchange disk, the selected input 1PPS is bridged to all output 1PPS signal lines); and detecting whether the pulse per second (1PPS) exists or not and reporting the pulse per second to the main control, detecting the rising edge, wherein the signal of the 1PPS is the pulse per second, and the frequency is 1 Hz.
Step S15, after the time domain synchronization, performing CDR initialization for clock data recovery on the single disk and the master switch disk.
It can be understood that, after the time domain synchronization, the single disk and the master control exchange disk may be subjected to CDR initialization, and the initialization at this time can ensure that the initialization time of the single disk and the master control exchange disk is synchronous, that is, the initialization operation is performed synchronously, which is beneficial to statistics of subsequent time, and improves the accuracy of determining whether the sub-disk performs CDR initialization again.
According to the scheme, the single disk and the master control exchange disk are powered on simultaneously; in a first bit field of a preset custom bus, the master control exchange disk receives open source framework SSM data of a backboard; the master control exchange disk sends master control configuration data to the preset custom bus; in a second bit domain of the preset custom bus, the master control exchange disk synchronizes the single disk in a time domain; after the time domain synchronization, performing Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk; the flexibility of CDR application can be greatly improved, the accuracy of judging whether the sub-disk carries out CDR initialization again is improved, and meanwhile, the reliability and the stability of the centralized IPRAN router equipment are also improved.
Further, fig. 8 is a flowchart illustrating a sixth embodiment of the CDR debugging method of the present invention, and as shown in fig. 8, the sixth embodiment of the CDR debugging method of the present invention is proposed based on the first embodiment, and in this embodiment, after step S10, the CDR debugging method further includes the following steps:
step S101, the single disk sends an in-place detection signal to the master control exchange disk, and the master control exchange disk determines the in-place state of the single disk according to the in-place detection signal.
It should be noted that the on-site detection signal is a signal of a current on-site state detected by the single disk, and the main control switching disk can determine the on-site state of the single disk through the on-site detection signal, that is, whether the single disk is on the target switching device at this time.
And step S102, when the in-place state is not present, forwarding the current service to a standby single disk for processing.
It can be understood that, when the in-place state is not present, that is, the single disk is not on the target switching device at this time, the current service is forwarded to the standby single disk for processing; each branch disk or sub-card has an in-place detection signal to be sent to the master control check disk, and whether the branch disk or the sub-card is in-place is detected in real time; when a branch disk or a daughter card is plugged, the service can be forwarded through other branch disks or daughter cards, and general services can have backup protection.
In a specific implementation, the application of the preset custom bus is as shown in fig. 9, fig. 9 is an application schematic diagram of the preset custom bus in the CDR debugging method of the present invention, as shown in fig. 9, the whole frame is powered on, that is, after the master switch card and the daughter card are powered on simultaneously, the daughter card completes initialization after 2 minutes, the master switch card completes initialization after 5 minutes, when the master switch card completes initialization, the master switch card notifies the daughter card of the completion of initialization through the custom bus, at this time, the daughter card initializes a CDR once again, and the daughter card notifies the master card after completing the CDR initialization, and interaction is completed; after the main control exchange card completes initialization, inserting 1 sub card at the moment, the main control immediately acquires the sub card in position, informing the main control exchange card after the sub card is initialized, judging that the sub card is inserted after the main control exchange card is initialized by the main control exchange card, and informing the sub card to complete interaction without initializing the sub card CDR chip again; after the sub-card is initialized, the main control exchange card is inserted, when the main control exchange card is initialized, the sub-card is informed to initialize the CDR again, and after the sub-card is initialized, the main control card is informed, and the interaction process is completed; the single bus circuit of the preset custom bus replaces a point-to-point circuit, the FPGA is adopted to complete the custom single bus protocol, the whole process is completed through a hardware real-time channel, and the reliability and the practicability of the centralized IPRAN router device are greatly improved.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a CDR debugging device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the CDR debugging apparatus may include: a processor 1001, such as a CPU, a communication bus 1002, a user side interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., a Wi-Fi interface). The Memory 1005 may be a high-speed RAM Memory or a Non-Volatile Memory (Non-Volatile Memory), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration of the apparatus shown in fig. 10 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 10, a memory 1005 as a storage medium may include an operating device, a network communication module, a user side interface module, and a CDR debugging program.
The apparatus of the present invention calls the CDR debugging program stored in the memory 1005 by the processor 1001, and performs the following operations:
simultaneously electrifying a single disk and a master control exchange disk, and carrying out Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk;
when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus;
and the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
acquiring master control initialization completion time of the master control exchange disk, master control insertion time of the master control exchange disk into target exchange equipment and single disk insertion time of the single disk into the target exchange equipment;
and judging whether to inform the single disk to carry out CDR initialization again according to the master control initialization completion time, the master control insertion time and the single disk insertion time.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
determining the sequence of the master control exchange disk and the single disk inserted into the target exchange device according to the master control insertion time and the single disk insertion time;
and judging whether to inform the single disk to carry out CDR initialization again according to the sequence and the main control initialization completion time.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, whether the single disk is informed to carry out CDR initialization again is judged according to the single disk insertion time and the master control initialization completion time;
and when the sequence is that the single disk is inserted first and the master control exchange disk is inserted later, informing the single disk to carry out CDR initialization again.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, comparing the single disk insertion time with the master control initialization completion time;
when the single disk insertion time is before the master control initialization completion time, informing the single disk to perform CDR initialization again;
and when the single disk insertion time is after the master initialization completion time, informing the single disk not to perform CDR initialization again.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
simultaneously powering on the single disk and the master control exchange disk;
in a first bit field of a preset custom bus, the master control exchange disk receives open source framework SSM data of a backboard;
the master control exchange disk sends master control configuration data to the preset custom bus;
in a second bit domain of the preset custom bus, the master control exchange disk synchronizes the single disk in a time domain;
and after the time domain synchronization, performing Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
receiving time data information of the master control exchange disk through an RS-422 interface in a second bit field of the preset custom bus;
converting the time data information into an international atomic time format, adding preset time information, and generating time data to be transmitted;
after the rising edge of the next second pulse arrives, sending the time data to be transmitted to the preset custom bus;
the preset custom bus adds the preset time information to the time data to be transmitted, converts the time data to GPS time data in a GPS time format, and sends the GPS time data to the single disk;
and synchronizing the time domain of the master control exchange disk and the single disk according to a preset time synchronization source and the GPS time data.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
acquiring a preset time synchronization source of the single disc and a slot position second pulse of a synchronization source slot position of the preset time synchronization source, bridging the slot position second pulse to other slot positions of the single disc,
and the master control exchange disk bridges the slot second pulse to all signal lines outputting the second pulse, and the master control exchange disk and the single disk are synchronized by external time second pulse according to the GPS time data.
Further, processor 1001 may call a CDR debugging program stored in memory 1005, and also perform the following operations:
the single disk sends an on-position detection signal to the master control exchange disk, and the master control exchange disk determines the on-position state of the single disk according to the on-position detection signal;
and when the in-place state is not in, forwarding the current service to a standby single disk for processing.
According to the scheme, the single disk and the master control exchange disk are powered on simultaneously, and clock data recovery CDR initialization is carried out on the single disk and the master control exchange disk; when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus; the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished; the self-adaptive CDR mode can be conveniently adopted on the centralized IPRAN router and the switch equipment, the problem that a backboard of the centralized router is prone to error codes is successfully solved, the flexibility of CDR application is greatly improved, and meanwhile the reliability and the stability of the centralized IPRAN router equipment are also improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A CDR debugging method is characterized by comprising the following steps:
simultaneously electrifying a single disk and a master control exchange disk, and carrying out Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk;
when the master control exchange disk is initialized, the master control exchange disk sends an initialization completion notification to the single disk according to a preset custom bus;
and the single disk carries out CDR initialization again and informs the master control exchange disk after the initialization is finished.
2. The CDR debugging method of claim 1, wherein after the master switch board sends an initialization completion notification to the single board according to a preset custom bus when the master switch board initialization is completed, the CDR debugging method further comprises:
acquiring master control initialization completion time of the master control exchange disk, master control insertion time of the master control exchange disk into target exchange equipment and single disk insertion time of the single disk into the target exchange equipment;
and judging whether to inform the single disk to carry out CDR initialization again according to the master control initialization completion time, the master control insertion time and the single disk insertion time.
3. The CDR debugging method of claim 2, wherein the determining whether to notify the single disk of performing CDR initialization again according to the master initialization completion time, the master insertion time, and the single disk insertion time comprises:
determining the sequence of the master control exchange disk and the single disk inserted into the target exchange device according to the master control insertion time and the single disk insertion time;
and judging whether to inform the single disk to carry out CDR initialization again according to the sequence and the main control initialization completion time.
4. The CDR debugging method of claim 3, wherein the determining whether to notify the single disk of performing CDR initialization again according to the sequence and the master initialization completion time comprises:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, whether the single disk is informed to carry out CDR initialization again is judged according to the single disk insertion time and the master control initialization completion time;
and when the sequence is that the single disk is inserted first and the master control exchange disk is inserted later, informing the single disk to carry out CDR initialization again.
5. The CDR debugging method of claim 4, wherein the determining whether to notify the single disk to perform CDR initialization again according to the single disk insertion time and the master initialization completion time when the precedence order is that the master switch disk is inserted first and the single disk is inserted later comprises:
when the sequence is that the master control exchange disk is inserted first and the single disk is inserted later, comparing the single disk insertion time with the master control initialization completion time;
when the single disk insertion time is before the master control initialization completion time, informing the single disk to perform CDR initialization again;
and when the single disk insertion time is after the master initialization completion time, informing the single disk not to perform CDR initialization again.
6. The CDR debugging method of any one of claims 1-5, wherein the powering on a single disk and a master switch disk simultaneously, performing Clock Data Recovery (CDR) initialization on the single disk and the master switch disk, comprises:
simultaneously powering on the single disk and the master control exchange disk;
in a first bit field of a preset custom bus, the master control exchange disk receives open source framework SSM data of a backboard;
the master control exchange disk sends master control configuration data to the preset custom bus;
in a second bit domain of the preset custom bus, the master control exchange disk synchronizes the single disk in a time domain;
and after the time domain synchronization, performing Clock Data Recovery (CDR) initialization on the single disk and the master control exchange disk.
7. The CDR debugging method of claim 6, wherein the time domain synchronization of the single disk by the master switch disk in the second bit domain of the preset custom bus comprises:
receiving time data information of the master control exchange disk through an RS-422 interface in a second bit field of the preset custom bus;
converting the time data information into an international atomic time format, adding preset time information, and generating time data to be transmitted;
after the rising edge of the next second pulse arrives, sending the time data to be transmitted to the preset custom bus;
the preset custom bus adds the preset time information to the time data to be transmitted, converts the time data to GPS time data in a GPS time format, and sends the GPS time data to the single disk;
and synchronizing the time domain of the master control exchange disk and the single disk according to a preset time synchronization source and the GPS time data.
8. The CDR debugging method of claim 7, wherein the time domain synchronizing the master switch disk and the single disk according to a preset time synchronization source and the GPS time data comprises:
acquiring a preset time synchronization source of the single disc and a slot position second pulse of a synchronization source slot position of the preset time synchronization source, bridging the slot position second pulse to other slot positions of the single disc,
and the master control exchange disk bridges the slot second pulse to all signal lines outputting the second pulse, and the master control exchange disk and the single disk are synchronized by external time second pulse according to the GPS time data.
9. The CDR debugging method of any one of claims 1-5, wherein the single disk and a master switch disk are powered on simultaneously, and after performing Clock Data Recovery (CDR) initialization on the single disk and the master switch disk, the CDR debugging method further comprises:
the single disk sends an on-position detection signal to the master control exchange disk, and the master control exchange disk determines the on-position state of the single disk according to the on-position detection signal;
and when the in-place state is not in, forwarding the current service to a standby single disk for processing.
10. A CDR debugging device, comprising: a memory, a processor, and a CDR debugging program stored on the memory and executable on the processor, the CDR debugging program configured to implement the steps of the CDR debugging method of any one of claims 1 to 9.
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