CN112073032A - Low-pass filter circuit - Google Patents

Low-pass filter circuit Download PDF

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Publication number
CN112073032A
CN112073032A CN202011033188.1A CN202011033188A CN112073032A CN 112073032 A CN112073032 A CN 112073032A CN 202011033188 A CN202011033188 A CN 202011033188A CN 112073032 A CN112073032 A CN 112073032A
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Prior art keywords
pass filter
filter circuit
low
transconductance amplifier
output
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Inventor
熊中燕
郑卫国
项勇
万鸿
王江涛
陈毅敏
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Techtotop Microelectronics Co Ltd
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Techtotop Microelectronics Co Ltd
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Priority to CN202011033188.1A priority Critical patent/CN112073032A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks

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Abstract

The application relates to the field of circuits, and provides a low-pass filter circuit which comprises an amplifying circuit with adjustable gain, a high-pass filter circuit and a low-pass filter circuit with gain configuration of 1, wherein the amplifying circuit with the variable gain is arranged at the front end of the filter circuit, so that the signal-to-noise ratio is improved, the gain configuration of the low-pass filter circuit is 1, the power consumption of an input-stage transconductance amplifier of the low-pass filter circuit is reduced, and the occupied area of a circuit board is reduced; in addition, the high-pass filter circuit can filter direct current offset and target low-frequency signals to reduce low-frequency noise.

Description

Low-pass filter circuit
Technical Field
The application belongs to the technical field of circuits, and particularly relates to a low-pass filter circuit.
Background
The low-pass filter circuit plays an important role in communication, navigation and various signal detection and transmission systems, and is usually used for suppressing out-of-band signals and reducing noise and interference of high-frequency leakage signals. In order to reduce the overall noise of the system, it is generally required that the signal path has a sufficient gain in the preceding stage, and therefore the gain of the filter is essential in a high performance system.
As the requirement for channel width is now widened, the bandwidth of the filter is required to be widened, so that the transconductance value Gm0 (i.e. gain) of the input stage transconductance amplifier that determines the bandwidth of the filter is required to be increased, while the gain of the Gm _ C (formed by the transconductance amplifier and the grounded capacitor) filter is equal to Gm0/2Gm1, and Gm1 is the transconductance value of the transconductance amplifier of the later stage. In the conventional low-pass filter, if a gain of 20dB is required, the Gm0 needs to be equal to 20 times of the Gm1, the input stage transconductance amplifier consumes very large power consumption, and occupies a large area of a circuit board, so that the overall power consumption of the mobile device is limited. Or alternatively gain is applied to the filter and then amplified, but the noise contribution of this approach will be large, affecting the signal-to-noise ratio requirements received by the channel.
Disclosure of Invention
The application provides a low pass filter circuit, aims at solving traditional low pass filter circuit high power dissipation, occupies the big problem of circuit board area.
The present application is achieved as a low-pass filter circuit comprising:
the amplifying circuit is used for carrying out differential amplification on a pair of input signals according to a preset gain and then outputting the signals, wherein the preset gain is adjustable;
the high-pass filter circuit is connected with the output of the amplifying circuit and is used for coupling the alternating current signal output by the amplifying circuit so as to filter direct current offset and a target low-frequency signal, and the alternating current signal is output after common-mode bias voltage is superposed;
and the low-pass filter circuit is connected with the output of the high-pass filter circuit and is used for performing high-pass filtering on the signal output by the high-pass filter circuit and outputting a differential signal of a target bandwidth and a target cutoff frequency, and the gain of the low-pass filter circuit is configured to be 1.
In some embodiments, the capacitance value of the ground capacitor in the low-pass filter circuit is adjustable, and the bandwidth and/or the cut-off frequency of the differential signal output by the low-pass filter circuit is adjusted by adjusting the capacitance value of the ground capacitor.
In some embodiments, the grounded capacitor includes a first capacitor and at least one second capacitor, and the first capacitor and each of the second capacitors are respectively connected between a transconductance amplifier on the low-pass filter circuit and the ground through a switch.
In some embodiments, the switch connected with the first capacitor is controlled to be switched on and off by inputting a first switch signal so as to adjust the bandwidth, and the switch connected with the second capacitor is controlled to be switched on and off by inputting a second switch signal so as to adjust the cut-off frequency.
In some of these embodiments, the low pass filter circuit is a third order low pass filter circuit.
In some embodiments, the low pass filter circuit comprises an input stage transconductance amplifier, a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, a fifth transconductance amplifier, and a sixth transconductance amplifier, wherein:
the input end of the input stage transconductance amplifier is connected with the output of the high-pass filter circuit, the output end of the input stage transconductance amplifier is connected with the input and the output of the first transconductance amplifier, the output end of the second transconductance amplifier is connected with the output of the first transconductance amplifier and the input of the third transconductance amplifier in common, the input end of the second transconductance amplifier, the output end of the third transconductance amplifier, the output end of the fourth transconductance amplifier and the output and the input of the fifth transconductance amplifier are connected in common, the input end of the fourth transconductance amplifier, the input end of the fifth transconductance amplifier and the output and the input of the sixth transconductance amplifier are connected in common, and the connection point of the input and the output of the sixth transconductance amplifier is used as the output of the low-pass filter circuit; the output of the first transconductance amplifier, the output of the third transconductance amplifier and the output of the fifth transconductance amplifier are respectively connected with the grounding capacitor.
In some embodiments, the high-pass filter circuit includes a first coupling capacitor, a second coupling capacitor, a first resistor, and a second resistor, the first coupling capacitor and the second coupling capacitor are respectively connected in series to a differential transmission line between the amplifier circuit and the low-pass filter circuit, one end of the first resistor is connected between the first coupling capacitor and the low-pass filter circuit, one end of the second resistor is connected between the second coupling capacitor and the low-pass filter circuit, and the other end of the first resistor and the other end of the second resistor are connected to a common-mode reference voltage.
In some embodiments, the amplifying circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an adjustable resistor array, a first output load, and a second output load;
the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are used for accessing the pair of input signals, the source electrode of the first NMOS tube is connected with one end of the adjustable resistor array, the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the sixth PMOS tube; the source electrode of the second NMOS tube is connected with the other end of the adjustable resistor array, the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube and the drain electrode of the seventh PMOS tube; the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube are connected in common and connected with a bias voltage; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are grounded, the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube are connected in common, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with a working power supply, the grid electrode of the third PMOS tube is grounded through the first output load, the grid electrode of the fourth PMOS tube is grounded through the second output load, and a connection point of the grid electrode of the third PMOS tube and the first output load and a connection point of the grid electrode of the fourth PMOS tube and the second output load are respectively used as two outputs of the amplifying circuit.
In some of these embodiments, the adjustable resistive array comprises: and the two ends of the plurality of impedance circuits are respectively connected to one end and the other end of the adjustable resistor array, and each impedance circuit comprises at least one impedance device and a switch connected with the at least one impedance device in series.
In some of these embodiments, the impedance of the first output load and the second output load is adjustable.
The low-pass filter circuit improves the signal-to-noise ratio by placing the variable-gain amplifying circuit at the front end of the filter circuit, so that the gain of the low-pass filter circuit can be configured to be 1, the power consumption of the input-stage transconductance amplifier of the low-pass filter circuit is reduced, and the occupied area of a circuit board is reduced; in addition, the high-pass filter circuit can filter direct current offset and target low-frequency signals to reduce low-frequency noise.
Drawings
Fig. 1 is a block diagram of a low-pass filter circuit according to an embodiment of the present application.
Fig. 2 is a circuit diagram of a low pass filter circuit provided in an embodiment of the present application;
fig. 3 is a circuit diagram of an amplifying circuit of the low-pass filter circuit shown in fig. 2;
fig. 4 is a circuit diagram of the ground capacitance of the low-pass filter circuit shown in fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, a low pass filter circuit includes an amplifying circuit 10 with adjustable gain, a high pass filter circuit 20 and a low pass filter circuit 30.
The amplifying circuit 10 is configured to differentially amplify and output a pair of input signals VinP and VinN according to a preset gain, where the preset gain is adjustable; the high-pass filter circuit 20 is connected to the output of the amplifier circuit 10, and is configured to couple the ac signal output by the amplifier circuit 10 to filter the dc offset and the target low-frequency signal, and output after superimposing the common-mode bias voltage; the low-pass filter circuit 30 is connected to an output of the high-pass filter circuit 20, and is configured to high-pass filter the signal output from the high-pass filter circuit 20, and output a differential signal between a target bandwidth and a target cutoff frequency, and a gain of the low-pass filter circuit 30 is set to 1.
The amplifier circuit 10 is a pseudo-differential structure open-loop amplifier circuit using local source negative feedback, and gain change can be realized by adjusting a source negative feedback resistor, so that the circuit gain is changed, the circuit has the advantages of low power consumption and high linearity, and meanwhile, the amplifier circuit 10 is placed at the front ends of the filter circuits 20 and 30, so that the signal-to-noise ratio is improved. In the actual circuit production process or layout design, mismatch occurs, which results in dc offset generated at the output of the amplifying circuit 10, and the high-pass filter circuit 20 can solve the problem.
Referring to fig. 2, the low-pass filter circuit 30 is a multi-order low-pass filter composed of a transconductance amplifier and a ground capacitor, in the present application, a transconductance value Gm0 of the input-stage transconductance amplifier 37 is twice as large as a transconductance value Gm1 of each of the transconductance amplifiers 31 to 36 of the subsequent stages, so that the overall gain of the low-pass filter circuit 30 is 1, the low-pass filter circuit 30 does not amplify signals any more, power consumption can be saved, the transconductance value of the input-stage transconductance amplifier 37 is small, the size of the device can be small, and the occupied area is greatly reduced.
Referring to fig. 3, in some embodiments, the amplifying circuit 10 includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a first PMOS transistor M6, a second PMOS transistor M7, a third PMOS transistor M8, a fourth PMOS transistor M9, a fifth PMOS transistor M10, a sixth PMOS transistor M11, a seventh PMOS transistor M12, an adjustable resistor array 11, a first output load R11, and a second output load R12, where;
the gate of the first NMOS transistor M1 and the gate of the second NMOS transistor M2 are inputs of the amplifying circuit 10 and are used for accessing a pair of input signals VinP and VinN, the source of the first NMOS transistor M1 is connected with one end of the adjustable resistor array 11, the drain of the first PMOS transistor M6 and the drain of the third NMOS transistor M3, and the drain of the first NMOS transistor M1 is connected with the gate of the first PMOS transistor M6, the gate of the third PMOS transistor M8 and the drain of the sixth PMOS transistor M11; the source electrode of the second NMOS transistor M2 is connected to the other end of the adjustable resistor array 11, the drain electrode of the second PMOS transistor M7 and the drain electrode of the fourth NMOS transistor M4, and the drain electrode of the second NMOS transistor M2 is connected to the gate electrode of the second PMOS transistor M7, the gate electrode of the fourth PMOS transistor M9 and the drain electrode of the seventh PMOS transistor M12; the grid electrode of the third NMOS transistor M3, the grid electrode of the fourth NMOS transistor M4 and the grid electrode of the fifth NMOS transistor M5 are connected in common and connected with a bias voltage VB; the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4 and the source of the fifth NMOS transistor M5 are grounded, the drain of the fifth NMOS transistor M5 is connected to the drain of the fifth PMOS transistor M10, the gate of the fifth PMOS transistor M10, the drain of the fifth PMOS transistor M10, the gate of the sixth PMOS transistor M11 and the gate of the seventh PMOS transistor M12 are grounded, the source of the first PMOS transistor M6, the source of the second PMOS transistor M7, the source of the third PMOS transistor M8, the source of the fourth PMOS transistor M9, the source of the fifth PMOS transistor M10, the source of the sixth PMOS transistor M11 and the source of the seventh PMOS transistor M12 are connected to an operating power supply, the gate of the third PMOS transistor M8 is grounded through the first output load R11, and the gate of the fourth PMOS transistor M9 is grounded through the second output load R12, the connection point between the gate of the third PMOS transistor M8 and the first output load R11 and the connection point between the gate of the fourth PMOS transistor M9 and the second output load R12 are respectively used as two outputs of the amplifier circuit 10.
The first NMOS transistor M1 and the second NMOS transistor M2 are input differential pair transistors, the grid electrode of the first NMOS transistor M1 is an input port of an input signal VinP, the grid electrode of the second NMOS transistor M2 is an input port of an input signal VinN, different gain selections can be realized by adjusting the equivalent resistance value of the adjustable resistor array 11 connected into the circuit, and the adjustable resistor array 11 is connected between the source electrode of the first NMOS transistor M1 and the source electrode of the second NMOS transistor M2 and forms a negative feedback structure; the first PMOS transistor M6 and the second PMOS transistor M7 are devices that function as negative feedback. The third NMOS transistor M3 and the fourth NMOS transistor M4 mirror the current of the fifth NMOS transistor M5 to play a role of current bias, the sixth PMOS transistor M11 and the seventh PMOS transistor M12 mirror the current of the fifth PMOS transistor M10 to be the current load bias of the first NMOS transistor M1 and the second NMOS transistor M2, the proportion of the current consumed by the sixth PMOS transistor M11 to the current of the third NMOS transistor M3 of the bias transistor is less than half, and the fifth PMOS transistor M10 is connected with the fifth NMOS transistor M5 to form a current path. The current of the third PMOS transistor M8 mirror feedback device, the first PMOS transistor M6, is used as the output current, the drain of the third PMOS transistor M8 is the output port of the output signal VoutP, and the drain of the fourth PMOS transistor M9 is the output port of the output signal VoutN. The first output load R11 and the second output load R12 can determine the gain value and the output common mode voltage, and the gain of the amplifying circuit 10 can be simply regarded as the ratio of the resistance value of the first output load R11 and the equivalent resistance value of the adjustable resistor array 11, so that the gain of the amplifying circuit 10 can be adjusted by adjusting the resistance value of the adjustable resistor array 11 or the first output load R11.
Referring to fig. 3, in some embodiments, the adjustable resistor array 11 includes a plurality of impedance circuits, two ends of the plurality of impedance circuits are respectively connected to one end and the other end of the adjustable resistor array 11, and each impedance circuit includes at least one impedance device and a switch connected in series with the at least one impedance device. In an example, taking an impedance circuit as an example, the impedance circuit includes a switch (such as an NMOS transistor) M13 and two impedance devices R13 and R14 connected in series across the switch M13, and the switch M13 is controlled by a switch signal S1 to select whether the impedance circuit is connected in the circuit or not, so as to adjust the equivalent resistance of the adjustable resistor array 11. In a further embodiment, the impedance of the first output load R11 and the second output load R12 is adjustable. Therefore, adjusting the resistance of the adjustable resistor array 11 or the first output load R11 can adjust the gain of the amplifying circuit 10.
Referring to fig. 2, in some embodiments, the high-pass filter circuit 20 includes a first coupling capacitor C1, a second coupling capacitor C2, a first resistor R1, and a second resistor R2, the first coupling capacitor C1 and the second coupling capacitor C2 are respectively connected in series to a differential transmission line between the amplifier circuit 10 and the low-pass filter circuit 30, one end of the first resistor R1 is connected between the first coupling capacitor C1 and the low-pass filter circuit 30, one end of the second resistor R2 is connected between the second coupling capacitor C2 and the low-pass filter circuit 30, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to the common mode reference voltage.
The first coupling capacitor C1 and the second coupling capacitor C2 are respectively connected in series between the output of the amplifying circuit 10 and the input of the input stage transconductance amplifier 37 of the low pass filter circuit 30, and couple the ac signal of the previous stage. One end of the first resistor R1 is connected to the first coupling capacitor C1, the other end is connected to the common-mode reference voltage VCM, one end of the second resistor R2 is connected to the second coupling capacitor C2, the other end is connected to the common-mode reference voltage VCM, the first resistor R1, the second resistors R2R1 and R2 form a filter circuit with high-pass characteristic together with the first coupling capacitor C1 and the second coupling capacitor C2 while providing an input common-mode bias voltage for the input-stage transconductance amplifier 37, so as to filter out dc offset and target low-frequency signals and reduce low-frequency noise. The target low frequency is matched and adjusted according to the system requirements and parameters of the coupling capacitors C1 and C2 and the resistors R1 and R2.
Referring to fig. 2, in one example, the low pass filter circuit 30 is a third order low pass filter circuit. The third-order low pass filter circuit includes an input stage transconductance amplifier 37, a first transconductance amplifier 31, a second transconductance amplifier 32, a third transconductance amplifier 33, a fourth transconductance amplifier 34, a fifth transconductance amplifier 35, and a sixth transconductance amplifier 36, wherein:
the input of the input stage transconductance amplifier 37 is connected with the output of the high-pass filter circuit 20, the output of the input stage transconductance amplifier 37 is connected with the input and the output of the first transconductance amplifier 31, the output of the second transconductance amplifier 32 is connected with the output of the first transconductance amplifier 31 and the input of the third transconductance amplifier 33, the input of the second transconductance amplifier 32, the output of the third transconductance amplifier 33, the output of the fourth transconductance amplifier 34 and the output of the fifth transconductance amplifier 35 are connected in common, the input of the fourth transconductance amplifier 34, the input of the fifth transconductance amplifier 35 and the output and the input of the sixth transconductance amplifier 36 are connected in common, and the connection point of the input and the output of the sixth transconductance amplifier 36 is used as the output of the low-pass filter circuit 30; the output of the first transconductance amplifier 31, the output of the third transconductance amplifier 33, and the output of the fifth transconductance amplifier 35 are connected to a ground capacitor C/C2, respectively. The capacitance values of the grounded capacitance C connected to the output of the first transconductance amplifier 31 and the output of the fifth transconductance amplifier 35 and the grounded capacitance C2 connected to the output of the third transconductance amplifier 33 may be different.
Let the transconductance value of the input stage transconductance amplifier 37 be Gm0, and the transconductance values Gm1 Gm6 of the first to sixth transconductance amplifiers 31-36 be equal. The input stage transconductance amplifier 37 mainly converts voltage into current, and the input terminal is connected to the output nodes a and b of the RC high-pass filter circuit 20, wherein a common-mode feedback circuit is arranged inside the first transconductance amplifier 31, the third transconductance amplifier 33 and the fifth transconductance amplifier 35 to provide a stable output common-mode voltage.
Optionally, the capacitance of the grounded capacitor C/C2 in the low-pass filter circuit 30 is adjustable, and the bandwidth and/or cut-off frequency of the differential signal output by the low-pass filter circuit 30 is adjusted by adjusting the capacitance of the grounded capacitor C/C2.
Referring to fig. 4, the grounding capacitor C/C2 includes a first capacitor C00 and at least one second capacitor C01-C04, and the first capacitor C00 and each second capacitor are respectively connected between the transconductance amplifier of the low pass filter circuit 30 and the ground through a switch M00-M04. The on-off of a switch M00 connected with the first capacitor is controlled by inputting a first switch signal B so as to adjust/select the bandwidth of the low-pass filter circuit 30, and the on-off of switches M01-M04 connected with the second capacitors C01-C04 are respectively controlled by inputting second switch signals C < 4-1 > so as to adjust/calibrate the cut-off frequency of the low-pass filter circuit 30. Terminals P and N are shown with one connected to the output of the transconductance amplifier and the other to ground.
In one example, the first capacitor C00 is connected to the NMOS device M00, the first capacitor C00 is connected to the circuit when the first switch signal B is high, the bandwidth of the low pass filter circuit 30 becomes smaller, and the bandwidth of the low pass filter circuit 30 becomes larger when the first switch signal B is low. In at least one second capacitor C01-C04, the capacitor C01 is connected with the NMOS device M01, the capacitor C02 is connected with the NMOS device M02, the capacitor C04 is connected with the NMOS device M03, the capacitor C08 is connected with the NMOS device M04, 16 combinations of second switching signals C <4> -1 > can be used for calibrating the cut-off frequency of the low-pass filter circuit 30, a default value of the second switching signals C <4> -1 > is set to be equal to 1000 (binary coding), namely the second switching signals C <4> are high level, and the second switching signals C <3>, C <2> and C <1> are low level, so that the bandwidth adjustment of the low-pass filter circuit 30 can be increased and reduced.
Referring to fig. 2 and 4, the gain of the low pass filter circuit 30 is equal to Gm0/2Gm1, and in the present embodiment, the gain is provided by the pre-stage variable gain amplifier circuit 10, so the low pass filter circuit 30 does not need gain, and Gm0 is set equal to 2 times Gm1, i.e. the gain is equal to 1, and the bandwidth is equal to 1
Figure BDA0002704382650000091
Cutoff frequency Q equal to
Figure BDA0002704382650000092
C2The capacitance value of the ground capacitor C2 connected to the two output terminals of the third transconductance amplifier 33 is C, which is the capacitance value of the ground capacitor C connected to the two output terminals of the first and fifth transconductance amplifiers 31 and 35.
Compared with the prior art, the signal-to-noise ratio transmission method and the signal-to-noise ratio transmission device have the advantages that the circuit structure is innovated, the requirements of the transmission channel on the signal-to-noise ratio are met, the power consumption and the occupied board area are reduced, and the signal-to-noise ratio transmission method and the signal-to-noise ratio transmission device are very suitable for being used in a mobile terminal device integrated circuit with.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A low pass filter circuit, comprising:
the amplifying circuit is used for carrying out differential amplification on a pair of input signals according to a preset gain and then outputting the signals, wherein the preset gain is adjustable;
the high-pass filter circuit is connected with the output of the amplifying circuit and is used for coupling the alternating current signal output by the amplifying circuit so as to filter direct current offset and a target low-frequency signal, and the alternating current signal is output after common-mode bias voltage is superposed;
and the low-pass filter circuit is connected with the output of the high-pass filter circuit and is used for performing high-pass filtering on the signal output by the high-pass filter circuit and outputting a differential signal of a target bandwidth and a target cutoff frequency, and the gain of the low-pass filter circuit is configured to be 1.
2. The low-pass filter circuit according to claim 1, wherein a capacitance value of a ground capacitor in the low-pass filter circuit is adjustable, and a bandwidth and/or a cutoff frequency of a differential signal output from the low-pass filter circuit is adjusted by adjusting the capacitance value of the ground capacitor.
3. A low-pass filter circuit as claimed in claim 2, characterized in that said grounded capacitance comprises a first capacitance and at least one second capacitance, said first capacitance and each of said second capacitances being connected via a switch to ground and a transconductance amplifier on said low-pass filter circuit, respectively.
4. A low-pass filter circuit as claimed in claim 3, characterized in that the bandwidth is adjusted by switching a switch connected to the first capacitor by inputting a first switching signal, and the cut-off frequency is adjusted by switching a switch connected to the second capacitor by inputting a second switching signal.
5. A low-pass filter circuit as claimed in any one of claims 1 to 4, characterized in that the low-pass filter circuit is a third-order low-pass filter circuit.
6. A low pass filter circuit as claimed in claim 2, wherein the low pass filter circuit comprises an input stage transconductance amplifier, a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, a fifth transconductance amplifier, and a sixth transconductance amplifier, wherein:
the input end of the input stage transconductance amplifier is connected with the output of the high-pass filter circuit, the output end of the input stage transconductance amplifier is connected with the input and the output of the first transconductance amplifier, the output end of the second transconductance amplifier is connected with the output of the first transconductance amplifier and the input of the third transconductance amplifier, the input end of the second transconductance amplifier, the output end of the third transconductance amplifier, the output end of the fourth transconductance amplifier and the input end of the fifth transconductance amplifier are connected in common, the input end of the fourth transconductance amplifier, the output end of the fifth transconductance amplifier and the output and the input end of the sixth transconductance amplifier are connected in common, and the connection point of the input end and the output end of the sixth transconductance amplifier is used as the output of the low-pass filter circuit; the output of the first transconductance amplifier, the output of the third transconductance amplifier and the output of the fifth transconductance amplifier are respectively connected with the grounding capacitor.
7. The low-pass filter circuit as claimed in claim 1, 2, 3, 4 or 6, wherein the high-pass filter circuit comprises a first coupling capacitor, a second coupling capacitor, a first resistor and a second resistor, the first coupling capacitor and the second coupling capacitor are respectively connected in series with a differential transmission line between the amplifying circuit and the low-pass filter circuit, one end of the first resistor is connected between the first coupling capacitor and the low-pass filter circuit, one end of the second resistor is connected between the second coupling capacitor and the low-pass filter circuit, and the other end of the first resistor and the other end of the second resistor are connected to a common-mode reference voltage.
8. The low pass filter circuit of claim 1, 2, 3, 4 or 6, wherein the amplifying circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an adjustable resistor array, a first output load and a second output load, wherein;
the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are used for accessing the pair of input signals, the source electrode of the first NMOS tube is connected with one end of the adjustable resistor array, the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the sixth PMOS tube; the source electrode of the second NMOS tube is connected with the other end of the adjustable resistor array, the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube and the drain electrode of the seventh PMOS tube; the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube are connected in common and connected with a bias voltage; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are grounded, the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube are connected in common, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with a working power supply, the grid electrode of the third PMOS tube is grounded through the first output load, the grid electrode of the fourth PMOS tube is grounded through the second output load, and a connection point of the grid electrode of the third PMOS tube and the first output load and a connection point of the grid electrode of the fourth PMOS tube and the second output load are respectively used as two outputs of the amplifying circuit.
9. A low pass filter circuit as claimed in claim 8, wherein said adjustable resistor array comprises: and the two ends of the plurality of impedance circuits are respectively connected to one end and the other end of the adjustable resistor array, and each impedance circuit comprises at least one impedance device and a switch connected with the at least one impedance device in series.
10. A low pass filter circuit as claimed in claim 8, wherein the impedance of the first output load and the second output load is adjustable.
CN202011033188.1A 2020-09-27 2020-09-27 Low-pass filter circuit Pending CN112073032A (en)

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CN202011033188.1A CN112073032A (en) 2020-09-27 2020-09-27 Low-pass filter circuit

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Application Number Priority Date Filing Date Title
CN202011033188.1A CN112073032A (en) 2020-09-27 2020-09-27 Low-pass filter circuit

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CN112073032A true CN112073032A (en) 2020-12-11

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CN202011033188.1A Pending CN112073032A (en) 2020-09-27 2020-09-27 Low-pass filter circuit

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