CN112072763B

CN112072763B - Load state detection circuit and power chip

Info

Publication number: CN112072763B
Application number: CN202011251182.1A
Authority: CN
Inventors: 刘彬; 李瑞平; 池伟; 陈博; 许锦龙
Original assignee: Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Current assignee: Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Priority date: 2020-11-11
Filing date: 2020-11-11
Publication date: 2021-01-26
Anticipated expiration: 2040-11-11
Also published as: CN112072763A

Abstract

The invention provides a load state detection circuit and a power supply chip, wherein the load state detection circuit comprises a constant voltage source module, a power supply module and a signal module, wherein a first input end and a second input end of the signal module are respectively connected with a first end and a second end of a first resistor of the power supply module, and a current working state of a load is judged by detecting the current flowing through the first resistor and the voltage of the second end, so that a power output circuit is driven to be started. The configuration enables the power chip to be capable of closing the power chip under the no-load state to reduce energy consumption to the maximum extent, closing the power chip under the short-circuit condition to protect the power chip from being damaged by short-circuit current, and being capable of automatically starting when the short-circuit state of the load is removed, so that the three requirements that the power chip can not simultaneously meet the requirements of reducing energy consumption under the no-load state, protecting the power chip under the short-circuit condition and automatically starting when the short-circuit state is removed in the prior art are solved.

Description

Load state detection circuit and power chip

Technical Field

The invention relates to the technical field of power chips, in particular to a load state detection circuit and a power chip.

Background

For a power converter device using a battery as a power supply, the loss of an output end in a no-load state is an important design index because the capacity of the battery is limited and the frequency of application of the power converter device is relatively low; taking a USB port charger on an electric bicycle as an example, the USB port charger is in an idle state at an output end most of the time, and if the current consumed in the idle state is 3mA, the current is not large, but may affect the user experience. If the portable electric tool is applied, the problem is more prominent because the battery capacity of the portable electric tool is small, and the battery capacity may be consumed by the portable electric tool after a period of time, which may affect the normal use of the portable electric tool. In order to avoid the situation that the power converter consumes the electric quantity of a battery due to large power consumption in a long-term no-load state, a power converter solution with low power consumption is needed;

in addition, in the normal use process, the output end is short-circuited due to careless operation, so that the chip is easy to be damaged due to high loss and high temperature, and even the chip is damaged seriously, thereby bringing serious potential safety hazard to the product.

For the scheme of the power converter equipment with the high-voltage battery pack as the power supply, part of customer solutions are made by adopting an imported low-power-consumption power supply chip, the cost is high, the shelf life is unstable, and importantly, the power consumption of the made product is still more than 1mA in the no-load state, the automatic power on-off function is not provided, namely, the problem of power consumption in the no-load state cannot be thoroughly solved, and the problem of output short-circuit protection still exists; in addition, a part of solutions are solved by matching a power supply chip with an MCU and a power MOS tube, and although an autonomous power on/off function and a short-circuit protection function can be realized, the power consumption in an idle state exceeds 1mA, and the solution circuit is complex and high in cost.

To sum up, the problem that the three requirements of reducing energy consumption in an idle state, protecting the power supply chip under a short-circuit condition and automatically starting the power supply chip when the short-circuit condition is removed cannot be met simultaneously by the conventional power supply chip.

Disclosure of Invention

The invention aims to provide a load state detection circuit and a power supply chip, and aims to solve the problems that the existing power supply chip cannot simultaneously meet three requirements of reducing energy consumption in an idle state, protecting the power supply chip in a short-circuit condition and automatically starting the power supply chip when the short-circuit state is removed.

In order to solve the above technical problem, the present invention provides a load status detection circuit, which includes a constant voltage source module, a power supply module and a signal module,

the power supply module comprises a first resistor and a first transistor, the first transistor is an NPN type triode, a first end of the first resistor is connected with an output end of the constant voltage source module, a second end of the first resistor is connected with a collector electrode of the first transistor, the collector electrode and a base electrode of the first transistor are connected, and an emitter electrode of the first transistor is used for being connected with a load;

the first input end of the signal module is connected with the first end of the first resistor, the second input end of the signal module is connected with the second end of the first resistor, and the signal module is configured to output a working signal to drive the power output circuit to be turned on when the reference current flowing through the first resistor meets a first preset condition and the reference voltage obtained by the second input end of the signal module meets a second preset condition.

Optionally, the first preset condition includes that the reference current is greater than 0A and the duration exceeds a preset duration.

Optionally, the second preset condition includes that the reference voltage is greater than 1.4V and the duration time exceeds the preset duration.

Optionally, the signal module includes a charge-discharge submodule and a capacitor;

the charge and discharge sub-module is configured to charge the capacitor when the reference current is greater than 0A and the reference voltage is greater than 1.4V, and otherwise, to discharge the capacitor;

the signal module is configured to output the operating signal when the voltage of the capacitor is greater than or equal to a preset voltage.

Optionally, the constant voltage source module is further configured to provide a bias current, the charge/discharge submodule includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a second resistor, a third resistor, and a fourth resistor, and the signal module further includes an eighth transistor;

the second transistor is a PNP type triode, an emitter of the second transistor is connected with the first end of the first resistor, and a base of the second transistor is connected with the second end of the first resistor and used for acquiring the reference voltage;

the third transistor is an NPN type triode, a collector electrode of the third transistor is connected with a collector electrode of the second transistor, and a base electrode of the third transistor is connected with a collector electrode of the third transistor;

the fourth transistor is an NPN type triode, a collector electrode of the fourth transistor is connected with an emitter electrode of the third transistor, and a base electrode of the fourth transistor is connected with a collector electrode of the fourth transistor;

one end of the second resistor is connected with a collector of the second transistor, and the other end of the second resistor is connected with an emitter of the fifth transistor;

the fifth transistor is a PNP type triode, and the collector of the fifth transistor is grounded;

one end of the third resistor is connected with an emitting electrode of the fourth transistor, and the other end of the third resistor is connected with a base electrode of the seventh transistor;

one end of the fourth resistor is connected with an emitting electrode of the fourth transistor, and the other end of the fourth resistor is grounded;

the sixth transistor is an NPN-type triode, a collector of the sixth transistor is connected with a base of the fifth transistor, a base of the sixth transistor is connected with a collector of the seventh transistor, and an emitter of the sixth transistor is grounded;

the seventh transistor is an NPN-type triode, a collector of the seventh transistor is used for obtaining the bias current, and an emitter of the seventh transistor is grounded;

one end of the capacitor is connected with a collector of the sixth transistor, and the other end of the capacitor is connected with an emitter of the sixth transistor;

the eighth transistor is an NPN-type triode, a collector of the eighth transistor is used for acquiring the bias current and outputting the working signal, a base of the eighth transistor is connected with a collector of the sixth transistor, and an emitter of the eighth transistor is connected with an emitter of the sixth transistor.

Optionally, the signal module is further configured to periodically output the working signal with a first preset pulse width when the reference voltage does not satisfy the second preset condition.

Optionally, the load state detection circuit further includes a timing module, an enable end of the timing module is connected to the second output end of the signal module, and an output end of the timing module is connected to the third input end of the signal module;

the signal module is configured to send an enable signal to the timing module through a second output end of the signal module when the reference voltage does not satisfy the second preset condition, and output the working signal with a first preset pulse width through a first output end of the signal module when a third input end of the signal module receives a trigger signal sent by the timing module with a second preset pulse width and the reference voltage does not satisfy the second preset condition;

the timing module is configured to periodically send the trigger signal of the second preset pulse width to the signal module when receiving the enable signal sent by the signal module.

Optionally, the constant voltage source module includes a constant current source, a current mirror and a voltage regulating resistor interface, the voltage regulating resistor interface is used for being connected with an external voltage regulating resistor, the constant current source is connected with an input end of the current mirror, and the voltage regulating resistor is connected with an output end of the current mirror;

the voltage provided by the constant voltage source module is realized by the current output by the current mirror flowing through the voltage regulating resistor.

Optionally, the voltage output by the constant voltage source module is greater than the working voltage provided by the power output circuit, and the difference range is 1.45V-1.55V.

In order to solve the above technical problem, the present invention provides a power chip, where the power chip includes the above load state detection circuit and a power output circuit, where the load state detection circuit and the power output circuit are powered by the same power supply, a first output end of the signal module is connected to an enable end of the power output circuit, a power supply output end of the power output circuit is connected to a load, and the power output circuit is configured to turn on and supply power to the load when the enable end of the power output circuit receives the working signal; otherwise, closing.

In the load state detection circuit and the power supply chip provided by the invention, the load state detection circuit comprises a constant voltage source module, a power supply module and a signal module, wherein a first input end and a second input end of the signal module are respectively connected with a first end and a second end of a first resistor of the power supply module, and the current working state of a load is judged by detecting the current flowing through the first resistor and the voltage of the second end, so that a power output circuit is driven to be started. The configuration enables the power chip to be capable of closing the power chip under the no-load state to reduce energy consumption to the maximum extent, closing the power chip under the short-circuit condition to protect the power chip from being damaged by short-circuit current, and being capable of automatically starting when the short-circuit state of the load is removed, so that the three requirements that the power chip can not simultaneously meet the requirements of reducing energy consumption under the no-load state, protecting the power chip under the short-circuit condition and automatically starting when the short-circuit state is removed in the prior art are solved.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:

fig. 1 is a schematic structural diagram of a load state detection circuit according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a power chip according to a first embodiment of the invention;

FIG. 3 is a circuit diagram of a load status detection circuit according to a second embodiment of the present invention;

fig. 4 is a waveform diagram of a load state detection circuit when a constant voltage load is connected according to a second embodiment of the present invention;

fig. 5 is a schematic waveform diagram of the load state detection circuit according to the second embodiment of the present invention when the load state detection circuit is connected to a constant current load or a constant resistance load;

FIG. 6 is a circuit diagram of a load status detection circuit according to a third embodiment of the present invention;

fig. 7 is a waveform diagram of the load state detection circuit according to the third embodiment of the present invention when the load state detection circuit is connected to a constant current load or a constant resistance load;

fig. 8 is a partially enlarged schematic view of a portion a in fig. 7.

In the drawings:

10-a load state detection circuit; 20-a power output circuit; 30-load; 40-voltage regulating resistance; 50-a power supply;

100-a constant voltage source module; 200-a power supply module; 300-a signal module; 400-a timing module;

110-a constant current source; 120-a current mirror; 130-voltage regulating resistor interface; 210-a first resistance; 220 — a first transistor; 310-charge and discharge submodule; 320-a capacitor; 330-eighth transistor; 410-a timing power supply module; 420-automatically reset timer.

Detailed Description

To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.

As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "proximal end" and "distal end" generally refer to the corresponding two parts, which include not only the end points, but also the terms "mounted", "connected" and "connected" should be understood broadly, e.g., as a fixed connection, as a detachable connection, or as an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The core idea of the invention is to provide a load state detection circuit and a power supply chip, so as to solve the problem that the existing power supply chip can not simultaneously meet the three requirements of reducing energy consumption in an idle state, protecting the power supply chip in a short-circuit condition and automatically starting the power supply chip when the short-circuit condition is removed.

The following description refers to the accompanying drawings.

[ EXAMPLES one ]

Referring to fig. 1 to 2, in which fig. 1 is a schematic structural diagram of a load status detection circuit according to a first embodiment of the present invention; FIG. 2 is a schematic structural diagram of a power chip according to a first embodiment of the invention

As shown in fig. 1, the load condition detection circuit 10 of this embodiment includes a constant voltage source module 100, a power supply module 200 and a signal module 300, where the power supply module 200 includes a first resistor 210 and a first transistor 220, the first transistor 220 is an NPN-type transistor, a first end of the first resistor 210 is connected to an output end of the constant voltage source module 100, a second end of the first resistor 210 is connected to a collector of the first transistor 220, a collector and a base of the first transistor 220 are connected, and an emitter of the first transistor 220 is used for connecting to a load 30;

the first input end of the signal module 300 is connected to the first end of the first resistor 210, the second input end of the signal module 300 is connected to the second end of the first resistor 210, and the signal module is configured such that, when the reference current flowing through the first resistor 210 satisfies a first preset condition and the reference voltage obtained at the second input end of the signal module 300 satisfies a second preset condition, the first output end of the signal module 300 outputs the working signal to drive the power output circuit 20 to be turned on.

It should be understood that the reference current may be calculated according to a voltage difference between the voltage obtained at the first input terminal of the signal module 300 and the reference voltage, and a resistance value of the first resistor 210; or the reference current is not calculated, and whether the reference current meets the first preset condition or not is directly judged through a reasonably designed circuit; the specific implementation manner of determining whether the reference current satisfies the first preset condition is not limited herein. The working signal is at one of a high level or a low level. When the reference current satisfies a first preset condition and the reference voltage satisfies a second preset condition, the first output terminal of the signal module 300 outputs the working signal, the configuration may be made according to the common knowledge in the art, for example, by first using an analog-to-digital conversion circuit to obtain a reference voltage, obtaining a reference current through a digital logic circuit, judging whether the reference voltage and the reference current accord with the preset conditions through another digital logic circuit, and converting the determination result into the working signal that can be recognized by the power output circuit, or for example, referring to [ embodiment two ], if the circuit is in a circuit form that can output the working signal when the reference current meets a first preset condition and the reference voltage meets a second preset condition, the circuit form should be regarded as the protection scope of the claims of the present application.

So configured, firstly, the detection accuracy of the load state detection circuit 10 is improved by the constant voltage source module 100; then, by configuring the first transistor 220, the damage to the load state detection circuit, which may be caused when the load is in an unfavorable operation state, is prevented; then, by configuring the first resistor 210, the signal module 300 can reverse the working state of the load through the working state of the first resistor 210, and finally, by reasonably configuring the first preset condition and the second preset condition, when the load is in a normal working state, the signal module 300 outputs the working signal, the power output circuit is turned on, and when the load is in an unfavorable working state, the power output circuit is turned off, therefore, the power supply chip can be turned off to reduce energy consumption to the maximum extent under the no-load state, can be turned off to protect the power supply chip from being damaged by short-circuit current under the short-circuit condition, and can be automatically started when the short-circuit condition of the load is removed, and the three requirements that the power supply chip can not simultaneously reduce energy consumption under the no-load state, protect the power supply chip under the short-circuit condition and automatically start when the short-circuit condition is removed in the prior art are met.

Preferably, the first preset condition includes that the reference current is greater than 0A and the duration exceeds a preset duration. Whether the reference current is greater than 0A or not can be used for judging whether the current is no-load or not, and is also beneficial to the simplified design of the circuit, and the signal module 300 can be allowed to directly judge whether the condition that the reference current is greater than 0A is satisfied or not without calculating the value of the reference current first and then judging whether the condition is satisfied or not according to the calculated value. The preset duration is used for preventing poor contact in the hot plug process of the load 30, so that an internal circuit is repeatedly started, and application experience and system performance are influenced.

Further, the second preset condition includes that the reference voltage is greater than 1.4V and the duration exceeds the preset duration. Whether the reference voltage is greater than 1.4V or not can be used for judging whether the load 30 is in a short-circuit state at present, according to experience, when the output voltage of the load 30 in a short-circuit state is lower than the voltage of normal operation, generally within 0.5V, and the voltage drop caused by the first transistor 220 is calculated to be 0.7V, therefore, if the reference voltage is less than 1.2V, the load 30 is likely to be in the short-circuit state, and the judgment basis of 1.4V is adopted in implementation, on one hand, the safety margin can be increased, the possibility of misjudgment is reduced, on the other hand, the integral multiple of 0.7V is also provided, and the value of 0.7V is close to the conduction voltage drop value of the triode, so that the configuration is convenient for the design of subsequent circuits (the integral multiple means that when other circuits are matched with the circuit in the current section, only a small number of triodes need to be matched to operate, and if the integral multiple is not, a complex, and the number of transistors used will increase).

Based on the first preset condition and the second preset condition, the specific implementation manner of the signal module 300 may be various, and in a preferred embodiment, the signal module 300 includes a charging and discharging submodule 310 and a capacitor 320;

the charging and discharging submodule 310 is configured to charge the capacitor 320 when the reference current is greater than 0A and the reference voltage is greater than 1.4V, and otherwise, to discharge the capacitor 320;

the signal module 300 is configured to output the operation signal when the voltage of the capacitor 320 is greater than or equal to a preset voltage;

the charging and discharging submodule 310 charges the capacitor 320 so that the total time period for which the voltage of the capacitor 320 is raised from 0V to the preset voltage is the preset time period.

It should be understood that the logic for outputting the operation signal when the voltage of the capacitor 320 is greater than or equal to a preset voltage may be configured according to the common knowledge in the art, for example, a voltage comparison circuit is used to obtain the voltage of the capacitor 320 and the preset voltage, and the voltage comparison circuit is configured to output the operation signal when the obtained voltage of the capacitor 320 is greater than or equal to the obtained preset voltage. Preferably, the preset voltage is set as a turn-on voltage of a transistor, and the logic is implemented by matching with other elements, and specific implementation schemes can be understood according to the related descriptions of the second embodiment. However, whatever the implementation manner, the circuit form of the signal module 300 outputting the working signal when the voltage of the capacitor 320 is greater than or equal to the preset voltage should be regarded as the protection scope of the claims of the present application.

If the output end of the power supply module 200 of this embodiment is connected to a constant voltage load, when the working condition of the load changes from a short circuit to a normal connection load, the reference voltage will automatically increase to above 1.4V, and after a preset time period, the signal module 300 can output a working signal to drive the power output circuit 20 to be turned on again. However, under some working conditions, if a constant current or constant resistance load is connected, since the current provided by the load state detection circuit 10 itself is relatively small, the reference voltage is not automatically raised to above 1.4V in a state where the power output circuit 20 is not operating, and the power output circuit 20 cannot be automatically restarted.

In order to improve the adaptability of the load status detecting circuit 10, in a preferred embodiment, the signal module 300 is further configured to periodically output the working signal with a first preset pulse width when the reference voltage does not satisfy the second preset condition. By periodically activating the power output circuit 20, it is detected whether the short circuit condition of the load has been released. In a certain period, if the short-circuit state of the load is not yet released, the signal module 300 does not continuously send the working signal after sending the working signal with the first preset pulse width, but waits for an interval of one period to send the working signal with the first preset pulse width again, during which the power output circuit 20 enters the off state again to save the electric energy; if the short-circuit state of the load 30 is removed, after the signal module 300 sends the working signal with the first preset pulse width, since the reference current meets the first preset condition and the reference voltage meets the second preset condition, the signal module 300 will continue to send the working signal, so that the power output circuit 20 enters the continuous working state.

It is emphasized that, the inventors have conducted a careful analysis on the timing of the periodic transmission of the operating signal with the first preset pulse width, and it is generally easy to conceive of designing the periodic detection signal under the condition that the load is unloaded or short-circuited, so that the power output circuit 20 can be automatically restarted under any condition. However, in practice, such a scheme is not preferable, because the load-unloaded condition may last for a long time, and in the load-unloaded condition, repeatedly and briefly activating the power output circuit 20 may generate high energy consumption, so that the initial power-saving design purpose is not well achieved, and secondly, such frequent activation may result in shortened service life of the power output circuit 20 or accidental damage. The working signal with the first preset pulse width is sent periodically in the short-circuit state, so that the reasonable design is achieved, the short-circuit state is always followed by other alarm measures, an operator of the circuit can eliminate the short-circuit state of the load in a short time, at the moment, the requirement that the circuit can recover to work in the first time is that the priority is high, and therefore the working signal with the first preset pulse width is sent periodically in the time period, so that the reasonable design is achieved, and the comprehensive effect of better power saving and self-starting can be achieved. Therefore, preferably, the signal module 300 is configured not to periodically transmit the operation signal with the first preset pulse width when the load is unloaded.

Of course, in the state of no-load or short-circuit of the load, the working signal with the preset pulse width is periodically sent, so that the problems that the existing power supply chip cannot simultaneously meet the three requirements of reducing energy consumption in the no-load state, protecting the power supply chip in the case of short-circuit, and automatically starting the power supply chip when the short-circuit state is removed can be solved, and the protection scope of the claims of the present application should be considered.

In an embodiment, the load status detecting circuit 10 further includes a timing module 400, an enable terminal of the timing module 400 is connected to the second output terminal of the signal module 300, and an output terminal of the timing module 400 is connected to the third input terminal of the signal module 300;

the signal module 300 is configured to send an enable signal to the timing module 400 through a second output terminal of the signal module when the reference voltage does not satisfy the second preset condition, and output the working signal with a first preset pulse width through a first output terminal of the signal module when a third input terminal of the signal module receives a trigger signal that the timing module 400 sends a second preset pulse width and the reference voltage does not satisfy the second preset condition;

the timing module 400 is configured to periodically send the trigger signal of the second preset pulse width to the signal module 300 when receiving the enable signal sent by the signal module 300.

It should be understood that the second preset pulse width and the first preset pulse width may be equal or unequal, and the specific implementation manner thereof may be determined by actual requirements and the specific connection manner of the circuit. If the signal module 300 simply converts the trigger signal into the working signal and outputs the working signal, the second preset pulse width is equal to the first preset pulse width, and if consideration is given based on other requirements, such as prevention of malfunction, the second preset pulse width may be made larger than the first preset pulse width, and the signal module 300 may delay the working signal for a period of time when receiving the trigger signal, where the delay time is equal to a difference between the second preset pulse width and the first preset pulse width and then output the working signal.

The timing module 400 and the signal module 300 are used to send the trigger signal and receive the trigger signal and convert the trigger signal into the working signal, and the specific circuit forms thereof may be set according to common knowledge in the art, and an implementation manner thereof may be understood according to the related contents in [ embodiment three ]. No matter what specific circuit form they take, so long as the working logic described in the present embodiment is implemented, it should be regarded as the protection scope of the claims of the present application.

In an exemplary embodiment, the constant voltage source module 100 includes a constant current source 110, a current mirror 120 and a voltage regulating resistor interface 130, the voltage regulating resistor interface 130 is configured to be connected to an external voltage regulating resistor 40, the constant current source 110 is connected to an input terminal of the current mirror 120, and the voltage regulating resistor 40 is connected to an output terminal of the current mirror 120;

the voltage provided by the constant voltage source module 100 is realized by the current outputted by the current mirror 120 flowing through the voltage regulating resistor 40. Specifically, the constant current source 110 generates a constant current, and after the constant current is copied by the current mirror, the configuration is formed, so that the power chip where the load state detection circuit 10 is located is suitable for power supplies with different voltages, and the adaptability of the power chip is improved.

Further, the voltage output by the constant voltage source module 100 is greater than the working voltage provided by the power output circuit 20, and the difference range is between 1.45V and 1.55V.

So configured, when the voltage output by the constant voltage source module 100 is output to the load through the first resistor 210 and the first transistor 220, the output voltage is close to the operating voltage provided by the power output circuit 20, and the influence of the load state detection circuit 10 on the power supply state of the load is minimized.

As shown in fig. 2, the power chip provided in this embodiment includes the above-mentioned load state detection circuit 10 and the power output circuit 20, where the load state detection circuit 10 and the power output circuit 20 are powered by the same power supply 50, a first output terminal of the signal module 300 is connected to an enable terminal of the power output circuit 20, a power supply output terminal of the power output circuit 20 is connected to a load, and the power output circuit 20 is configured to turn on and supply power to the load 30 when the enable terminal of the power output circuit 20 receives the operating signal; otherwise, closing. It should be understood that the specific circuit form of the power output circuit 20 can be configured by those skilled in the art according to the practical situation and the prior art, and the other components and connection modes of the power supply chip can be configured by those skilled in the art according to the practical situation and the prior art, which are not described in detail in the present specification.

Because the power chip comprises the load state detection circuit 10, the power chip also has the beneficial effect of the load state detection circuit 10, and can solve the problem that the power chip in the prior art cannot simultaneously meet the three requirements of reducing energy consumption in an idle state, protecting the power chip in a short-circuit condition and automatically starting the power chip when the short-circuit state is removed.

[ example two ]

Referring to fig. 3 to 5, fig. 3 is a circuit schematic diagram of a load status detection circuit according to a second embodiment of the present invention; fig. 4 is a waveform diagram of a load state detection circuit when a constant voltage load is connected according to a second embodiment of the present invention; fig. 5 is a waveform diagram of the load state detection circuit according to the second embodiment of the present invention when the load state detection circuit is connected to a constant current load or a constant resistance load.

As shown in fig. 3, the present embodiment provides a load condition detection circuit 10, where the load condition detection circuit 10 includes a constant voltage source module 100, a power supply module 200, and a signal module 300.

The constant voltage source module 100 includes a constant current source 110, a current mirror 120 and a voltage regulating resistor interface 130, wherein the voltage regulating resistor interface 130 is used for connecting with an external voltage regulating resistor 40, the constant current source 110 is connected with an input end of the current mirror 120, and the voltage regulating resistor 40 is connected with an output end of the current mirror 120;

the voltage provided by the constant voltage source module 100 is realized by the current outputted by the current mirror 120 flowing through the voltage regulating resistor 40.

The constant voltage source module 100 further comprises a first constant voltage source transistor Q12, a second constant voltage source transistor Q14, and a constant voltage source capacitor C2;

the first constant-voltage source transistor Q12 is a PNP-type triode, the base of the first constant-voltage source transistor Q12 is connected to the voltage-regulating resistor interface 130, the emitter of the first constant-voltage source transistor Q12 is connected to an output end of the current mirror 120, and the collector of the first constant-voltage source transistor Q12 is grounded;

the second constant voltage source transistor Q14 is an NPN-type triode, a base of the second constant voltage source transistor Q14 is connected to an emitter of the first constant voltage source transistor Q12, a collector of the second constant voltage source transistor Q14 is connected to an output end of the current mirror 120, an emitter of the second constant voltage source transistor Q14 is connected to one end of the constant voltage source capacitor C2, and the other end of the constant voltage source capacitor C2 is grounded.

So configured, a constant voltage can be provided for use by subsequent circuitry. It should be understood that, in the circuit connection manner shown in fig. 3, the output voltage of the constant voltage source module 100 = the current I1 of the constant current source 110 × the resistance value of the voltage regulating resistor 40. Preferably, the output voltage of the constant voltage source module 100 can be maintained at 1.5V higher than the operating voltage provided by the power output circuit 20 by adjusting the resistance value of the voltage regulating resistor 40.

The power supply module 200 includes a first resistor 210 and a first transistor 220, the first transistor 220 is an NPN-type transistor, a first end of the first resistor 210 is connected to an emitter of the second constant voltage source transistor Q14, a second end of the first resistor 210 is connected to a collector of the first transistor 220, the collector and a base of the first transistor 220 are connected, and the emitter of the first transistor 220 is used for connecting to the load 30.

With the configuration, the judgment basis of the load working state can be provided for the signal module.

The constant voltage source module is further used for providing a bias current, the charge and discharge submodule comprises a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, a second resistor R2, a third resistor R3 and a fourth resistor R4, and the signal module further comprises an eighth transistor 330;

the second transistor Q2 is a PNP-type triode, the emitter of the second transistor Q2 is connected to the first end of the first resistor 210, and the base of the second transistor Q2 is connected to the second end of the first resistor 210 for obtaining the reference voltage;

the third transistor Q3 is an NPN-type transistor, the collector of the third transistor Q3 is connected to the collector of the second transistor Q2, and the base of the third transistor Q3 is connected to its own collector;

the fourth transistor Q4 is an NPN-type transistor, the collector of the fourth transistor Q4 is connected to the emitter of the third transistor Q3, and the base of the fourth transistor Q4 is connected to its own collector;

one end of the second resistor R2 is connected to the collector of the second transistor Q2, and the other end is connected to the emitter of the fifth transistor Q5;

the fifth transistor Q5 is a PNP-type triode, and the collector of the fifth transistor Q5 is grounded;

one end of the third resistor R3 is connected with the emitter of the fourth transistor Q4, and the other end is connected with the base of the seventh transistor Q7;

one end of the fourth resistor R4 is connected with the emitter of the fourth transistor Q4, and the other end is grounded;

the sixth transistor Q6 is an NPN-type triode, the collector of the sixth transistor Q6 is connected to the base of the fifth transistor Q5, the base of the sixth transistor Q6 is connected to the collector of the seventh transistor Q7, and the emitter of the sixth transistor Q6 is grounded;

the seventh transistor Q7 is an NPN-type transistor, a collector of the seventh transistor Q7 is used for obtaining the bias current, and an emitter of the seventh transistor Q7 is grounded;

one end of the capacitor 320 is connected to the collector of the sixth transistor Q6, and the other end is connected to the emitter of the sixth transistor Q6;

the eighth transistor 330 is an NPN-type transistor, a collector of the eighth transistor 330 is used for obtaining the bias current and for outputting the operating signal, a base of the eighth transistor 330 is connected to a collector of the sixth transistor Q6, and an emitter of the eighth transistor 330 is connected to an emitter of the sixth transistor Q6.

In this embodiment, the load state detection circuit 10 outputs a low level signal as an operating signal to drive the power output circuit 20 to be turned on.

The operation principle of the load status detection circuit 10 is understood with reference to fig. 4 and 5, in fig. 4 and 5, VO (voltage), i.e., the voltage at the point VO in fig. 3, is also the voltage at the output terminal of the power supply module 200; a (voltage), which is the voltage at point a in fig. 3, is also the voltage at the first terminal of the first resistor 210; b (voltage), which is the voltage at point B in fig. 3, is also the voltage at the second end of the first resistor 210; c (voltage), which is the voltage at point C in fig. 3, is also the voltage at the collector of the second transistor Q2; d (voltage), which is the voltage at point D in fig. 3, is also the voltage of the capacitor 320; START (voltage), i.e. the voltage at START point in fig. 3, is also the voltage at the output of the signal module 300.

Referring to the second stage of fig. 4 or fig. 5, when the load 30 is no load, the output terminal VO of the power supply module 200 is in a high impedance state, the current I2 flowing through the first resistor 210 is 0, that is, the voltage difference between the two ends of the first resistor 210 is 0, the voltage difference between the base and the emitter of the second transistor Q2 is also 0, so the second transistor Q2 is turned off, thereby further causing the current I3 flowing into the capacitor 320 to be 0, the voltage of the capacitor 320 is always 0, the eighth transistor 330 is turned off, the signal at the output terminal START is at a high level, that is, the load detection circuit 10 does not output a working signal.

Referring to the first stage of fig. 4 or fig. 5- "when there is a load at the output end", when the load 30 is in a normal operating state, the output end VO of the power supply module 200 supplies power to the load, the current I2 flowing through the first resistor 210 generates a voltage across the first resistor 210, the second transistor Q2 is turned on, the voltage at the point C is stabilized at 2.1V, the seventh transistor Q7 is turned on, the sixth transistor Q6 is turned off, the base current of the 5 th transistor Q5 charges the capacitor 320, after the preset time period, the voltage of the capacitor 320 is increased from 0V to 0.7V, the eighth transistor 330 is turned on, and the START signal is inverted from a high level to a low level, i.e., the operating signal is output. The first preset condition and the second preset condition mentioned in [ embodiment one ] are compared with the above-described operation signal output process, since the first resistor 210 has a current flowing therethrough, the "reference current is greater than 0A" is satisfied, since the external voltage must be greater than 0.7V during normal operation of the load 30, and the first transistor 220 is raised by 0.7V (in fact, the external voltage is much higher than 1.4V, and the raised voltage of the first transistor 220 can be ignored, which is described here in order to correspond to the subsequent short-circuit operation), the "reference voltage greater than 1.4V" is satisfied, in addition, since the voltage of the capacitor 320 is increased from 0V to 0.7V, it is required to wait for a period of time, the time is the preset time length, so that the two conditions meet the condition that the duration time exceeds the preset time length on the premise of meeting. The working state at this time is in agreement with the description in [ example one ]. When the power output circuit 20 is driven to be turned on by the operating signal, the power supply 50 outputs a voltage to supply power to the load 30, and since the output voltage of the constant voltage power supply module 100 is maintained at 1.5V higher than the operating voltage provided by the power output circuit 20, and the voltage output by the power supply module 200 is reduced by about 1.4V after passing through the second transistor Q2 and the first transistor 220, the voltage output by the power supply module is slightly higher than the output voltage of the power output circuit 20, even if the power output circuit 20 is turned on, the load state detection circuit 10 still supplies power to the load through VO, that is, I2 always exists, the operating state of the load detection circuit 10 does not change, so that the START signal is always at a low level, and the power output circuit 20 continues to operate after being turned on.

Referring to the third stage of fig. 4 or 5, when the output terminal is short-circuited, the equivalent resistance of the load 30 is relatively small when the output terminal is short-circuited, and the voltage finally applied to the load 30 is pulled down to be less than 0.7V due to the limited output current of the power output circuit 20, so that the voltage of the output terminal VO of the power supply module 200 is also less than 0.7V, and the voltage of the VO is less than 0.7V at the node B and 0.7V at the node B, i.e. the voltage of the node a is less than 0.7+0.7+0.7, i.e. less than 2.1V, due to the presence of the first transistor 220 and the second transistor Q2, and the voltage at the node C is less than 2.1V. At this time, the voltage at the point C is less than 0.7V after passing through the third transistor Q3 and the fourth transistor Q4, the seventh transistor Q7 cannot be turned on, and the collector of the seventh transistor Q7 is at a high potential, so that the sixth transistor Q6 is turned on, the charge of the capacitor 320 is guided to the ground by the sixth transistor Q6, and the voltage of the capacitor 320 is reduced to 0V. Since the charging current of the capacitor 320 is the base current of the fifth transistor, and the discharging current is a normal current, the discharging current is much larger than the charging current. Therefore, in the current state, the voltage of the capacitor 320 is always maintained at 0V, and thus, the eighth transistor 330 cannot be turned on, the START voltage is at a high level, and at this time, the load detection circuit 10 does not output an operation signal.

Please refer to the fourth stage in fig. 4- "the output terminal is connected to the constant voltage load, when the short circuit state is removed", if the load 30 is the constant voltage load, after the short circuit state of the load 30 is removed, the voltage of the output terminal VO of the power supply module 200 returns to above 0.7V, and after the delay of the preset time duration, the power output circuit 20 is turned on again and maintains the on state.

Please refer to the fourth stage in fig. 5- "the output terminal is connected to a constant current or constant resistance load, and when the short circuit state is removed", if the load 30 is a constant current or constant resistance load, after the short circuit state of the load 30 is removed, the voltage of the output terminal VO of the power supply module 200 cannot return to above 0.7V, and the power output circuit 20 cannot be automatically restarted, which has a certain limitation.

The load state detection circuit 10 shown in this embodiment, although having a certain limitation, when connecting the constant voltage load, has solved among the prior art problem that the power chip can't satisfy the three demands of reducing the energy consumption under the no-load state simultaneously, protecting itself under the short-circuit condition and independently starting when the short-circuit state is got rid of, still has advantages such as simple structure, power consumption are lower simultaneously.

[ EXAMPLE III ]

Referring to fig. 6 to 8, fig. 6 is a circuit schematic diagram of a load status detection circuit according to a third embodiment of the present invention; fig. 7 is a waveform diagram of the load state detection circuit according to the third embodiment of the present invention when the load state detection circuit is connected to a constant current load or a constant resistance load; fig. 8 is a partially enlarged schematic view of a portion a in fig. 7.

As shown in fig. 6, the present embodiment provides a load state detection circuit 10, which is different from the load state detection circuit 10 in [ embodiment two ] as follows:

the load state detection circuit 10 further includes a timing module 400, the timing module 400 further includes a timing power supply module 410 and an automatic reset timer 420, the timing power supply module 410 is configured to provide electric energy required by operation for the automatic reset timer 420, an enable end of the automatic reset timer 420 is connected to the second output end of the signal module 300, and an output end of the timing module 400 is connected to the third input end of the signal module 300;

the signal module 300 is configured to send an enable signal to the timing module 400 through a second output terminal thereof when the reference voltage does not satisfy the second preset condition, and output the working signal with a first preset pulse width through a first output terminal thereof when a third input terminal thereof receives a trigger signal that the automatic reset timer 420 sends a second preset pulse width and the reference voltage does not satisfy the second preset condition;

the auto-reset timer 420 is configured to periodically send the trigger signal of the second preset pulse width to the signal module 300 when receiving the enable signal sent by the signal module 300.

Referring to fig. 6, the timing power supply module 410 includes a constant voltage source, which provides a constant voltage of V1 to the auto-reset timer 420, so as to ensure that the auto-reset timer 420 can work normally when receiving the trigger signal.

The elements and the connection relationship of the rest of the present embodiment are understood with reference to the relevant portions of [ embodiment two ], or with reference to fig. 6.

It should be understood that, in the present embodiment, when the reference current does not satisfy the first preset condition, the second output terminal of the signal module 300 also sends an enable signal to the timing module 400, however, this is not an essential feature for achieving the object of the present invention, and the above characteristics are only provided in this embodiment by simplifying the circuit and reasonably utilizing the prior art, and it may also be designed that when the reference current does not satisfy the first preset condition, the second output terminal of the signal module 300 does not send an enable signal to the timing module 400. Whether the second output terminal of the signal module 300 sends an enable signal to the timing module 400 when the reference current does not satisfy the first preset condition should be considered as the protection scope of the claims of the present application.

Referring to fig. 7 and 8, in fig. 7, VO (voltage), i.e., the voltage at the point VO in fig. 6, is also the voltage at the output terminal of the power supply module 200; a (voltage), which is the voltage at point a in fig. 6, is also the voltage at the first terminal of the first resistor 210; b (voltage), which is the voltage at point B in fig. 6, is also the voltage at the second end of the first resistor 210; c (voltage), which is a voltage at a point C in fig. 6, is also a voltage of the collector of the second transistor Q2; d (voltage), which is the voltage at point C in fig. 6, is also the voltage of the capacitor 320; IN (voltage), i.e., the voltage at the point IN fig. 6, is also the voltage at the enable terminal of the automatic reset timer 420, OUT (voltage), i.e., the voltage at the point OUT IN fig. 6, is also the voltage at the output terminal of the automatic reset timer 420; START (voltage), i.e. the voltage at START point in fig. 6, is also the voltage at the output of the signal module 300.

When the load 30 is IN an unloaded or short-circuit state, the voltage at point C is lower than 2.1V, which causes the transistor Q21 to turn off, the transistor Q23 to turn on, the input IN of the automatic reset timer 420 detects a low level signal, the automatic reset timer 420 starts to operate, and the output OUT of the automatic reset timer 420 outputs a high level pulse with a duration t3 at intervals of a fixed duration t2, wherein the durations represented by t2 and t3 can be understood with reference to fig. 8, and t3 is the second preset pulse width. When the output OUT of the automatic reset timer 420 is at a high level, the transistor Q22 is turned on, and the sixth transistor Q6 is turned off. It should be discussed in two cases, the first case is that when the state of the load 30 is no load, please refer to [ embodiment two ] related parts, the base of the fifth transistor Q5 has no current, although the sixth transistor Q6 is turned off, the capacitor 320 is not charged, and therefore the state of the subsequent circuit is not changed; in the second case, when the load 30 is in a short circuit state, a current exists at the base of the fifth transistor Q5, and the current can charge the capacitor 320, referring to fig. 8, after a time period t1 elapses, the voltage of the capacitor 320 reaches the turn-on voltage of the eighth transistor 330, and the eighth transistor 330 is turned on, wherein the time period t1 can be understood with reference to fig. 8, and t1 is the preset time period. Finally, the START level is inverted to the low level, the power output circuit 20 is turned on, the operation time period is t3-t1= t4, and the time period represented by t4 can be understood with reference to fig. 8, while t4 is the first preset pulse width. If the short circuit state of the load 30 is not removed, the power output circuit 20 stops working after a time period t4, and because t4 is narrow, the working time of the power output circuit 20 is short, the consumed energy is small, and the power supply chip and the system are not adversely affected; if the short-circuit state of the load 30 is removed, no matter whether the load 30 is a resistive load or a constant-current load, because the output power of the power output circuit 20 is relatively high, the voltage of the output terminal VO of the power supply module can be increased to be higher than 0.7V within a time period of t4, at this time, the seventh transistor Q7 is turned on, the turn-off state of the sixth transistor Q6 does not change with the disappearance of the high level of the output terminal OUT of the automatic reset timer 420, so that the signal module 300 can continuously output the low level, and the power output circuit 20 is in the continuous turn-on state, thereby realizing the self-starting function of the power chip after the short-circuit state of the load 30 is cancelled.

The working logic of the load 30 connected to the present embodiment is a constant voltage load, and the working logic of the present embodiment when the load 30 is no-load can be understood by referring to the description of the relevant part [ embodiment two ], and will not be described in detail herein.

It should be understood that the internal circuit of the timing module 400 and the connection relationship with the signal module 300 can be implemented as the circuit in fig. 6, and can also be implemented according to other schemes, for example, the automatic reset timer 420 is configured to periodically output a low level signal of the first pulse width when receiving the enable signal sent by the signal module 300, the collector of the eighth transistor 330 and the output of the automatic reset timer 420 output the working signal through an and circuit, and for example, the timing module 400 can be configured such that when receiving the enable signal sent by the signal module 300, the timing power supply module 410 supplies power to the automatic reset timer 420 (i.e., does not supply power for the rest of time) to further reduce the circuit power consumption. So configured, similar effects may also be achieved, and should also be considered as the scope of protection of the claims of the present application.

The load state detection circuit 10 shown in this embodiment, when connecting any form of load, solves the problem that the power chip in the prior art cannot simultaneously meet the three requirements of reducing energy consumption in an idle state, protecting itself in a short circuit condition, and automatically starting when the short circuit condition is removed.

In summary, in the load status detection circuit 10 and the power chip provided in the present invention, the load status detection circuit 10 includes a constant voltage source module 100, a power supply module 200, and a signal module 300, wherein a first input end and a second input end of the signal module 300 are respectively connected to a first end and a second end of a first resistor of the power supply module, and the power output circuit 20 is driven to be turned on by determining a current working status of the load 30 according to a current flowing through the first resistor 210 and a voltage at the second end. The configuration enables the power chip to be capable of closing the power chip under the no-load state to reduce energy consumption to the maximum extent, closing the power chip under the short-circuit condition to protect the power chip from being damaged by short-circuit current, and being capable of automatically starting when the short-circuit state of the load is removed, so that the three requirements that the power chip can not simultaneously meet the requirements of reducing energy consumption under the no-load state, protecting the power chip under the short-circuit condition and automatically starting when the short-circuit state is removed in the prior art are solved.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A load state detection circuit is characterized by comprising a constant voltage source module, a power supply module and a signal module,

the first input end of the signal module is connected with the first end of the first resistor, the second input end of the signal module is connected with the second end of the first resistor, and the signal module is configured such that when the reference current flowing through the first resistor meets a first preset condition and the reference voltage obtained by the second input end of the signal module meets a second preset condition, the first output end of the signal module outputs a working signal to drive the power output circuit to be turned on and supply power to the load; when the reference current does not meet a first preset condition, the first output end of the signal module does not output the working signal to drive the power output circuit to be closed and stop supplying power to the load; when the reference voltage does not meet a second preset condition, the first output end of the signal module does not output the working signal to drive the power output circuit to be closed and stop supplying power to the load or periodically outputs the working signal with a first preset pulse width to drive the power output circuit to be automatically started when the short-circuit state of the load is removed;

when the reference current does not meet the first preset condition, judging that the current load state is no-load; and when the reference voltage does not meet the second preset condition, judging that the current load state is a short circuit.

2. The load condition detection circuit according to claim 1, wherein the first predetermined condition comprises the reference current being greater than 0A and the duration exceeding a predetermined duration.

3. The load condition detection circuit according to claim 2, wherein the second predetermined condition comprises the reference voltage being greater than 1.4V and the duration exceeding the predetermined duration.

4. The load condition detection circuit according to claim 3, wherein the signal module comprises a charge and discharge submodule and a capacitor;

5. The load condition detecting circuit according to claim 4, wherein the constant voltage source module is further configured to provide a bias current, the charge/discharge submodule includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a second resistor, a third resistor, and a fourth resistor, and the signal module further includes an eighth transistor;

6. The load condition detection circuit according to claim 1, further comprising a timing module, wherein an enable terminal of the timing module is connected to the second output terminal of the signal module, and an output terminal of the timing module is connected to the third input terminal of the signal module;

7. The load condition detection circuit according to claim 1, wherein the constant voltage source module comprises a constant current source, a current mirror and a voltage regulating resistor interface, the voltage regulating resistor interface is used for being connected with an external voltage regulating resistor, the constant current source is connected with an input end of the current mirror, and the voltage regulating resistor is connected with an output end of the current mirror;

8. The load condition detection circuit according to claim 1, wherein the voltage output by the constant voltage source module is greater than the operating voltage provided by the power output circuit, and the difference is in a range of 1.45V to 1.55V.

9. A power supply chip, wherein the power supply chip comprises the load status detection circuit and the power output circuit according to any one of claims 1 to 8, the load status detection circuit and the power output circuit are powered by the same power supply, the first output terminal of the signal module is connected to the enable terminal of the power output circuit, the power supply output terminal of the power output circuit is connected to a load, and the power output circuit is configured to turn on and supply power to the load when the enable terminal of the power output circuit receives the working signal; otherwise, closing.