CN112071344A - Circuit for improving linearity and consistency of calculation in memory - Google Patents
Circuit for improving linearity and consistency of calculation in memory Download PDFInfo
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- CN112071344A CN112071344A CN202010910710.3A CN202010910710A CN112071344A CN 112071344 A CN112071344 A CN 112071344A CN 202010910710 A CN202010910710 A CN 202010910710A CN 112071344 A CN112071344 A CN 112071344A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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Abstract
The invention discloses a circuit for improving the calculation linearity and consistency in a memory, which comprises a 6T SRAM storage array with double word lines, a word line control module, a mode selection module, a time sequence control module, a pre-charging module, a current mirror module, a switch module and a buffer module, wherein the 6T SRAM storage array is respectively connected with the pre-charging module, the word line control module and the buffer module; the time sequence control module is respectively connected with the pre-charging module, the switch module and the current mirror module; the current mirror module is connected with the buffer module; and clamping the voltage on the bit line BL by using the current mirror module, preventing the voltage on the bit line BL from reducing, mirroring the reading current of the unit, converting the reading current into voltage, and outputting the voltage as a final calculation result through the buffer module. The circuit can realize the in-memory calculation with high linearity and high consistency, thereby greatly improving the practicability of the in-memory calculation.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a circuit for improving the linearity and consistency of calculation in a memory.
Background
The traditional von neumann architecture separates a processor computing unit from a memory, and the access speed of the memory is seriously lagged behind the computing speed of the processor, so that the memory is called a 'storage wall'. The limitation of the Memory on the energy efficiency ratio also becomes a bottleneck of the traditional von neumann system computer, In order to overcome the defects brought by the traditional von neumann structure, In-Memory Computing (IMC) is provided, and the In-Memory Computing does not need to transmit data to a processor and directly carries out operation In the Memory, so that the data throughput is greatly improved, and the energy efficiency is optimized. However, with the development of the in-memory technology, how to improve the linearity and consistency of the in-memory calculation becomes a serious problem to be solved urgently.
The essential of the in-memory calculation is analog quantity operation, almost all the in-memory calculation based on the SRAM depends on the voltage of a bit line BL and a multi-row reading technology, but the in-memory calculation based on the analog voltage of the bit line BL has the problems of poor linearity and poor consistency, so that calculation errors are caused, the development of in-memory calculation is severely limited, and the problem of nonlinearity and inconsistency existing in the in-memory calculation based on the SRAM can be solved at the same time due to the lack of an effective method in the prior art.
Disclosure of Invention
The invention aims to provide a circuit for improving the linearity and consistency of in-memory calculation, which can realize the in-memory calculation with high linearity and high consistency, thereby greatly improving the practicability of in-memory calculation.
The purpose of the invention is realized by the following technical scheme:
a circuit for improving in-memory computational linearity and consistency, the circuit comprising a 6T SRAM memory array having dual wordlines, a wordline control module, a mode selection module, a timing control module, a precharge module, a current mirror module, a switch module, and a buffer module, wherein:
the 6T SRAM memory array is respectively connected with the pre-charging module, the word line control module and the buffer module;
the word line control module is respectively connected with the mode selection module and the time sequence control module;
the time sequence control module is respectively connected with the pre-charging module, the switch module and the current mirror module;
the current mirror module is connected with the buffer module;
in a current mirror mode calculated in a memory, the pre-charging module charges bit lines BL, and after pre-charging is finished, the switch module connects the current mirror module to each bit line BL;
the 6T SRAM storage array with the double word lines comprises two independent word lines WLL and WLR, wherein the word lines WLL are not enabled, and only the word lines WLR are enabled;
the word line control module generates pulse widths with pulse widths of 8:4:2:1 to act on different word lines WLR, and the word lines WLR control corresponding rows in the 6T SRAM storage array to be opened so as to read and calculate multiple rows;
and clamping the voltage on the bit line BL by using the current mirror module, preventing the voltage on the bit line BL from reducing, mirroring the total reading current on the bit line BL, converting the total reading current into voltage, and outputting the voltage as a final calculation result through the buffer module.
According to the technical scheme provided by the invention, the circuit can realize the in-memory calculation with high linearity and high consistency, so that the practicability of the in-memory calculation is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic diagram of a circuit structure for improving the linearity and consistency of in-memory computation according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a current mirror module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an operating waveform of a current mirror module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a process of reading four rows by the circuit according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of a circuit structure for improving the linearity and consistency of calculation in a memory according to an embodiment of the present invention, where the circuit mainly includes a 6T SRAM memory array having dual word lines, a word line control module, a mode selection module, a timing control module, a precharge module, a current mirror module, a switch module, and a buffer module, where:
the 6T SRAM memory array is respectively connected with the pre-charging module, the word line control module and the buffer module;
the word line control module is respectively connected with the mode selection module and the time sequence control module;
the time sequence control module is respectively connected with the pre-charging module, the switch module and the current mirror module;
the current mirror module is connected with the buffer module;
in a current mirror mode calculated in a memory, the pre-charging module charges bit lines BL, and after pre-charging is finished, the switch module connects the current mirror module to each bit line BL;
the 6T SRAM storage array with the double word lines comprises two independent word lines WLL and WLR, wherein the word lines WLL are not enabled, and only the word lines WLR are enabled; by using the double word line unit structure, the number of access transistors connected on a single word line can be reduced, the number of through holes and the parasitic capacitance of the through holes of the interconnected word lines in a layout are reduced, the aim of reducing Elmore delay is fulfilled, and the influence of word line pulse width distortion on the consistency of different column calculations is reduced;
the word line control module generates pulse widths with pulse widths of 8:4:2:1 to act on different word lines WLR, and the word lines WLR control corresponding rows in the 6T SRAM storage array to be opened so as to read and calculate multiple rows;
and clamping the voltage on the bit line BL by using the current mirror module, preventing the voltage on the bit line BL from reducing, mirroring the total reading current on the bit line BL, converting the total reading current into voltage, and outputting the voltage as a final calculation result through the buffer module.
Fig. 2 is a schematic structural diagram of a current mirror module according to an embodiment of the present invention, the current mirror module includes four PMOS transistors M1, M2, M3, and M4, and a capacitor C, wherein:
the grid electrodes of the PMOS transistors M1 and M2 are connected with each other and connected with a first grid voltage VG (gate voltage), and the source electrodes are connected with VDD;
the gates of the PMOS transistors M3 and M4 are connected in parallel to the second gate voltage VCM, and the sources are connected to the drains of the PMOS transistors M1 and M2, respectively;
the drain electrode of the PMOS transistor M4 is connected with VG, and the VG is connected with a bit line BL;
the drain of PMOS transistor M3 is connected to the upper plate of capacitor C as output Vout；
The lower polar plate of the capacitor C is grounded;
the current mirror module clamps the voltage on the bit line BL, so that the charging current of the current mirror module to the bit line BL is equal to the reading current of the bit line BL, the reading current is mirrored in proportion to charge the capacitor C in the current mirror module, and finally the voltage V of the upper electrode plate of the capacitor CoutAs a final calculation result.
Fig. 3 is a schematic diagram of an operating waveform of the current mirror module according to the embodiment of the present invention, and in the pre-charge stage: bit line BL is precharged to about VDD/2, VoutVCM/VG is connected to VDD; in the pre-read phase: VCM is connected to about VDD/2 voltage, VG is connected to bit line BL; a reading stage: the word line WLR is turned on, multi-row reading is started, the PMOS transistors M2 and M4 are turned on, VDD charges the BL through the PMOS transistors M2 and M4, the voltage on the bit line BL is clamped, and the voltage of the bit line BL hardly drops because the charging current of the VDD-M2-M4 on the bit line BL is equal to the discharging current of the cell; meanwhile, M1-M3 proportionally mirrors the current of the bit line BL, and the mirrored current is collected by the capacitor C, and finally the voltage V of the upper plate of the capacitor CoutRepresenting the final calculation.
The current mirror module enables the voltage on the bit line BL to be always kept at a high level, so that the access transistor always works in a saturation region, and the working current linearity of the transistor in the saturation region is high; the voltage on the bit line BL is clamped, so that internal storage data can be protected from being overturned, and reading damage is eliminated; meanwhile, the influence of clamping current and leakage current provided by other units in the same column on the reading current is eliminated, so that the reading current of the unit is not interfered by other factors, and the linearity of calculation of each column is greatly improved.
In a specific implementation, as shown in fig. 4, which is a schematic diagram of a process of reading four rows by the circuit according to the embodiment of the present invention, WLR1, WLR2, WLR3, and WLR4 respectively represent four rows of word lines, and corresponding pulse widths T1, T2, T3, and T4 have pulse width ratios of 8:4:2:1, which respectively represent different weights, and the voltage on the bit line BL is clamped by the current mirror module, and pulse widths of word line signals having pulse widths of 8:4:2:1 are all enlarged and enhanced, and are respectively 5 times of pulse widths in a conventional mode. The pulse width is enlarged, the proportion of a distorted signal in an effective signal is reduced, and therefore the influence of word line pulse width distortion on the consistency of different column calculations is further reduced.
In addition, different from the traditional mode that pulse widths with different weights are opened at the same time, in the embodiment of the invention, the starting time of the word line signal with the pulse width of 8:4:2:1 is different, and the word line pulse with the low weight lags behind the pulse with the high weight, so that the influence of different column calculation consistency caused by the distortion of the pulse width signal with the low weight is reduced.
It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.
In summary, in the circuit structure according to the embodiment of the present invention, the 6T SRAM memory array having dual word lines is used to complete data storage and access, the word line pulse width distortion effect is reduced by reducing the number of via holes on the word lines, the linearity is improved by using the current mirror auxiliary circuit, the word line pulse width is enhanced by expansion, and the influence of the distortion signal on the effective signal is further reduced; by setting the start times of the pulse widths with different weights to be different, the pulse width with low weight lags behind the pulse width with high weight, the distortion of the pulse width signal with low weight is reduced.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A circuit for improving in-memory computational linearity and consistency, the circuit comprising a 6T SRAM memory array having dual wordlines, a wordline control module, a mode selection module, a timing control module, a precharge module, a current mirror module, a switch module, and a buffer module, wherein:
the 6T SRAM memory array is respectively connected with the pre-charging module, the word line control module and the buffer module;
the word line control module is respectively connected with the mode selection module and the time sequence control module;
the time sequence control module is respectively connected with the pre-charging module, the switch module and the current mirror module;
the current mirror module is connected with the buffer module;
in a current mirror mode calculated in a memory, the pre-charging module charges bit lines BL, and after pre-charging is finished, the switch module connects the current mirror module to each bit line BL;
the 6T SRAM storage array with the double word lines comprises two independent word lines WLL and WLR, wherein the word lines WLL are not enabled, and only the word lines WLR are enabled;
the word line control module generates pulse widths with pulse widths of 8:4:2:1 to act on different word lines WLR, and the word lines WLR control corresponding rows in the 6T SRAM storage array to be opened so as to read and calculate multiple rows;
and clamping the voltage on the bit line BL by using the current mirror module, preventing the voltage on the bit line BL from reducing, mirroring the total reading current on the bit line BL, converting the total reading current into voltage, and outputting the voltage as a final calculation result through the buffer module.
2. The circuit of claim 1, wherein the current mirror module comprises four PMOS transistors M1, M2, M3, and M4, and a capacitor C, wherein:
the grid electrodes of the PMOS transistors M1 and M2 are connected and connected with a first grid voltage VG, and the source electrodes are connected with VDD;
the gates of the PMOS transistors M3 and M4 are connected in parallel to the second gate voltage VCM, and the sources are connected to the drains of the PMOS transistors M1 and M2, respectively;
the drain electrode of the PMOS transistor M4 is connected with VG, and the VG is connected with a bit line BL;
the drain of PMOS transistor M3 is connected to the upper plate of capacitor C as output Vout；
The lower polar plate of the capacitor C is grounded;
the current mirror module clamps the voltage on the bit line BL, so that the charging current of the current mirror module to the bit line BL is equal to the reading current of the bit line BL, the reading current is mirrored in proportion to charge the capacitor C in the current mirror module, and finally the voltage V of the upper electrode plate of the capacitor CoutAs a final calculation result.
3. The circuit of claim 1, wherein the current mirror module clamps the voltage on the bit line BL, and the pulse widths of the word line signals with pulse widths of 8:4:2:1 are increased to 5 times the pulse widths in the conventional mode.
4. The circuit of claim 1, wherein the word line signals with pulse widths of 8:4:2:1 start at different times, and the low weight word line pulses lag the high weight pulses, thereby reducing the effect of the distortion of the low weight pulse width signals on the consistency of the computation of different columns.
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Cited By (5)
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| CN112558922A (en) * | 2021-02-20 | 2021-03-26 | 中科院微电子研究所南京智能技术研究院 | Four-transistor memory computing device based on separated word lines |
| CN113628645A (en) * | 2021-08-16 | 2021-11-09 | 长鑫存储技术有限公司 | Memory array circuit, memory array layout and verification method |
| TWI814376B (en) * | 2022-02-16 | 2023-09-01 | 美商桑迪士克科技有限責任公司 | Semiconductor current mirror circuits and semiconductor apparatus |
| EP4307304A3 (en) * | 2022-05-25 | 2024-04-17 | STMicroelectronics International N.V. | Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram) |
| EP4307303A3 (en) * | 2022-05-25 | 2024-04-24 | STMicroelectronics International N.V. | Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram) |
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| EP4307303A3 (en) * | 2022-05-25 | 2024-04-24 | STMicroelectronics International N.V. | Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram) |
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