CN112069115B - Data transmission method, equipment and system - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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Abstract
The embodiment of the invention provides a data transmission method, equipment and a system. The method comprises the following steps: the slave equipment receives data request information of a transaction sent by the master equipment; the data request information includes at least: a start address and a data length L; wherein, L represents: l +1 data units are to be transmitted; the slave device calculates an address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous; and the slave equipment executes transmission operation on the corresponding data unit according to the calculated address. Therefore, one data request does not need to be split into a plurality of requests, and discontinuous address increment can be realized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a data transmission method, device, and system.
Background
With the development of Chip technology, the demand for large high-performance chips is increasing, and SoC (System-on-Chip) chips are also the most important product development mode in the industry. A typical SoC chip system mainly includes: an on-chip interconnect bus, a master device, and a slave device. The master device and the slave device are mainly connected through an interface.
The interfaces where the master device, the slave device and the on-chip interconnection bus are connected have corresponding bus protocols, and the currently widely used bus protocol in the industry is the axi (advanced eXtensible interface) protocol.
In the AXI protocol, a read request or a write request may be referred to as a transaction data request. A data request of a transaction may include multiple data units, each referred to as a transfer.
There are 3 burst transmission mechanisms in the AXI protocol, including 3 mechanisms of FIXED, INCR, WRAP, and the INCR mechanism is most widely used.
The INCR mechanism includes: the addresses of each transfer in a transaction are successively incremented, wherein the address of the first transfer is AXADDR (start address) and the addresses of subsequent transfers are incremented based on the address of the preceding transfer until the last transfer is complete.
The inventor finds that with the development of ai (intellectual intelligence) technology and the demand for high-performance and diversified bus transmission, there are increasing demands for non-continuous incremental increase of addresses during data transmission. Based on the current AXI protocol, only one transaction data request can be split into a plurality of transaction requests. That is, assuming that one transaction data request includes 16 data units, if address non-continuous increment is required, the transaction data request needs to be split into 16 transaction data requests.
The above processing method will increase the resource consumption of the read address channel and the write address channel. Still following the previous example, if a transaction data request is split into 16 transaction data requests, then the bus protocol signal for sending the 15transaction data requests needs to be added; meanwhile, the number of times of arbitration is increased in the whole on-chip bus transmission (because not only one master device but also a plurality of master devices initiating data requests need arbitration, and if a data request is split into 16 data requests, the number of times of arbitration is increased), which affects the integrity of the requested data and the response efficiency.
Disclosure of Invention
In view of this, embodiments of the present invention provide a data transmission method, device and system to achieve discontinuous address increment without increasing resource consumption and arbitration times.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a method of data transmission, comprising:
the slave equipment receives data request information of a transaction sent by the master equipment; the data request information at least includes: a start address and a data length L; wherein L represents: l +1 data units are to be transmitted;
the slave device calculates an address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous increment mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
and the slave equipment executes transmission operation on the corresponding data unit according to the calculated address.
Optionally, the data request information further includes: discontinuous incremental information; the address discontinuous increment mode comprises an address discontinuous increment formula; the slave device calculates an address corresponding to each data unit based on the starting address and the bit width of the data unit according to a preset address discontinuous increment mode, and the method comprises the following steps: and the slave equipment calculates the address corresponding to each data unit based on the initial address, the bit width of the data unit and the discontinuous incremental information according to a preset address discontinuous incremental formula.
Optionally, the discontinuous increment information includes: length stepping information Len _ stride and Offset address information stride _ Offset _ Addr; the address discontinuous increment formula comprises:
address _ N ═ Start _ Address + ((N-1) × Number _ Bytes) + (INT ((N-1)/Len _ Stripe) × Stripe _ Offset _ Address _ Number _ Bytes); or, Address _ N ═ Start _ Address + ((N-1) Number _ Bytes) + (INT ((N-1)/Len _ Stripe) Stripe _ Offset _ Address); n is more than or equal to 1 and less than or equal to Burst _ Length, and Address _ N represents the Address of the Nth data unit; burst _ Length ═ L + 1; number _ Bytes represents the bit width of the data unit; start Address characterizes the Start Address.
Optionally, if the transaction is a read transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an arbiter signal of the AXI protocol; if the transaction is a write transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an AWUSER signal of the AXI protocol.
Optionally, the bit width of the signal cause and the signal cause are X bits, where a bit is used to transmit the Len _ Strip, and X-a bit is used to transmit the Strip _ Offset _ Addr; a is greater than or equal to 1 and less than X.
Optionally, the discontinuous increment information includes Offset address information Stripe _ Offset _ Addr; the address discontinuous increment formula comprises:
adress _ M ═ Adress _ M-1+ Number _ Bytes + Stripe _ Offset _ Addr; alternatively, the first and second electrodes may be,
adress _ M ═ Adress _ M-1+ Number _ Bytes + Stripe _ Offset _ Addr × Number _ Bytes; wherein, Number _ Bytes represents the bit width of the data unit; adress _ M-1 represents the address of the M-1 th data unit, and Adress _ M represents the address of the M-th data unit; m is more than or equal to 2 and less than or equal to Burst _ Length; the address of the first data unit is the starting address; burst _ Length ═ L + 1.
Optionally, the data request information further includes: and indication information indicating whether address discontinuous increment is carried out.
A data transmission device as a slave device in a data transmission system, comprising:
a receiving unit configured to: receiving data request information of a transaction sent by a master device; the data request information at least includes: a start address and a data length L; wherein L represents: l +1 data units are to be transmitted;
a computing unit to: calculating the address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
a first transmission unit to: and executing transmission operation on the corresponding data unit according to the calculated address.
A data transmission device as a master device in a data transmission system, comprising:
the data request information sending unit is used for sending data request information of one transaction to the slave equipment; the data request information at least includes: a start address and a data length L; wherein L represents: l +1 data units are to be transmitted; the starting address and the data length L are used for the slave device to calculate the address corresponding to each data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous; the transaction is a read transaction or a write transaction;
a second transmission unit configured to:
receiving L +1 data units which are read and returned by the slave device according to the calculated address; alternatively, the first and second electrodes may be,
and sending L +1 data units to the slave device, writing the sent L +1 data units into the calculated corresponding addresses by the slave device, and receiving write return information sent by the slave device.
A data transmission system comprising at least one master device and at least one slave device, the master device being configured to: sending data request information of a transaction; the data request information at least includes: a start address and a data length L; wherein L represents: l +1 data units are to be transmitted;
the slave device is to: calculating the address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
and executing transmission operation on the corresponding data unit according to the calculated address.
It can be seen that, in this embodiment, after receiving a data request of a transaction, the slave device may calculate an address of each to-be-transmitted data unit in the transaction according to a preset non-consecutive address increment manner, where addresses between some or all data units and adjacent units are not consecutive. Therefore, one transaction data request does not need to be split into a plurality of transaction requests, and discontinuous address increment can be realized.
The problem of increasing resource consumption and arbitration times in the existing processing mode is avoided.
Drawings
Fig. 1 is an exemplary structure of a data transmission system provided by an embodiment of the present invention;
fig. 2 is an operation process involved in a read request based on the AXI protocol according to an embodiment of the present invention;
fig. 3 is an operation process involved in a write request based on the AXI protocol according to an embodiment of the present invention;
fig. 4 is an exemplary flow of a data transmission method provided by an embodiment of the present invention;
fig. 5 is another exemplary flow chart of a data transmission method according to an embodiment of the present invention;
fig. 6a is an exemplary structure of a data transmission device as a slave device according to an embodiment of the present invention;
fig. 6b is an exemplary structure of a data transmission device as a master device according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a data transmission method, equipment and a system.
The data transmission system may be specifically an SoC chip system, please refer to fig. 1, and may include: an on-chip interconnect bus, at least one master device, and at least one slave device.
The master device and the slave device are the data transmission device claimed by the invention.
It should be noted that fig. 1 exemplarily shows 3 master devices (master devices 0-2) and 3 slave devices (slave devices 0-2), and in fact, those skilled in the art can flexibly design the number of master devices and slave devices according to the needs.
The interfaces where the master device, the slave device and the on-chip interconnection bus are connected have corresponding bus protocols, and the currently widely used bus protocol in the industry is the axi (advanced eXtensible interface) protocol.
The AXI protocol is a high performance, high bandwidth, low latency oriented bus standard.
The AXI protocol includes 5 channels: the device comprises a read address channel, a read data channel, a write address channel, a write data channel and a write response channel, wherein the read address channel and the read data channel are used for transmitting read data, and the write address channel, the write data channel and the write response channel are used for transmitting write data.
Fig. 2 shows the operational procedures involved in a read request based on the AXI protocol: the master device sends address and control information to the slave device through the master device interface read address channel, and the slave device returns corresponding read data through the read data channel.
Fig. 3 shows the operational procedure involved in a write request based on the AXI protocol: as shown in fig. 3, the master device sends address and control information to the slave device through the write address channel, and at the same time, the master device sends corresponding write data to the slave device through the write data channel, and after the slave device receives the data of the write address channel and the write data channel, the slave device sends a write return (representing that the slave device has accepted and completed the write operation) to the master device through the write response channel.
The master device interface in fig. 2 and 3 is a master device interface connected to the on-chip interconnection bus interface, and the slave device interface is a slave device interface connected to the on-chip interconnection bus interface.
Of course, when there are multiple masters, arbitration is required if the multiple masters simultaneously make read or write requests.
Currently, the mainstream and most widely used in the industry are AXI3 and AXI4 bus protocols, and the bus protocol signals involved in the two protocols in five channels are shown in table 1.
Since the two protocols are international standard protocols, the corresponding signal meanings are not described in detail herein, and only signals associated with the present application are selected in the following description for detailed description.
It should be noted that the following description refers to an expression of AX, and the description applies to both AR (read address channel) and AW (write address channel).
TABLE 1
In the AXI protocol, a read request or a write request may be referred to as a transaction data request. A data request of a transaction may include multiple data units, each referred to as a transfer.
A read request or a write request is subsequently denoted herein by transaction, unless specifically stated otherwise.
There are 3 burst transmission mechanisms in the AXI protocol, including 3 mechanisms of FIXED, INCR, WRAP, and the INCR mechanism is most widely used.
The INCR mechanism includes: the addresses of each transfer in a transaction are successively incremented, wherein the address of the first transfer is AXADDR (start address) and the addresses of subsequent transfers are incremented based on the address of the preceding transfer until the last transfer is complete.
With the development of ai (intellectual intelligence) technology and the demand for high-performance and diversified bus transmission, there are increasing demands for non-continuous incremental increase of addresses during data transmission. Based on the current AXI protocol, only one transaction data request can be split into a plurality of transaction requests. That is, assuming that one transaction data request includes 16 data units, if address non-continuous increment is required, the transaction data request needs to be split into 16 transaction data requests.
The above processing method will increase the resource consumption of the read address channel and the write address channel. Still following the previous example, if a transaction data request is split into 16 transaction data requests, then the bus protocol signal for sending the 15transaction data requests needs to be added; meanwhile, the number of times of arbitration is increased in the whole on-chip bus transmission (because not only one master device but also a plurality of master devices initiating data requests need arbitration, and if a data request is split into 16 data requests, the number of times of arbitration is increased), which affects the integrity of the requested data and the response efficiency.
The AXI protocol is the most widely used data transmission protocol at present, and most of ip (intelligent performance) units in the SoC chip are designed based on the AXI interface protocol, so on the premise of keeping using the AXI protocol, the embodiment of the invention improves and optimizes the INCR operation in the AXI protocol, so as to realize non-continuous increment of the address without increasing the resource consumption and arbitration times.
To achieve the above object, referring to fig. 4, the data transmission method executed by the SOC system may exemplarily include the following steps:
s1: the master device sends data request information of a transaction to the slave device.
The transaction may be a read transaction or a write transaction. The content of the data request information includes at least: a Start Address (indicated as Start Address) and a data length (indicated as L).
Specifically, the Start _ Address represents an Address represented by the 1 st transfer in the current transfer, and the value of the Address is AXADDR in the AXI protocol.
The data request information is transmitted through a read address channel or a write address channel. If the transaction is a read transaction, the value of Start _ Address is the value in the ARADDR signal transmitted by the read Address channel; if it is a write transaction, the value of Start _ Address is the value in the AWADDR signal transmitted by the write Address channel.
The data length L represents that L +1 data units are to be transmitted, or represents a data transmission length of a transaction.
In the AXI3 protocol, the length of data transmission supported by the INCR operation is 16 at most; in AXI4, the length of data transmission supported by the INCR operation is 256 at the maximum.
"L + 1" may also be denoted by Burst _ Length. If the transaction is a read transaction, the value of L is the value in an ARLEN signal transmitted by a read address channel; if the transaction is a write transaction, the value of L is the value in the AWLEN signal transmitted by the write address channel.
In an example, the data request information may further include indication information for indicating whether to perform non-consecutive address incrementing. When the non-sequential increment of the address is instructed, S2 and S3 are executed subsequently. And when the non-continuous increment of the address is indicated, the method can be processed according to the existing mode. In this way, scenarios may be accommodated that do not require non-sequential increments of addresses.
S2: and the slave device calculates the address corresponding to each data unit (transfer) according to a preset address discontinuous increment mode and based on the initial address and the bit width of the data unit.
The data bit width of each transfer in the current transfer can be characterized by using Number _ Bytes, and the expression range of decimal is 1, 2, 4, 8, 16, 32, 64 and 128.
The following description will describe a non-sequential increment manner of addresses different from each transfer address, which can be realized by using different manners: among the Burst _ Length (L +1) data units, addresses between some or all of the data units and adjacent data units are not consecutive.
S3: and the slave equipment executes transmission operation on the corresponding data unit according to the calculated address of each transfer.
In one example, the current transfer belonging to the next transfer within the current transfer may be characterized by N. The decimal representation of N ranges from 1 to 256. The maximum value of N of the current transaction is the value of Burst _ Length. Meanwhile, Address _ N may be used to represent the Address corresponding to the nth transfer in the current transfer.
After the Address _ N is calculated, if the transaction is a write transaction, the slave device may write the nth transfer received from the write data channel into the Address _ N, and send a write back to the master device through the write response channel.
If the transaction is a read transaction, the slave device can read the nth transfer from the Address _ N and return the nth transfer through the read data channel.
It can be seen that, in this embodiment, after receiving a data request of a transaction, the slave device may calculate an address of each to-be-transmitted data unit in the transaction according to a preset non-consecutive address increment manner, where addresses between some or all data units and adjacent units are not consecutive. Therefore, one transaction data request does not need to be split into a plurality of transaction requests, and discontinuous address increment can be realized.
The problem of increasing resource consumption and arbitration times in the existing processing mode is avoided.
The address non-sequential increment manner may comprise an address non-sequential increment formula. Fig. 5 shows an exemplary flow of a data transmission method based on the address discontinuous increment formula, which includes:
s51: the master device sends data request information of a transaction to the slave device.
In this embodiment, the data request information may include discontinuous increment information in addition to the Start Address Start _ Address and the data length L.
In one example, the non-consecutive incremental information may further include the following new incremental information:
length stepping information, denoted Len _ Stripe; the decimal expression of Len _ Stripe ranges from 0 to 255. Exemplary may be 1, 2, 4, 8, 16, 32, 64, 128, etc.
Offset address information, expressed in Stripe _ Offset _ Addr, whose decimal expression ranges from 0 to 255.
In one example, Len _ Stripe and Stripe _ Offset _ Addr may be carried by the AXUSER signal.
The AXUSER is a user-defined signal and can be opened for users to use.
More specifically, if the transaction is a read transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an ARUSER signal of the AXI protocol; if the transaction is a write transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an AWUSER signal of the AXI protocol.
The ARUSER and AWUSER signals are X bits wide, and the X length can be determined by the length sum of Len _ Stripe and Stripe _ Offset _ Addr. For example, X may be 4 bits in the AXI3 protocol and 8 bits in the AXI4 protocol.
Among the X bits, a bits (e.g., front a bits or rear a bits) can be used to transmit Len _ Strip, and X-a bits (e.g., rear X-a bits or front X-a bits) can be used to transmit Strip _ Offset _ Addr. a is greater than or equal to 1 and less than X. The length of a depends on the length of Len _ Stripe, and may be, for example, 2 bits, 4 bits, and so on.
And the slave equipment obtains the new information by analyzing the corresponding ARUSER and AWUSER.
S52: and substituting the values of the initial address, the bit width, the length stepping information and the offset address information of the data unit into an address discontinuous incremental formula to obtain the address corresponding to each data unit (transfer).
In one example, the address non-sequential increment formula may be:
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr*Number_Bytes)；
alternatively, the first and second electrodes may be,
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr).
n is more than or equal to 1 and less than or equal to Burst _ Length, and Address _ N represents the Address of the Nth data unit; burst _ Length ═ L + 1;
number _ Bytes represents the bit width of the data unit;
start Address characterizes the Start Address.
S53: and the slave equipment executes transmission operation on the corresponding data unit according to the calculated address of each transfer.
S53 is the same as S3, and is not repeated here.
In other embodiments of the present invention, the discontinuous increment information may include the Offset address information Stripe _ Offset _ Addr, and the address corresponding to each data unit (transfer) may be calculated by using other address discontinuous increment formulas.
For example, it is calculated using the following formula:
Adress_M＝Adress_M-1+Number_Bytes+Stripe_Offset_Addr；
alternatively, the first and second electrodes may be,
Adress_M＝Adress_M-1+Number_Bytes+Stripe_Offset_Addr*Number_Bytes。
wherein Adress _ M-1 represents the address of the M-1 th data unit, Adress _ M represents the address of the Mth data unit, and the address of the first data unit is the starting address.
M is more than or equal to 2 and less than or equal to Burst _ Length.
In one example, the Stripe _ Offset _ Addr may be carried by an AXUSER signal. More specifically, if the transaction is a read transaction, the Stripe _ Offset _ Addr is transmitted through an ARUSER signal of the AXI protocol; if the transaction is a write transaction, the Stripe _ Offset _ Addr is transmitted through an AWUSER signal of the AXI protocol.
The data transmission apparatus is described below.
Fig. 6a shows an exemplary structure of a data transmission device as a slave device, including:
the receiving unit 1 is used for receiving data request information of one transaction sent by a master device;
the data request information at least includes: a start address and a data length L; wherein, L represents: l +1 data units are to be transmitted;
the transaction is a write transaction or a read transaction.
A calculation unit 2 for:
calculating the address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode;
among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
a first transmission unit 3 for: and executing transmission operation on the corresponding data unit according to the calculated address.
For a related introduction, please refer to the above description, which is not repeated herein.
Fig. 6b shows an exemplary structure of a data transmission device as a master device, including:
a data request information sending unit 4, for sending data request information of a transaction to the slave device; the data request information includes at least: a start address and a data length L;
a second transmission unit 5 configured to:
receiving L +1 data units which are read and returned by the slave device according to the calculated address; alternatively, the first and second electrodes may be,
and sending L +1 data units to the slave device, writing the sent L +1 data units into the corresponding calculated addresses by the slave device, and receiving write return information sent by the slave device.
In another embodiment of the present invention, the data request information may further include: discontinuous increment information, and the discontinuous increment mode of the address comprises a discontinuous increment formula of the address.
In the aspect that the slave device calculates an address corresponding to each data unit based on the start address and the bit width of the data unit according to a preset address discontinuous increment manner, the calculating unit 2 is specifically configured to:
and calculating the address corresponding to each data unit based on the initial address, the bit width of the data unit and the discontinuous incremental information according to a preset address discontinuous incremental formula.
In one example, the non-consecutive increment information may include: length stepping information Len _ stride and Offset address information stride _ Offset _ Addr;
accordingly, the address non-sequential increment formula may include:
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr*Number_Bytes)；
alternatively, the first and second electrodes may be,
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr)
n is more than or equal to 1 and less than or equal to Burst _ Length, and Address _ N represents the Address of the Nth data unit; burst _ Length ═ L + 1; number _ Bytes represents the bit width of the data unit; start Address characterizes the Start Address.
For a related introduction, please refer to the above description, which is not repeated herein.
Specifically, if the transaction is a read transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an ARUSER signal of the AXI protocol; if the transaction is a write transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an AWUSER signal of the AXI protocol.
Optionally, the bit width of the signal cause and the signal cause are X bits, where a bit is used to transmit Len _ Strip, and X-a bit is used to transmit Strip _ Offset _ Addr.
For a related introduction, please refer to the above description, which is not repeated herein.
In another embodiment of the present invention, the discontinuous increment information may include: offset address information Stripe _ Offset _ Addr;
the address discontinuous increment formula can comprise:
Adress_M＝Adress_M-1+Number_Bytes+Stripe_Offset_Addr；
alternatively, the first and second electrodes may be,
adress _ M ═ Adress _ M-1+ Number _ Bytes + Stripe _ Offset _ Addr × Number _ Bytes; wherein, Number _ Bytes represents the bit width of the data unit; adress _ M-1 represents the address of the M-1 th data unit, and Adress _ M represents the address of the Mth data unit. M is more than or equal to 2 and less than or equal to Burst _ Length.
The address of the first data unit is the aforementioned starting address.
For a related introduction, please refer to the above description, which is not repeated herein.
In another embodiment of the present invention, the data request information may further include: and indication information indicating whether address discontinuous increment is carried out.
Those of skill would further appreciate that the various illustrative components and model steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or model described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, WD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method of data transmission, comprising:
the slave equipment receives data request information of a transaction sent by the master equipment; the data request information at least includes: the data processing method comprises the steps of starting address, data length L and discontinuous increment information, wherein the discontinuous increment information comprises length stepping information Len _ Stripe and Offset address information Stripe _ Offset _ Addr; wherein L represents: l +1 data units are to be transmitted;
the slave device calculates an address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous increment mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
the slave device executes transmission operation on the corresponding data unit according to the calculated address;
the address discontinuous increment mode comprises an address discontinuous increment formula, and the slave device calculates the address corresponding to each data unit according to a preset address discontinuous increment mode and based on the starting address and the bit width of the data unit, wherein the address discontinuous increment mode comprises:
and the slave equipment calculates the address corresponding to each data unit based on the initial address, the bit width of the data unit and the discontinuous incremental information according to a preset address discontinuous incremental formula.
2. The method of claim 1,
the address discontinuous increment formula comprises:
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr*Number_Bytes)；
alternatively, the first and second electrodes may be,
Address_N＝Start_Address+((N-1)*Number_Bytes)+(INT((N-1)/Len_stripe)*Stripe_Offset_Addr)；
n is more than or equal to 1 and less than or equal to Burst _ Length, and Address _ N represents the Address of the Nth data unit; burst _ Length ═ L + 1;
number _ Bytes represents the bit width of the data unit;
start Address characterizes the Start Address.
3. The method of claim 1,
if the transaction is a read transaction, transmitting Len _ Stripe and Stripe _ Offset _ Addr through an ARUSER signal of an AXI protocol;
if the transaction is a write transaction, Len _ Stripe and Stripe _ Offset _ Addr are transmitted through an AWUSER signal of the AXI protocol.
4. The method of claim 3,
the bit width of the ARUSER signal and the AWUSER signal is X bits, wherein a bits are used for transmitting the Len _ Strip, and X-a bits are used for transmitting the Stripe _ Offset _ Addr; a is greater than or equal to 1 and less than X.
5. The method of claim 1,
the discontinuous increment information comprises Offset address information Stripe _ Offset _ Addr;
the address discontinuous increment formula comprises:
Adress_M＝Adress_M-1+Number_Bytes+Stripe_Offset_Addr；
alternatively, the first and second electrodes may be,
Adress_M＝
Adress_M-1+Number_Bytes+Stripe_Offset_Addr*Number_Bytes；
wherein, Number _ Bytes represents the bit width of the data unit; adress _ M-1 represents the address of the M-1 th data unit, and Adress _ M represents the address of the M-th data unit; m is more than or equal to 2 and less than or equal to Burst _ Length; the address of the first data unit is the starting address; burst _ Length ═ L + 1.
6. The method of claim 1, wherein the data request information further comprises: and indication information indicating whether address discontinuous increment is carried out.
7. A data transmission device, as a slave device in a data transmission system, comprising:
a receiving unit configured to: receiving data request information of a transaction sent by a master device; the data request information at least includes: the data processing method comprises the steps of starting address, data length L and discontinuous increment information, wherein the discontinuous increment information comprises length stepping information Len _ Stripe and Offset address information Stripe _ Offset _ Addr; wherein L represents: l +1 data units are to be transmitted;
a computing unit to: calculating the address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
a first transmission unit to: according to the calculated address, executing transmission operation on the corresponding data unit;
wherein the address discontinuous increment mode includes an address discontinuous increment formula, and the calculation unit is specifically configured to:
and the slave equipment calculates the address corresponding to each data unit based on the initial address, the bit width of the data unit and the discontinuous incremental information according to a preset address discontinuous incremental formula.
8. A data transmission device, as a master device in a data transmission system, comprising:
the data request information sending unit is used for sending data request information of one transaction to the slave equipment; the data request information at least includes: the data processing method comprises the steps of starting address, data length L and discontinuous increment information, wherein the discontinuous increment information comprises length stepping information Len _ Stripe and Offset address information Stripe _ Offset _ Addr; wherein L represents: l +1 data units are to be transmitted; the starting address and the data length L are used for the slave device to calculate the address corresponding to each data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous; the transaction is a read transaction or a write transaction;
a second transmission unit configured to:
receiving L +1 data units which are read and returned by the slave device according to the calculated address; alternatively, the first and second electrodes may be,
sending L +1 data units to the slave device, writing the sent L +1 data units into the calculated corresponding addresses by the slave device, and receiving write return information sent by the slave device;
the address discontinuous increment mode includes an address discontinuous increment formula, and the starting address and the data length L are used by the slave device to calculate an address corresponding to each data unit according to a preset address discontinuous increment mode, which specifically includes:
the starting address and the data length L are used for the slave device to calculate the address corresponding to each data unit according to a preset address discontinuous increment formula.
9. A data transmission system comprising at least one master device and at least one slave device, characterized in that:
the master device is configured to: sending data request information of a transaction; the data request information at least includes: the data processing method comprises the steps of starting address, data length L and discontinuous increment information, wherein the discontinuous increment information comprises length stepping information Len _ Stripe and Offset address information Stripe _ Offset _ Addr; wherein L represents: l +1 data units are to be transmitted;
the slave device is to: calculating the address corresponding to each data unit based on the initial address and the bit width of the data unit according to a preset address discontinuous incremental mode; among the L +1 data units, the addresses between part or all of the data units and the adjacent data units are discontinuous;
according to the calculated address, executing transmission operation on the corresponding data unit;
wherein the address discontinuous increment mode includes an address discontinuous increment formula, and the slave device is specifically configured to:
and the slave equipment calculates the address corresponding to each data unit based on the initial address, the bit width of the data unit and the discontinuous incremental information according to a preset address discontinuous incremental formula.
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