CN112068965A - Data processing method and device, electronic equipment and readable storage medium - Google Patents
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- 238000003672 processing method Methods 0.000 title claims abstract description 34
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- 239000000872 buffer Substances 0.000 claims abstract description 88
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- 238000004422 calculation algorithm Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
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- 230000008878 coupling Effects 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- 230000006835 compression Effects 0.000 description 1
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- 238000004590 computer program Methods 0.000 description 1
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- 238000001914 filtration Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012464 large buffer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
The application discloses a data processing method, a data processing device, electronic equipment and a readable storage medium, and belongs to the technical field of data processing. The method is applied to an electronic device, the electronic device comprises a plurality of processors, and the method comprises the following steps: acquiring a frame to be distributed and acquiring the frame processing efficiency corresponding to each processor at the current moment; determining, by a plurality of the processors, a target processor based on a frame processing efficiency of each of the processors; and distributing the frame to be distributed to a buffer area corresponding to the target processor. The frame to be distributed can be distributed to the buffer areas corresponding to the processors in a balanced mode by obtaining the frame processing efficiency corresponding to each processor.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a data processing method and apparatus, an electronic device, and a readable storage medium.
Background
With the requirement of the electronic equipment for data processing, the electronic equipment is provided with other processing devices in addition to the original processor for data processing, so that the processor and the other processing devices can cooperatively perform data processing. However, in the method of processing the data by the processor in cooperation with other processing devices, there is a problem that the throughput rate is yet to be improved.
Disclosure of Invention
The application provides a data processing method, a data processing device, an electronic device and a readable storage medium, so as to overcome the defects.
In a first aspect, an embodiment of the present application provides a data processing method, which is applied to an electronic device, where the electronic device includes multiple processors, and the method includes: acquiring data to be distributed and acquiring data processing efficiency corresponding to each processor at the current moment; determining, by a plurality of the processors, a target processor based on the data processing efficiency of each of the processors; and distributing the data to be distributed to a buffer area corresponding to the target processor.
In a second aspect, an embodiment of the present application further provides a data processing apparatus, which is applied to an electronic device, where the electronic device includes a plurality of processors, and the apparatus includes: the device comprises an acquisition module, a determination module and a distribution module. The acquisition module is used for acquiring data to be distributed and acquiring data processing efficiency corresponding to each processor at the current moment. And the determining module is used for determining a target processor by the plurality of processors according to the data processing efficiency of each processor. And the distribution module is used for distributing the data to be distributed to the buffer area corresponding to the target processor.
In a third aspect, an embodiment of the present application further provides an electronic device, including one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the above-described methods.
In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, and the program code can be called by a processor to execute the above method.
According to the data processing method and device, the electronic device and the readable storage medium, the electronic device comprises a plurality of processors, the data to be distributed and the data processing efficiency corresponding to each processor at the current moment are firstly obtained, then the target processor is determined by the plurality of processors according to the data processing efficiency of each processor, and finally the data to be distributed are distributed to the buffer area corresponding to the target processor. According to the data processing method and device, the data to be distributed can be distributed to the buffer areas corresponding to the target processors in a balanced mode by obtaining the data processing efficiency corresponding to each processor, the computing power of electronic equipment hardware can be fully utilized to a certain extent, and therefore the throughput rate of data processing is improved.
Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating a first conventional load sharing method;
fig. 2 is a schematic diagram illustrating a second conventional load sharing method;
FIG. 3 illustrates a method flow diagram of a data processing method provided by an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating how long it takes for each processor to process data within a time period in the data processing method according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a number of frames processed by each processor in a time period in a data processing method according to an embodiment of the present application;
FIG. 6 is a method flow diagram of a data processing method according to another embodiment of the present application;
FIG. 7 is a flow chart illustrating additional steps in a data processing method provided by another embodiment of the present application;
fig. 8 is a schematic diagram illustrating a process of allocating data to be allocated in a data processing method according to another embodiment of the present application;
FIG. 9 illustrates a method flow diagram of a data processing method provided by yet another embodiment of the present application;
FIG. 10 is a block diagram of a data processing apparatus provided by an embodiment of the present application;
fig. 11 shows a block diagram of an electronic device provided in an embodiment of the present application;
fig. 12 illustrates a storage unit provided in an embodiment of the present application and used for storing or carrying program codes for implementing a data processing method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
A Central ProceSSing Unit (CPU) is a final execution unit for information proceSSing and program operation, and serves as an operation and control core in the electronic device. As the functions of electronic devices become more and more abundant, the amount of data to be processed also becomes larger and larger, so that other processing devices are also configured in the electronic devices to perform data processing in cooperation with the processor. For example, a Digital Signal ProceSSor (DSP) and a Graphics ProceSSing Unit (GPU) are introduced to solve the problem, and image ProceSSing using a dedicated chip such as the DSP and the GPU is a major measure for improving image ProceSSing efficiency and power consumption of electronic devices in the current electronic devices. Some image algorithms originally running on the CPU are developed into a calculation form of a GPU or a DSP to share part of calculation power, so that the purposes of improving the program running performance and reducing the CPU load are achieved.
The first mode is a computing power transfer mode, which mainly directly develops an algorithm function into a GPU or DSP mode for calculation so as to reduce the calculation of the CPU, and the first mode is shown in figure 1. although the CPU calls the DSP or GPU to perform data calculation, the load of the GPU can be reduced, namely the computing power of the CPU is transferred to the GPU or the DSP, the CPU is in an idle state during the calculation of the DSP/GPU, namely the first mode cannot repeatedly use the system computing power. For example, in DSP computing, it is possible that the GPU is in an idle state, or the GPU does not need to be completely idle, and partial computing power may be provided. The second mode is a serial pipeline mode, which mainly divides an algorithm of certain data into several processing processes which can be serial and respectively put on different computing units CPU, GPU or DSP to execute so as to achieve a pipeline working model, thereby improving the throughput rate of data processing, and the second mode is as shown in FIG. 2. As can be seen from fig. 2, the algorithm of a certain frame may be separately placed on the CPU, the GPU and the DSP for execution, although the second method simultaneously uses the computing power of each computing unit of the CPU, the GPU and the DSP, due to the characteristics of pipeline operation, the job2 of the same frame may wait for the job1 to be executed again after the job1 is finished, which may result in a partial idle period in the middle of the computing unit that runs faster, for example, there is a vacancy between the job2 and the job2 in fig. 2, that is, the computing power of the computing unit in this method may not be fully used, and when the second method is used, the algorithm must be pipelined split, different parts are implemented by different hardware, and the development difficulty is high.
Therefore, in order to solve the above problem, embodiments of the present application provide a data processing method. Referring to fig. 3, a data processing method according to an embodiment of the present application is shown. The data processing method is applied to electronic equipment, the electronic equipment comprises a plurality of processors, and in a specific embodiment, the data processing method comprises the following steps: step S301 to step S303.
Step S301: and acquiring data to be distributed and acquiring the data processing efficiency corresponding to each processor at the current moment.
In the embodiment of the application, the data to be distributed may be image frames, that is, one data to be distributed may represent one image frame, and the electronic device may obtain a plurality of data to be distributed, and then configure the plurality of data to be distributed on the plurality of processors respectively according to a preset rule. In some embodiments, after obtaining the data to be allocated, the method may determine whether a plurality of processors exist in the electronic device, and if only one processor exists in the electronic device, directly allocate the data to be allocated to a buffer area of the processor, in this process, the electronic device may first determine whether the number of the data to be processed in the buffer area of the processor is smaller than a preset number, and if the number of the data to be allocated is smaller than the preset number, directly allocate the data to be allocated to the buffer area corresponding to the processor; if the number of the data to be processed is larger than the preset number, continuously detecting whether the number of the data to be processed is smaller than the preset number or not, and distributing the data to be distributed to a buffer area corresponding to the processor until the number of the data to be processed is smaller than the preset number. As another mode, the electronic device may also determine whether the space of the buffer corresponding to the processor is greater than a space threshold, if so, allocate the data to be allocated to the buffer corresponding to the processor, and if so, keep a waiting state until the space of the buffer corresponding to the processor is greater than the space threshold, and allocate the data to be allocated to the buffer corresponding to the processor.
In other embodiments, if a plurality of processors exist in the electronic device, the present application may obtain data processing efficiency corresponding to each processor at the current time, where the plurality of processors may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a digital signal processing unit (DSP), and the Central Processing Unit (CPU) is a final execution unit for information processing and program operation, as an operation and control core in the electronic device; a Graphic Processor (GPU) is a microprocessor which is dedicated to perform image and graphic related operations on personal computers, workstations, game machines and some mobile devices (e.g., tablet computers, smart phones, etc.), and is mainly used for rendering and drawing display contents, the GPU reduces the dependence of a graphics card on a CPU (central processing unit) and performs part of the work of the CPU, especially when 3D graphics are processed, the core technologies adopted by the GPU include hardware T & L (geometric transformation and illumination processing), cubic environment texture mapping and vertex mixing, texture compression and concave-convex mapping, a dual-texture four-pixel 256-bit rendering engine, and the like; digital Signal Processors (DSPs) are processors consisting of large or very large scale integrated circuit chips that perform digital signal processing tasks, primarily for measuring, filtering or compressing continuous real analog signals. The Graphic Processing Unit (GPU) and the Digital Signal Processor (DSP) are used for processing tasks distributed by the Central Processing Unit (CPU), the data processing burden of the central processing unit can be reduced to a certain extent, and the data to be distributed to the Central Processing Unit (CPU), the Graphic Processing Unit (GPU) and the Digital Signal Processor (DSP) through reasonable distribution can not only improve the data processing efficiency, but also improve the throughput rate of data processing.
Illustratively, a frame image is taken as an example. The electronic device may obtain the image frame to be allocated and the frame processing efficiency corresponding to each processor at the current time, and due to the influences of the functions and hardware performance of different processors, the frame processing efficiencies corresponding to different processors are different, that is, the time consumed by different processors to process the same frame of image is different, as shown in fig. 4. As can be seen from fig. 4, it takes 30ms for a Central Processing Unit (CPU) to process one frame of image, 20ms for a Graphics Processing Unit (GPU) to process one frame of image, and 15ms for a digital signal processing unit (DSP) to process one frame of image. Thus, a Central Processing Unit (CPU) can process 2 frame images, a Graphic Processing Unit (GPU) can process 3 frame images, and a digital signal processing unit (DSP) can process 4 frame images in one 60ms period. To understand more clearly the case that multiple processors process image frames within a time period, the present application provides an exemplary diagram as shown in fig. 5, from fig. 5, the CPU can process 2 frames of images within a time period, the GPU can process 3 frames of images within a time period, and the DSP can process 4 frames of images within a time period, so that the electronic device can process 9 frames of images in total within a time period, that is, theoretically, the maximum throughput of the electronic device within a time period is 9 frames.
In this embodiment of the application, the data processing efficiency may be the amount of data to be processed stored in the buffer corresponding to the processor at the current time, may also be a ratio between the amount of data to be processed corresponding to each processor in a preset time period and the preset time period, or may also be a ratio between the amount of data to be processed in the buffer corresponding to each processor and a reference value, where the reference value may be a ratio between the amount of data to be processed in the buffer corresponding to the processor and the preset time period. After the data processing efficiency corresponding to each processor is obtained, according to the data processing efficiency of each processor, the present application may determine a target processor by a plurality of processors, that is, enter step S302.
Step S302: determining, by a plurality of the processors, a target processor based on the data processing efficiency of each of the processors.
In some embodiments, after the electronic device obtains the data processing efficiency of each processor, the target processor may be determined by multiple processors, that is, after the electronic device obtains the frame to be allocated, it may determine to which processor the data to be allocated is allocated according to the data processing efficiency of each processor at the current time. As one way, after determining the target processor, the electronic device may allocate the data to be allocated to the buffer corresponding to the target processor by using a dynamic policy allocation hybrid calculation policy, that is, enter step S303.
In other embodiments, when the target processor is determined by multiple processors according to the data processing efficiency of each processor, it may be determined whether the data processing efficiency of each processor is the same, if not, the data processing efficiency of each processor is sorted, and the processor with the smallest data processing efficiency is taken as the target processor. In addition, if the data processing efficiency of the processors is the same, the method and the device can acquire the size of each processor buffer area and take the processor with the large buffer area as a target processor. For example, the data processing efficiency of the graphics processor and the digital signal processor is less than that of the central processing unit, and the data processing efficiency of the graphics processor and the digital signal processor is the same, and the comparison shows that the buffer size a corresponding to the graphics processor is larger than the buffer size B corresponding to the digital signal processor, and then the graphics processor can be taken as the target processor.
Step S303: and distributing the data to be distributed to a buffer area corresponding to the target processor.
In some embodiments, after the electronic device determines the target processor by a plurality of processors according to the data processing efficiency of each processor, the application may allocate data to be allocated to a buffer corresponding to the target processor. In the process, the electronic device can configure a corresponding timestamp for the data to be distributed, and then output a processing result of the data to be distributed according to the timestamp, that is, when the electronic device distributes the data to be distributed to a buffer area corresponding to a target processor, the electronic device can construct a global output chain, the global output chain is used for representing an output sequence of the data, and when new data to be distributed is obtained, the application not only needs to distribute the data to be distributed to the buffer area of the corresponding processor, but also needs to place the data to be distributed to the tail end of the global output chain, so that the global output sequence can be recorded. Finally, the method and the device can output the data one by one according to the head of the global output chain, when the data at the head of the global output chain is not processed, the data need to wait until the data at the head is processed, the data are output, and the follow-up data are output one by one in the same way.
The data processing method provided by the embodiment of the application distributes the data to be distributed to the buffer area corresponding to the target processor in a balanced manner by acquiring the data processing efficiency corresponding to each processor at the current moment. According to the data processing method and device, the data to be distributed can be distributed to the buffer areas corresponding to the target processors in a balanced mode by obtaining the data processing efficiency corresponding to each processor, the computing power of electronic equipment hardware can be fully utilized to a certain extent, and therefore the throughput rate of data processing is improved.
Another embodiment of the present application provides a data processing method, which is applied to an electronic device, and the electronic device may include a plurality of processors. Referring to fig. 6, the data processing method may include steps S601 to S605.
Step S601: and acquiring data to be distributed.
Step S602: and respectively acquiring the quantity of the data to be processed stored in the buffer area corresponding to each processor at the current moment.
In this embodiment, the electronic device may respectively obtain the data amount of the to-be-processed data stored in the buffer corresponding to each processor at the current time, and use the data amount of the to-be-processed data as the data processing efficiency of the corresponding processor. Illustratively, N data are correspondingly arranged on a buffer area corresponding to the central processing unit at the current moment, and the data processing efficiency of the central processing unit can be N at the moment; the buffer area corresponding to the graphics processor at the current moment corresponds to M data, and the data processing efficiency of the graphics processor can be M at the moment; at the present moment, L data are correspondingly arranged on the buffer area corresponding to the digital signal processor, and the data processing efficiency of the digital signal processor can be L.
Step S603: and determining the data processing efficiency of each processor according to the quantity of the data to be processed of each processor.
Optionally, the application may use the number of the data to be processed of each processor as the data processing efficiency of each processor.
Step S604: determining, by a plurality of the processors, a target processor based on the data processing efficiency of each of the processors.
In some embodiments, after obtaining the data processing efficiency corresponding to each processor, the electronic device may determine, by the multiple processors, the target processor according to the data processing efficiency of each processor. Specifically, the electronic device may rank the plurality of data processing efficiencies, and use the processor with the smallest data processing efficiency as the target processor. For example, 2 pieces of data to be processed are stored in a buffer area corresponding to the central processing unit, where the buffer area is acquired by the electronic device at the current time, that is, the data processing efficiency corresponding to the central processing unit may be 2; the buffer area corresponding to the graphics processor stores 3 data to be processed, namely the data processing efficiency corresponding to the graphics processor can be 3; there are 4 data to be processed in the buffer area corresponding to the digital signal processor, that is, the data processing efficiency corresponding to the digital signal processor is 4. Through comparison, the data processing efficiency of the central processing unit is the minimum, that is, the data to be distributed can be distributed to the buffer area corresponding to the central processing unit.
In other embodiments, after the data processing efficiency corresponding to each processor is obtained, when the data processing efficiency of at least two processors is the same, the size of the buffer corresponding to each processor may be obtained, and the processor with the largest buffer may be used as the target processor. As another mode, when the data processing efficiency of at least two processors in the electronic device is the same, the applicant may obtain the average data processing efficiency of each processor in a preset time period, and use the processor with the minimum average data processing efficiency as the target processor.
Step S605: and distributing the data to be distributed to a buffer area corresponding to the target processor.
As one way, the data processing method as shown in fig. 7 may further include steps S606 to S607.
Step S606: and configuring a time stamp for the data to be distributed.
In this embodiment of the application, when the electronic device allocates the data to be allocated to the buffer corresponding to the target processor, a timestamp may be configured for the data to be allocated, and then a processing result of the data to be allocated is output according to the timestamp, that is, step S607 is performed. In some embodiments, after determining a target processor for the data to be distributed, the electronic device may configure a corresponding timestamp for the data to be distributed, and then output a processing result of the data to be distributed according to the timestamp.
In some embodiments, after the buffer of the processor finishes processing data, the data input sequence needs to be known to determine which data is output first, and if the data processed first is output immediately, the output sequence is disordered. Therefore, when the data to be distributed are distributed to the processors, the time stamps can be configured for the data to be distributed, and after each data to be distributed is distributed to the processors for processing, the data to be distributed needs to be output according to the time stamps. For example, data a to be allocated is allocated to the buffer of the cpu for processing at time T1, and data B to be allocated is allocated to the buffer of the gpu for processing at time T2, and time T1 is earlier than time T2, then the cpu outputs the processed data a first, and the gpu outputs the processed data B later. Through setting up this application like this not only can make full use of each treater, can guarantee the exactness of output order and the balance of output data frequency simultaneously.
In other embodiments, when the electronic device allocates data to be allocated to a buffer corresponding to a target processor, a global output chain may be constructed, where the global output chain is used to indicate an output order of the data, and when new data to be allocated is obtained, the application not only needs to allocate the data to be allocated to the buffer of the corresponding processor, but also needs to place the data to be allocated to a tail end of the global output chain, so that the global output order can be recorded. Finally, the method and the device can output the data one by one according to the head of the global output chain, when the data at the head of the global output chain is not processed, the data need to wait until the data at the head is processed, the data are output, and the follow-up data are output one by one in the same way.
Step S607: and outputting the processing result of the data to be distributed according to the time stamp.
In order to more clearly understand the output order of the data to be allocated, the present application provides a diagram as shown in fig. 8, and it can be seen from fig. 8 that after a plurality of data to be allocated are allocated to buffers corresponding to a plurality of processors according to a preset rule for processing, the output order of the data is output according to the data input order, that is, the input order of the data to be allocated and the output order of the processed data are corresponding to each other, and the present application can determine the output order of all the data to be allocated through a global output chain.
In addition, the sequence of the plurality of data to be processed in each buffer area in fig. 8 can be represented by a buffer frame chain, and the buffer frame chain is used for recording the processing sequence of each data to be processed in the buffer area. The global output chain and the buffer frame chain are realized through a linked list, each element is a pointer pointing to data to be processed, and when new data to be distributed needs to be processed, the head address of the new data to be distributed can be respectively inserted into the tail ends of the global output chain and the buffer frame chain. As can be known from fig. 8, when data to be allocated is allocated to a corresponding processor, the data to be allocated is allocated according to the data processing efficiency of the processor, so that the computing resources of the electronic device can be fully utilized in a balanced manner. Finally, the data output method and the data output device can output the processed data according to the sequence of the data, if the data are not processed completely, the data need to wait, and thus the data output is disordered.
It should be noted that, before obtaining the data processing efficiency corresponding to each processor at the current time, the present application may first obtain a data distribution time period, that is, determine whether the current time period is a target distribution time period according to the data distribution time period, obtain the data processing efficiency corresponding to each processor at the current time if the current time period is the target distribution time period, and then determine a target processor by the plurality of processors according to the data processing efficiency of each processor. And if the current period is not the target distribution period, distributing the acquired data to be distributed to the plurality of processors on average, wherein the target distribution period can be the middle period or the later period of data distribution, in other words, when the period for distributing the data is the early period, the acquired data to be distributed can be distributed to the plurality of processors on average. For example, the data allocation earlier stage acquires three image frame data, which are respectively an a image, a B image, and a C image, because in the data allocation earlier stage, the a image may be allocated to the buffer of the central processing unit, the B image may be allocated to the buffer of the graphics processing unit, and the C image may be allocated to the digital signal processing unit.
In other embodiments, the application may also allocate the data to be allocated to the buffer corresponding to the processor according to a ratio of data processing efficiency of each processor. For example, if the ratio of the data processing efficiency of the signal processor DSP to the data processing efficiency of the central processing unit CPU is 2:1, then the data to be allocated is allocated to the corresponding buffer according to 1:2, so that each processing of the electronic device can work at full capacity.
The data processing method provided by the embodiment of the application distributes the data to be distributed to the buffer area corresponding to the target processor in a balanced manner by acquiring the data processing efficiency corresponding to each processor at the current moment. According to the data processing method and device, the data to be distributed can be distributed to the buffer areas corresponding to the target processors in a balanced mode by obtaining the data processing efficiency corresponding to each processor, the computing power of electronic equipment hardware can be fully utilized to a certain extent, and therefore the throughput rate of data processing is improved. In addition, the method and the device can make full use of each processor, and can ensure the correctness of the output sequence and the balance of the output data frequency.
The application further provides a data processing method, which is applied to an electronic device, and the electronic device can comprise a plurality of processors. Referring to fig. 9, the data processing method may include steps S901 to S905.
Step S901: and acquiring data to be distributed.
Step S902: and acquiring the processing data volume of each processor in a preset time period.
In some embodiments, the processing data amount of each processor in the preset time period refers to the amount of data processed by each processor in different time periods, and the preset time period may be a preset time period before the current time. For example, the current time is 20:00, 9/2020, and the preset time period is 24 hours, then the preset time period is a time period from 20:00, 9/2020, 19/2020, to 20:00, 9/2020, 20/00. The preset time period may be in the unit of hour, or in the unit of days, or in the unit of seconds, etc., and how to set the preset time period is not specifically limited, and may be selected according to actual situations. The number of the data processed by the different processors in the preset time period may be the same or different, for example, the number of the processor data processed by the central processor in the preset time period is 2, and the number of the processor data processed by the graphics processor in the preset time period is 5.
Step S903: and determining the ratio of the processing data volume of each processor to the preset time period, and taking the ratio as the data processing efficiency corresponding to each processor.
As a mode, after the electronic device obtains the processing data amount of each processor within a preset time period, the application may determine a ratio of the processing data amount of each processor to the preset time period, and use the ratio as the data processing efficiency corresponding to each processor. For example, 30 frames of images are processed in the last 2 seconds by the central processing unit CPU, and the data processing efficiency corresponding to the central processing unit is 15 frames per second.
In other embodiments, the present application may respectively obtain the number of to-be-processed data stored in a buffer corresponding to each processor at the current time, then obtain the processing data amount of each processor in a preset time period, and determine a ratio of the processing data amount of each processor to the preset time period as a reference value. Finally, the data processing efficiency of each processor can be determined according to the number of the data to be processed of each processor and the reference value. Illustratively, the number of frames to be processed in the processing buffer area of the central processing unit CPU, the graphics processing unit GPU and the digital signal processing unit DSP at the current time is 2 frames, 3 frames and 5 frames, respectively, while the processing efficiencies of the central processing unit CPU, the graphics processing unit GPU and the digital signal processing unit DSP counted at the latest period of time are 20 frames/s, 30 frames/s and 70 frames/s, respectively, and the ratio of the number of data to be processed corresponding to each processor to the average processing efficiency is 0.1, 0.1 and 0.07 through calculation, that is, the time for processing one frame by the digital signal processing unit DSP is the shortest, and at this time, the data to be allocated can be allocated to the buffer area corresponding to the digital signal processing unit DSP. Therefore, the present application may use a ratio of the number of the to-be-processed data of each of the processors to the reference value as the data processing efficiency of each of the processors.
Step S904: determining, by a plurality of the processors, a target processor based on the data processing efficiency of each of the processors.
Step S905: and distributing the data to be distributed to a buffer area corresponding to the target processor.
In the embodiment of the application, when a data processing system corresponding to the electronic device is just started, a preset number of data to be distributed can be evenly distributed to the buffer area of each processor, after a preset time period, the electronic device can estimate the data processing efficiency of each processor, when a new data to be distributed is input, the electronic device can estimate how much time to process the data to be processed according to the data processing efficiency of each processor and how many data to be processed are waiting in the buffer area corresponding to the processor, and then can finish processing the data to be processed, so that the processor which can complete the task of the buffer area at first can be found, and the new data to be distributed is placed in the buffer queue of the processor. As a specific example, the average processing efficiency of the CPU is 20 frames per second, the average processing efficiency of the GPU is 30 frames per second, and the average processing efficiency corresponding to the DSP is 50 frames per second; the statistics shows that the buffer area of the CPU at the current moment has 2 frames of images to be processed, the buffer area of the GPU has 3 frames of images to be processed, and the buffer area of the DSP has 4 frames of images to be processed; it is calculated that the CPU can process the data in its buffer area within 2/20 ═ 0.1s, the GPU can process the data in its buffer area within 3/30 ═ 0.1s, and the DSP can process the data in its buffer area within 4/50 ═ 0.08 s.
The data processing method provided by the embodiment of the application distributes the data to be distributed to the buffer area corresponding to the target processor in a balanced manner by acquiring the data processing efficiency corresponding to each processor at the current moment. According to the data processing method and device, the data to be distributed can be distributed to the buffer areas corresponding to the target processors in a balanced mode by obtaining the data processing efficiency corresponding to each processor, the computing power of electronic equipment hardware can be fully utilized to a certain extent, and therefore the throughput rate of data processing is improved. In addition, the data processing method provided by the application can enable each processor in the electronic equipment to work at full load, so that the highest throughput rate is reached or approached.
Referring to fig. 10, an embodiment of the present application provides a data processing apparatus 800. In a specific embodiment, the data processing apparatus 800 includes: an acquisition module 801, a determination module 802, and an assignment module 803.
An obtaining module 801, configured to obtain data to be allocated and obtain data processing efficiency corresponding to each processor at a current time.
Further, the obtaining module 801 is further configured to respectively obtain the number of to-be-processed data stored in the buffer corresponding to each processor at the current time; and determining the data processing efficiency of each processor according to the quantity of the data to be processed of each processor.
Further, the obtaining module 801 is further configured to obtain a processing data amount of each processor in a preset time period; and determining the ratio of the processing data volume of each processor to the preset time period, and taking the ratio as the data processing efficiency corresponding to each processor.
Further, the obtaining module 801 is further configured to respectively obtain the number of to-be-processed data stored in the buffer corresponding to each processor at the current time; acquiring the processing data volume of each processor in a preset time period; determining a ratio of the processed data amount of each processor to the preset time period as a reference value; and determining the data processing efficiency of each processor according to the number of the data to be processed of each processor and the reference value.
Further, the obtaining module 801 is further configured to use a ratio of the number of the to-be-processed data of each of the processors to the reference value as the data processing efficiency of each of the processors.
A determining module 802, configured to determine a target processor by a plurality of the processors according to the data processing efficiency of each of the processors.
Further, the determining module 801 is further configured to rank the plurality of data processing efficiencies, and use the processor with the smallest data processing efficiency as the target processor.
An allocating module 803, configured to allocate the data to be allocated to the buffer corresponding to the target processor.
Further, the data processing apparatus 800 is further configured to configure a timestamp for the data to be allocated; and outputting the processing result of the data to be distributed according to the time stamp.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, the coupling between the modules may be electrical, mechanical or other type of coupling.
According to the data processing device provided by the embodiment of the application, the data to be distributed is evenly distributed to the buffer area corresponding to the target processor by using the acquisition module to acquire the data processing efficiency corresponding to each processor at the current moment, specifically, the data to be distributed and the data processing efficiency corresponding to each processor at the current moment are acquired by using the acquisition module, then the target processor is determined by using the plurality of processors according to the data processing efficiency of each processor by using the determination module, and finally the data to be distributed is distributed to the buffer area corresponding to the target processor by using the distribution module. According to the data processing method and device, the data to be distributed can be distributed to the buffer areas corresponding to the target processors in a balanced mode by obtaining the data processing efficiency corresponding to each processor, the computing power of electronic equipment hardware can be fully utilized to a certain extent, and therefore the throughput rate of data processing is improved.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
Referring to fig. 11, a block diagram of an electronic device 1000 according to an embodiment of the present disclosure is shown. The electronic device 1000 may be an electronic device capable of running an application, such as a smart phone, a tablet computer, and an electronic book. The electronic device 1000 in the present application may include one or more of the following components: a first processing component 1010, a first processing component 1020, a third processing component 1030, a memory 1040, a data output device 1050, and one or more applications, wherein the one or more applications may be stored in the memory 1040 and configured to be executed by the one or more first processing components 1010, second processing components 1020, or third processing component 1030, the one or more programs configured to perform a method as described in the aforementioned method embodiments.
The first processing device 1010 may include one or more processing cores. The first processing device 1010 connects various portions throughout the electronic apparatus 1000 using various interfaces and lines, and performs various functions of the electronic apparatus 1000 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 1040 and calling data stored in the memory 1040. Alternatively, the first ProceSSing device 1010 may be implemented in hardware using at least one of Digital Signal ProceSSing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The first ProceSSing device 1010 may integrate one or a combination of a Central ProceSSing Unit (CPU) and a modem for ProceSSing wireless communication. The CPU mainly processes an operating system, a user interface, an application program, and the like. The second ProceSSing device 1020 may be a Graphics ProceSSing Unit (GPU), and the second ProceSSing device 1020 is responsible for rendering and drawing of display content. It is understood that the modem may not be integrated into the first processing device 1010, but may be implemented by a communication chip, and the third processor may be a digital signal processor.
The Memory 1040 may include a Random AcceSS Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 1040 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 1040 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 1000 during use (e.g., phone book, audio-video data, chat log data), and the like.
In some embodiments, the electronic device 1000 further includes an information detection module configured to detect whether refresh information is obtained, where the refresh information indicates at least one of that the buffer is written with metadata or that the electronic device is abnormal.
In some embodiments, the electronic device 1000 further includes a data processing module, and the data processing module is configured to, if the refresh information is obtained, write the data in the buffer to the memory according to the refresh information.
The data output device is used for outputting local data. Optionally, the data output device may be a network device. The network device is used for receiving and transmitting electromagnetic waves, and realizing the interconversion between the electromagnetic waves and the electric signals, so as to communicate with a communication network or other equipment, such as audio playing equipment. The network device may include various existing circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption/decryption chip, a Subscriber Identity Module (SIM) card, memory, and so forth. The network device may communicate with various networks such as the internet, an intranet, a wireless network, or with other devices via a wireless network. The wireless network may comprise a cellular telephone network, a wireless local area network, or a metropolitan area network. For example, the network device may interact with the base station.
Referring to fig. 12, a block diagram of a computer-readable storage medium 2000 according to an embodiment of the present disclosure is shown. The computer-readable storage medium 2000 has stored therein program code that can be invoked by a processor to perform the methods described in the above-described method embodiments.
The computer-readable storage medium 2000 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 2000 includes a non-volatile computer-readable storage medium. The computer readable storage medium 2000 has storage space for program code 2010 to perform any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. Program code 2010 may be compressed, for example, in a suitable form.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. A data processing method applied to an electronic device, the electronic device including a plurality of processors, the method comprising:
acquiring data to be distributed and acquiring data processing efficiency corresponding to each processor at the current moment;
determining, by a plurality of the processors, a target processor based on the data processing efficiency of each of the processors;
and distributing the data to be distributed to a buffer area corresponding to the target processor.
2. The method of claim 1, wherein the obtaining the data processing efficiency corresponding to each of the processors at the current time comprises:
respectively acquiring the quantity of data to be processed stored in a buffer area corresponding to each processor at the current moment;
and determining the data processing efficiency of each processor according to the quantity of the data to be processed of each processor.
3. The method of claim 1, wherein the obtaining the data processing efficiency corresponding to each of the processors at the current time comprises:
acquiring the processing data volume of each processor in a preset time period;
and determining the ratio of the processing data volume of each processor to the preset time period, and taking the ratio as the data processing efficiency corresponding to each processor.
4. The method of claim 1, wherein the obtaining the data processing efficiency corresponding to each of the processors at the current time comprises:
respectively acquiring the quantity of data to be processed stored in a buffer area corresponding to each processor at the current moment;
acquiring the processing data volume of each processor in a preset time period;
determining a ratio of the processed data amount of each processor to the preset time period as a reference value;
and determining the data processing efficiency of each processor according to the number of the data to be processed of each processor and the reference value.
5. The method according to claim 4, wherein the determining the data processing efficiency of each processor according to the number of the data to be processed of each processor and the reference value comprises:
and taking the ratio of the number of the data to be processed of each processor to the reference value as the data processing efficiency of each processor.
6. The method of claim 1, wherein determining, by a plurality of the processors, a target processor based on the data processing efficiency of each processor comprises:
and sequencing the plurality of data processing efficiencies, and taking the processor with the minimum data processing efficiency as a target processor.
7. The method according to claim 1, further comprising, after the allocating the data to be allocated to the buffer corresponding to the target processor, the step of:
configuring a time stamp for the data to be distributed;
and outputting the processing result of the data to be distributed according to the time stamp.
8. The method of claim 1, wherein the processor comprises a central processing unit, a graphics processor, and a digital signal processor.
9. A data processing apparatus, applied to an electronic device including a plurality of processors, the apparatus comprising:
the acquisition module is used for acquiring data to be distributed and acquiring the data processing efficiency corresponding to each processor at the current moment;
a determining module for determining a target processor by a plurality of said processors based on the data processing efficiency of each said processor;
and the distribution module is used for distributing the data to be distributed to the buffer area corresponding to the target processor.
10. An electronic device, comprising:
one or more processors;
a memory;
one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-7.
11. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 7.
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