CN112054062B - SOI MOSFET device and preparation method thereof - Google Patents

SOI MOSFET device and preparation method thereof Download PDF

Info

Publication number
CN112054062B
CN112054062B CN202010893868.4A CN202010893868A CN112054062B CN 112054062 B CN112054062 B CN 112054062B CN 202010893868 A CN202010893868 A CN 202010893868A CN 112054062 B CN112054062 B CN 112054062B
Authority
CN
China
Prior art keywords
region
body contact
deep
isolation
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010893868.4A
Other languages
Chinese (zh)
Other versions
CN112054062A (en
Inventor
李多力
曾传滨
高林春
王家佳
罗家俊
韩郑生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN202010893868.4A priority Critical patent/CN112054062B/en
Publication of CN112054062A publication Critical patent/CN112054062A/en
Application granted granted Critical
Publication of CN112054062B publication Critical patent/CN112054062B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

The invention discloses an SOI MOSFET device and a preparation method thereof, wherein the device comprises: an active region and a gate electrode on the buried oxide layer; the partial isolation region is arranged at the edge of the active region and extends to two sides along the width direction of the grid electrode, and a partial active region is arranged between the partial isolation region and the oxygen-buried layer at intervals; the shallow slot isolation region is arranged at the outermost side of the device; the body contact region is arranged between the shallow slot isolation region and part of the isolation region, and a deep injection region is arranged from the bottom of the body contact region to the buried oxide layer and is connected with the body contact region and the active region. The device and the method provided by the invention are used for solving the technical problem of edge leakage of the SOI device in the prior art. The technical effect of improving the edge leakage of the SOI device is achieved.

Description

SOI MOSFET device and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to an SOI MOSFET device and a method of fabricating the same.
Background
In the modern CMOS process, the difference based on the substrate materials is mainly divided into two process technical schemes of bulk silicon and SOI, wherein the SOI technology has the advantages of eliminating parasitic latch-up effect, high speed, low noise, heat resistance, radiation resistance and the like compared with the bulk silicon technology due to the full dielectric isolation structure characteristics of devices, so that the SOI technology is widely adopted and becomes an important component of the CMOS process.
The conventional MOSFET device has a front trench isolation STI edge vertical parasitic FET structure at both ends due to the overlap of the active area edge and the gate strips. In SOI technology, the full dielectric isolation connects the STI to the buried oxide BOX, which makes the edge vertical parasitic MOS structure of the SOI device more complex, which is more prone to edge leakage than bulk silicon devices, especially under the total dose irradiation environment, positive charges accumulated in the STI and BOX oxide layers will invert the active region edge impurities to form a conductive channel, causing parasitic MOS structure leakage.
The edge leakage analysis of a conventional SOI device is shown in fig. 1. The vertical structure at the overlapping position of the grid and the edge of the active region can have a parasitic edge MOS structure, the parasitic structure takes the source drain of the main device as the source drain, and the field oxide layer as the gate medium. In the process of thermal heating, the STI and BOX oxide layers have obvious segregation effect on the well doped impurities (particularly P-well boron doping of NMOS devices), so that the impurity concentration at the interface between the active region and silicon dioxide is reduced, the opening threshold of the edge parasitic device is reduced, and an upper edge leakage channel is generated. In the included angle region formed by the STI isolation and the BOX, the segregation of the oxide layers from the side surface of the STI and the upper surface of the BOX can make the well concentration in the region lower, as shown in fig. 1 (b), the inversion threshold of the impurity is lower, and larger lower edge leakage is easy to generate under the effect of positive charge accumulation of the oxide, as shown in fig. 1 (c), which is a weak link of the leakage of the edge of the SOI device, and special measures need to be taken for suppression.
Disclosure of Invention
The present disclosure is directed, at least in part, to solving the technical problem of edge leakage in SOI devices in the prior art.
The embodiment of the disclosure provides the following technical scheme:
in a first aspect, there is provided an SOI MOSFET device comprising:
The active region and the grid electrode are positioned on the buried oxide layer, and an active region and a drain region are arranged in the active region;
The partial isolation region is arranged at the edge of the active region and extends to two sides along the width direction of the grid electrode, and a part of the active region is arranged between the partial isolation region and the oxygen burying layer at intervals;
The shallow slot isolation region is arranged at the outermost side of the device;
The body contact region is arranged between the shallow groove isolation region and the partial isolation region, a deep injection region is arranged from the bottom of the body contact region to the oxygen burying layer, and the deep injection region is connected with the body contact region and the active region; the doping types of the deep injection region, the body contact region and the active region are the same, and the doping types of the source region and the drain region are different from the doping type of the active region.
Optionally, the doping concentration of the deep implantation region and the doping concentration of the body contact region are both greater than the doping concentration of the active region.
Optionally, the thickness of the active region reserved between the partial isolation region and the buried oxide layer is greater than or equal to 50nm.
Optionally, the doping concentration of the deep implantation region is greater than 1e18/cm 3, and the doping concentration of the active region and the channel region of the device is greater than 1e17/cm 3.
Optionally, the deep injection region fills an included angle formed by the shallow trench isolation region and the oxygen-buried layer; the deep implant region does not extend beyond the portion of the isolation region to be spaced apart from the source region and the drain region.
In a second aspect, a method for fabricating an SOI MOSFET device is provided, comprising:
providing a substrate, wherein an oxygen burying layer is arranged on the substrate, and a semiconductor material layer is arranged on the oxygen burying layer;
Forming a shallow slot isolation region at the outermost side of a device and a part of isolation regions extending to two sides along the width direction of a grid electrode of the device on the semiconductor material layer, wherein the shallow slot isolation region extends downwards to be connected with the oxygen-buried layer, a part of the semiconductor material layer is arranged between the part of isolation regions and the oxygen-buried layer at intervals, and a part of the semiconductor material layer is arranged between the part of isolation regions and the shallow slot isolation regions at intervals;
Forming a source region, a drain region, a body contact region and a deep implantation region on the semiconductor material layer, wherein the body contact region is formed between the shallow trench isolation region and the partial isolation region, the deep implantation region extends from the bottom of the body contact region to the buried oxide layer, and the deep implantation region is connected with the body contact region and the active region of the device; the doping types of the deep injection region, the body contact region and the active region are the same, and the doping types of the source region and the drain region are different from the doping type of the active region;
And preparing a grid electrode on the surface of the channel region between the source region and the drain region.
Optionally, before forming the shallow trench isolation region and the partial isolation region, the method further comprises: and carrying out ion implantation on the semiconductor material layer so that the doping concentration is more than 1e17/cm 3.
Optionally, forming a shallow trench isolation region at the outermost side of the device and a partial isolation region extending to two sides along the width direction of the gate of the device on the semiconductor material layer, including: etching the semiconductor material layer to the buried oxide layer in a region where the shallow trench isolation region needs to be formed; etching the semiconductor material layer in the region where the partial isolation region needs to be formed to a position which is more than or equal to 50nm from the buried oxide layer; and filling isolation oxide in the etched region to form the shallow trench isolation region and the partial isolation region.
Optionally, forming a source region, a drain region, a body contact region and a deep implantation region on the semiconductor material layer includes: performing ion implantation between the shallow trench isolation region and the partial isolation region to form the body contact region, wherein the doping concentration of the body contact region is greater than that of the active region; preparing an implantation window on the body contact region, the implantation window comprising all or part of the surface of the body contact region; and performing ion deep implantation in the implantation window to form the deep implantation region extending from the bottom of the body contact region to the buried oxide layer and connecting the body contact region and the active region of the device.
Optionally, forming a source region, a drain region, a body contact region and a deep implantation region on the semiconductor material layer includes: the deep implantation region with the doping concentration larger than 1e18/cm 3 is formed by implantation with the dosage more than 1e14/cm 2.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
according to the SOI MOSFET device and the preparation method thereof provided by the embodiment of the application, the edge of the active region is provided with the partial isolation region extending to two sides along the width direction of the grid electrode, the body contact region arranged between the shallow trench isolation region and the partial isolation region is combined, and the deep injection region is arranged from the bottom of the body contact region to the buried oxide layer. In one aspect, a portion of the isolation region separates the SOI device edge from the BOX, eliminating the effect of positive charge accumulation in the BOX layer on device edge parasitic MOS. On the other hand, the deep injection region under the combined body contact region can greatly improve the impurity concentration of the edge of the active region between the source and the drain, increase the starting threshold of the edge parasitic MOS device and prevent the formation of an edge leakage channel. And the partial isolation region can also prevent the performance influence of the deep injection region on the source region and the drain region, and reduce adverse parasitic effects on the basis of ensuring the performance of the device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of edge leakage of a prior art SOI device;
Fig. 2 is a block diagram of an SOI MOSFET device in accordance with one or more embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a deep implant region location in accordance with one or more embodiments of the present disclosure;
Fig. 4 is a flow chart of a method of fabricating an SOI MOSFET device in accordance with one or more embodiments of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In the context of the present disclosure, similar or identical components may be indicated by identical or similar reference numerals.
In order to better understand the above technical solutions, the following detailed description will be made with reference to specific embodiments, and it should be understood that the embodiments of the present disclosure and specific features in the embodiments are detailed descriptions of the technical solutions of the present disclosure, and not limiting the technical solutions of the present disclosure, and the technical features in the embodiments and embodiments of the present disclosure may be combined with each other without conflict.
According to one aspect of the present disclosure, there is provided an SOI MOSFET device, as shown in fig. 2, comprising:
An active region 2 and a grid electrode 3 which are positioned on the oxygen burying layer 1, wherein an active region 21 and a drain region 22 are arranged in the active region 2;
A partial isolation region 4 disposed at the edge of the active region 2 and extending to both sides in the width direction of the gate electrode 3, wherein a part of the active region 2 is spaced between the partial isolation region 4 and the buried oxide layer 1;
the shallow slot isolation region 5 is arranged at the outermost side of the device;
a body contact region 6 arranged between the shallow trench isolation region 5 and the partial isolation region 4, wherein a deep implantation region 7 is arranged from the bottom of the body contact region 6 to the buried oxide layer 1, and the deep implantation region 7 connects the body contact region 6 and the active region 2; wherein the doping types of the deep implantation region 7, the body contact region 6 and the active region 2 are the same, and the doping types of the source region 21 and the drain region 22 are different from those of the active region 2.
In fig. 2, (B) is a cross-sectional view of (a) upper broken line area B, and (c) is a cross-sectional view of (a) lower broken line area a-a'.
Specifically, when the device is an SOI NMOS device, the active region 2 is doped P-type, the deep implanted region 7 and the body contact region 6 are doped p+ type, and the source region 21 and the drain region 22 are doped n+ type. When the device is an SOI PMOS device, the active region 2 is doped with N type, the deep injection region 7 and the body contact region 6 are doped with N+ type, and the source region 21 and the drain region 22 are doped with P+ type.
In a specific implementation process, the doping concentration of the deep implantation region 7 and the doping concentration of the body contact region 6 are both greater than the doping concentration of the active region 2. The active region 2 comprises a channel region of the device and a semiconductor material layer region below the source and drain regions.
The following description will be made by taking the device as an SOI NMOS, and the active region 2 and the like are all prepared on silicon as an example:
The deep P-type implantation of the deep implant region 7 greatly increases the concentration of P-type doping in the lower portion of the silicon layer of the body contact region 6. Preferably, the deep injection region 7 is arranged to fill the included angle formed by the shallow trench isolation region 5 and the buried oxide layer 1, so that the concentration of P-type impurities near the included angle between the shallow trench isolation region 5 and the buried oxide layer 1 is greatly improved, and the lower edge leakage channel which is easily conducted in an inversion mode between the N+ source drain regions of the original device becomes extremely difficult to be inverted, thereby thoroughly cutting off the lower edge leakage path. On the other hand, although the overlapping edge of the gate electrode 3 and the partial isolation region 4 may still generate an upper edge leakage path under the effect of positive charge accumulation in the irradiation process, since the partial isolation region 4 is separated from the buried oxide layer 1 with a P-type well region therebetween and shielded, the electric field generated by positive charge accumulation in the buried oxide layer 1 can no longer affect the edge parasitic MOS structure of the partial isolation region 4, and therefore, the inversion degree of the upper edge channel of the device is only dependent on the positive charge accumulation in the field oxidation of the partial isolation region 4, and is independent of the buried oxide layer 1, which significantly limits the magnitude of the upper edge leakage and optimizes the upper edge leakage degree.
In an alternative embodiment, the deep implantation region 7 may extend not only below the fully filled body contact region 6 and the angle between the shallow trench isolation region 5 and the buried oxide layer 1, but also below the partial isolation region 4, as shown in fig. 2. It is also possible to provide that the deep implant region 7 only partially fills under the body contact region 6 and/or partially fills the angle of the shallow trench isolation region 5 with the buried oxide layer 1 as shown in fig. 3. As long as the deep implant region 7 extends from the bottom of the body contact region 6 to the buried oxide layer 1 and connects the body contact region 6 and the active region 2, there is no limitation.
Specifically, the deep P-type injection is only required to be performed on any section of the edges of the body contact region 6 and the active region 2 to cut off the lower edge leakage channel, so that the layout design of the deep injection region 7 is relatively flexible, and the deep injection region is ensured to be overlapped with the body contact region 6 sufficiently only by conforming to the design rule of the injection window. Preferably, the deep implant region 7 is provided so as not to extend beyond the region under part of the isolation region 4 to be spaced apart from the source region 21 and said drain region 22 as shown in figures 2 and 3. The distance from the main MOS device (source-drain region and channel region) is ensured to avoid interfering with the performance of the device and also avoid influencing the source-drain region when the implanted ions form the deep implanted region 7. This provides latitude to the layout design.
The above description takes the device as an SOI NMOS as an example, and if the device is a PMOS, only the doping type (N/P) involved needs to be interchanged, and the scheme still applies. However, in general, the oxide has no segregation on the N-type impurity, so that PMOS generally does not need to consider the problem of edge leakage during irradiation. The device structure provided by the application has more obvious improvement effect on NMOS.
Preferably, the thickness of the active region 2 reserved between the partial isolation region 4 and the buried oxide layer 1 is greater than or equal to 50nm. The doping concentration of the deep implantation region 7 is greater than 1e18/cm 3, and the doping concentration of the active region 2 and the channel region of the device is greater than 1e17/cm 3.
Based on the same inventive concept, the application also provides a preparation method of the SOI MOSFET device provided by the application, as shown in fig. 4, comprising the following steps:
Step S401, providing a substrate, wherein an oxygen burying layer 1 is arranged on the substrate, and a semiconductor material layer is arranged on the oxygen burying layer 1;
step S402, forming a shallow trench isolation region 5 at the outermost side of the device and a partial isolation region 4 extending to two sides along the width direction of the gate electrode 3 of the device on the semiconductor material layer, wherein the shallow trench isolation region 5 extends downwards to be connected with the buried oxide layer 1, a part of the semiconductor material layer (active region 2) is spaced between the partial isolation region 4 and the buried oxide layer 1, and a part of the semiconductor material layer is spaced between the partial isolation region 4 and the shallow trench isolation region 5;
Step S403, forming a source region 21, a drain region 22, a body contact region 6 and a deep implantation region 7 on the semiconductor material layer, wherein the body contact region 6 is formed between the shallow trench isolation region 5 and the partial isolation region 4, the deep implantation region 7 extends from the bottom of the body contact region 6 to the buried oxide layer 1, and the deep implantation region 7 connects the body contact region 6 and the active region 2 of the device; wherein the doping types of the deep implantation region 7, the body contact region 6 and the active region 2 are the same, and the doping types of the source region 21 and the drain region 22 are different from those of the active region 2;
Step S404, preparing a gate electrode 3 on the channel region surface between the source region 21 and the drain region 22.
The semiconductor material layer may be a silicon layer, a silicon germanium layer, or the like, which is not limited herein. Preferably, the application is suitable for thicker semiconductor material layers (the thickness of the semiconductor material layer is more than 150 nm) and shallower P+ doping (the depth of the P+ high concentration distribution is less than the thickness of the semiconductor material layer).
After providing the substrate with the buried oxide layer 1 and the semiconductor material layer arranged upwards in sequence, ion implantation can be performed on the semiconductor material layer first, so that the doping concentration is greater than 1e17/cm 3, and the semiconductor material layer is used as an active region 2 below a channel region and a source drain region of the device. Of course, the semiconductor material layer may be implanted after the shallow trench isolation region 5 and the partial isolation region 4 are formed, which is not limited herein. The implantation doping step can be completed simultaneously with the channel implantation of the device by sharing a well mask.
Then, shallow trench isolation regions 5 at the outermost sides of the device and partial isolation regions 4 extending to both sides in the width direction of the gate electrode 3 of the device are formed on the semiconductor material layer. Specifically, etching the semiconductor material layer to the buried oxide layer 1 in the area where the shallow trench isolation region 5 needs to be formed; and etching the semiconductor material layer to a position which is more than or equal to 50nm from the oxygen-buried layer 1 in a region where the partial isolation region 4 needs to be formed. And filling isolation oxide in the etched area to form the shallow trench isolation region 5 and the partial isolation region 4.
Specifically, a 1-layer mask can be added in the original shallow trench isolation region 5 etching step of the device, and the edge of the active region 2in the width direction of the device gate extends outwards by a certain width to define an SOI part isolation region 4. And etching the shallow trench isolation region to the buried oxide layer 1. And forming strip-shaped grooves which are only etched to the middle part of the upper semiconductor material layer of the buried oxide layer 1 of the SOI in the partial isolation region through the additional 1 times of partial silicon etching, and filling isolation oxide together with other grooves which are completely etched to the buried oxide layer 1, thereby forming a fully isolated shallow trench isolation region 5 and a partial isolation region 4 at the same time.
For example, if the device is an SOI NMOS device, the semiconductor material layer under the partial isolation 4 is P-type as the channel region. Correspondingly, for the SOI PMOS device, the semiconductor material layer under the partial isolation region 4 is N-type. In order to ensure a stable low series resistance of the semiconductor material layer between part of the isolation region 4 and the buried oxide layer 1, the thickness of the remaining semiconductor material layer should remain at least 50nm.
Then, a source region 21, a drain region 22, a body contact region 6 and a deep implant region 7 are formed on the semiconductor material layer. Specifically, ion implantation is performed between the shallow trench isolation region 5 and the partial isolation region 4 to form the body contact region 6, and the doping concentration of the body contact region 6 is greater than that of the active region 2; preparing an implantation window on the body contact region 6, the implantation window comprising all or part of the surface of the body contact region 6; ion deep implantation is performed in the implantation window, and the deep implantation region 7 extending from the bottom of the body contact region 6 to the buried oxide layer 1 and connecting the body contact region 6 and the active region 2 of the device is formed.
The implantation window may cover not only the body contact region 6 but also only a part of the body contact region 6, which is not limited herein.
Specifically, taking a device as an SOI NMOS device as an example, a 1-layer mask plate can be added in the step of device source drain injection, and an injection window can be photoetched in the region of the P+ body contact region 6 of the device. The window need only expose the edge of body contact region 6 at any location where it engages the active region, while the edge of the implantation window is preferably kept a safe distance from the overlapping location of device gate 3 and part of isolation region 4 to avoid lateral diffusion of ions affecting device characteristics when deep P-type implants form deep implant region 7. The deep P-type implantation can adopt P-type impurity ions such as boron and the like, the ion range corresponding to the implantation energy is approximately equal to or slightly smaller than the thickness of the semiconductor material layer, and the deep implantation region with the doping concentration larger than 1e18/cm 3 is formed by adopting the dose implantation of more than 1e14/cm 2.
And then preparing structures such as a grid electrode 3, a metal lead and the like, and finally forming the device for resisting the edge leakage. Therefore, the application thoroughly eliminates the parasitic MOS leakage channel at the lower edge of the active region 2 and optimizes the parasitic MOS leakage channel at the upper edge through the combination of the body contact region 6, the deep injection region 7 and a partial isolation process.
In view of the fact that the method provided in this embodiment is the method for manufacturing the device provided in the foregoing embodiment, the specific structure of the device has been described in detail, and will not be described in detail.
Specifically, in the SOI MOSFET device and the method for manufacturing the same according to the embodiments of the present application, a partial isolation region extending to both sides in the width direction of the gate is provided at an edge of the active region, a body contact region is provided between the shallow trench isolation region and the partial isolation region in combination, and a deep implantation region is provided from a bottom of the body contact region to the buried oxide layer. In one aspect, a portion of the isolation region separates the SOI device edge from the BOX, eliminating the effect of positive charge accumulation in the BOX layer on device edge parasitic MOS. On the other hand, the deep injection region under the combined body contact region can greatly improve the impurity concentration of the edge of the active region between the source and the drain, increase the starting threshold of the edge parasitic MOS device and prevent the formation of an edge leakage channel. And the partial isolation region can also prevent the performance influence of the deep injection region on the source region and the drain region, and reduce adverse parasitic effects on the basis of ensuring the performance of the device.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, given that such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims (9)

1. An SOI MOSFET device, comprising:
The active region and the grid electrode are positioned on the buried oxide layer, and an active region and a drain region are arranged in the active region;
The partial isolation region is arranged at the edge of the active region and extends to two sides along the width direction of the grid electrode, and a part of the active region is arranged between the partial isolation region and the oxygen burying layer at intervals;
The shallow slot isolation region is arranged at the outermost side of the device;
The body contact region is arranged between the shallow groove isolation region and the partial isolation region, a deep injection region is arranged from the bottom of the body contact region to the oxygen burying layer, and the deep injection region is connected with the body contact region and the active region; the doping types of the deep injection region, the body contact region and the active region are the same, and the doping types of the source region and the drain region are different from the doping type of the active region;
the doping concentration of the deep injection region and the doping concentration of the body contact region are both greater than the doping concentration of the active region.
2. The device of claim 1, wherein:
And the thickness of the active region reserved between the partial isolation region and the buried oxide layer is greater than or equal to 50nm.
3. The device of claim 1, wherein:
The doping concentration of the deep implantation region is greater than 1e18/cm 3, and the doping concentration of the active region and the channel region of the device is greater than 1e17/cm 3.
4. The device of claim 1, wherein:
the deep injection region fills an included angle formed by the shallow groove isolation region and the buried oxide layer;
the deep implant region does not extend beyond the portion of the isolation region to be spaced apart from the source region and the drain region.
5. A method of fabricating an SOI MOSFET device, comprising:
providing a substrate, wherein an oxygen burying layer is arranged on the substrate, and a semiconductor material layer is arranged on the oxygen burying layer;
Forming a shallow slot isolation region at the outermost side of a device and a part of isolation regions extending to two sides along the width direction of a grid electrode of the device on the semiconductor material layer, wherein the shallow slot isolation region extends downwards to be connected with the oxygen-buried layer, a part of the semiconductor material layer is arranged between the part of isolation regions and the oxygen-buried layer at intervals, and a part of the semiconductor material layer is arranged between the part of isolation regions and the shallow slot isolation regions at intervals;
Forming a source region, a drain region, a body contact region and a deep implantation region on the semiconductor material layer, wherein the body contact region is formed between the shallow trench isolation region and the partial isolation region, the deep implantation region extends from the bottom of the body contact region to the buried oxide layer, and the deep implantation region is connected with the body contact region and the active region of the device; the doping types of the deep injection region, the body contact region and the active region are the same, and the doping types of the source region and the drain region are different from the doping type of the active region;
the doping concentration of the deep injection region and the doping concentration of the body contact region are both greater than the doping concentration of the active region;
And preparing a grid electrode on the surface of the channel region between the source region and the drain region.
6. The method of claim 5, further comprising, prior to forming the shallow trench isolation region and the partial isolation region:
and carrying out ion implantation on the semiconductor material layer so that the doping concentration is more than 1e17/cm 3.
7. The method of claim 5, wherein forming a shallow trench isolation region on the semiconductor material layer that is outermost of a device and a portion of the isolation region that extends to both sides in a width direction of a gate of the device comprises:
Etching the semiconductor material layer to the buried oxide layer in a region where the shallow trench isolation region needs to be formed; etching the semiconductor material layer in the region where the partial isolation region needs to be formed to a position which is more than or equal to 50nm from the buried oxide layer;
and filling isolation oxide in the etched region to form the shallow trench isolation region and the partial isolation region.
8. The method of claim 5, wherein forming a source region, a drain region, a body contact region, and a deep implant region on the layer of semiconductor material comprises:
Performing ion implantation between the shallow trench isolation region and the partial isolation region to form the body contact region, wherein the doping concentration of the body contact region is greater than that of the active region;
Preparing an implantation window on the body contact region, the implantation window comprising all or part of the surface of the body contact region;
And performing ion deep implantation in the implantation window to form the deep implantation region extending from the bottom of the body contact region to the buried oxide layer and connecting the body contact region and the active region of the device.
9. The method of claim 5, wherein forming a source region, a drain region, a body contact region, and a deep implant region on the layer of semiconductor material comprises:
The deep implantation region with the doping concentration larger than 1e18/cm 3 is formed by implantation with the dosage more than 1e14/cm 2.
CN202010893868.4A 2020-08-31 2020-08-31 SOI MOSFET device and preparation method thereof Active CN112054062B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010893868.4A CN112054062B (en) 2020-08-31 2020-08-31 SOI MOSFET device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010893868.4A CN112054062B (en) 2020-08-31 2020-08-31 SOI MOSFET device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN112054062A CN112054062A (en) 2020-12-08
CN112054062B true CN112054062B (en) 2024-04-30

Family

ID=73607881

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010893868.4A Active CN112054062B (en) 2020-08-31 2020-08-31 SOI MOSFET device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112054062B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1371132A (en) * 2001-02-13 2002-09-25 三菱电机株式会社 Semiconductor unit and its making process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6905919B2 (en) * 2003-07-29 2005-06-14 Chartered Semiconductor Manufacturing Ltd. Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
JP5360735B2 (en) * 2006-02-20 2013-12-04 セイコーインスツル株式会社 Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1371132A (en) * 2001-02-13 2002-09-25 三菱电机株式会社 Semiconductor unit and its making process

Also Published As

Publication number Publication date
CN112054062A (en) 2020-12-08

Similar Documents

Publication Publication Date Title
US8735990B2 (en) Radiation hardened FinFET
CN103531478B (en) Multi-Gate FETs and methods for forming the same
US7981783B2 (en) Semiconductor device and method for fabricating the same
US20080160706A1 (en) Method for fabricating semiconductor device
CN111092112B (en) MOS field effect transistor and manufacturing method thereof
US20170047430A1 (en) Manufacturing method of trench power mosfet
US20080061364A1 (en) Trench type MOS transistor and method for manufacturing the same
JP2008270806A (en) Semiconductor device and manufacturing method therefor
JP2016063072A (en) Semiconductor device manufacturing method
US9853099B1 (en) Double diffused metal oxide semiconductor device and manufacturing method thereof
KR20060106768A (en) Method of forming an integrated power device and structure
US6841440B2 (en) Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same
US8022475B2 (en) Semiconductor device optimized to increase withstand voltage and reduce on resistance
KR100724577B1 (en) High output resistance semiconductor device and method of fabricating the same
CN112054062B (en) SOI MOSFET device and preparation method thereof
JP2004022769A (en) Lateral high breakdown voltage semiconductor device
CN112466950B (en) Anti-edge leakage SOI MOS structure and forming method thereof
JP6022777B2 (en) Manufacturing method of semiconductor device
US5128733A (en) Silicon mesa transistor structure
KR101063567B1 (en) Mos device and the manufacturing method thereof
CN112018038A (en) Preparation method of semiconductor device
KR20100020688A (en) Ldmos semiconductor and method for fabricating the same
JP2006332232A (en) Semiconductor device and manufacturing method thereof
CN112466953B (en) H-shaped body contact SOI MOSFET device and manufacturing method thereof
CN111933693B (en) MOS transistor and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant