CN112039449A

CN112039449A - Ultrahigh frequency variable gain amplifier structure

Info

Publication number: CN112039449A
Application number: CN202010903645.1A
Authority: CN
Inventors: 柴远; 冯一坤
Original assignee: Nanjing Huijun Semiconductor Technology Co ltd
Current assignee: Nanjing Huijun Semiconductor Technology Co ltd
Priority date: 2020-09-01
Filing date: 2020-09-01
Publication date: 2020-12-04
Anticipated expiration: 2040-09-01
Also published as: CN112039449B

Abstract

The invention discloses an ultrahigh frequency variable gain amplifier structure, which comprises a first partial circuit (100) and a fourth partial circuit (400) which are formed by a broadband transformer matching network; the parallel amplitude control modules form a second partial circuit (200) and a third partial circuit (300), and the first partial circuit (100) completes 50-ohm load to input impedance R_inMatching and realizing single-ended signal RF_inConversion to differential signals in + and in-; the second part of the circuit (200) is composed of 6 parallel basic gain units based on the differential common source amplifier with the normalized size of 1x to 32 x; the third part of the circuit (300) is composed of 3 improved multiple parallel equivalent structures; the fourth partial circuit (400) completes the output impedance R_outMatching to a 50 ohm load, implementing differential signal out + and out-to-single ended signal RF_outThe conversion of (1). By passingIn the mode, the invention realizes accurate stepping on the basis of ensuring the gain and simultaneously ensures that each gain state has the same output impedance and amplitude modulation additional phase shift.

Description

Ultrahigh frequency variable gain amplifier structure

Technical Field

The invention relates to the technical field of electronic circuit design, in particular to an ultrahigh frequency variable gain amplifier which is particularly suitable for designing a gain adjusting module in a millimeter wave phased array system.

Background

In recent years, with the rapid development of communication technologies, higher and wider-band spectrum resources will be used. Aiming at the problems of large propagation loss and small signal coverage range of a high-frequency band, a phased array technology, including a multi-antenna array and a beam forming technology, is widely applied to a high-frequency communication system to make up for path loss and improve flexibility and directivity of signal coverage.

Phased array technology achieves beam deflection by applying a certain phase shift to the signals of the basic array. Meanwhile, the phase position is compensated in multiple directions, so that multiple beams are obtained. In millimeter wave phased array systems, precise control of phase and amplitude is an important factor.

The amplitude control module is an important component of the phased array system. When the phased array antenna scans beams, the channels are in different states, which causes the amplitudes of the channels to be inconsistent. The signal amplitude of each channel of the phased array system can be adjusted through amplitude control so as to reduce the amplitude deviation among the channels and reduce the side lobe of the synthesized beam of the phased array system, and therefore the directivity of the beam is enhanced. In addition, in a communication system, due to channel attenuation, atmospheric loss and interference of various noises, the strength of a signal received by a receiver is unstable, and a large dynamic range is generated. For more reliable reception of signals, attenuators or variable gain amplifiers are typically employed to ensure that the transmit and receive amplitudes are consistent at different phase states.

Compared with an attenuator, the variable gain amplifier has certain advantages in a high-frequency millimeter wave band. The attenuator has the advantages of ultra wide band, no direct current loss and the like, but because the attenuator is a passive device, the amplitude can be controlled only by controlling the loss and the control precision is not high. The variable gain amplifier has certain power consumption, but compared with the attenuator, the variable gain amplifier can provide a higher gain adjustment range and high-precision adjustment steps. In addition, the structure of the invention has 180-degree phase shift, and the design pressure of the phase shifter can be reduced to improve the performance of the whole system.

The cascode structure has high output impedance and gain and has shielding characteristics. The method has wide application in the design of the variable gain amplifier of the millimeter wave phased array system. However, as the frequency increases, some problems become more pronounced. The accuracy of the variable gain amplifier is severely affected by the change in the output impedance and phase of each gain state. The trade-off of indexes such as stepping precision, adjustment range and highest gain also becomes a big difficulty, so that new structures and designs are increasingly developed.

In the design of the high frequency band, a differential cascode structure is generally adopted to implement the variable gain amplifier. The structure has higher output impedance, and is beneficial to the design of a matching network. And the input end and the output end are isolated, so that the gain is higher. However, as the frequency increases and the index requirement increases, the design of the ultra-high frequency variable gain amplifier still faces many challenges, such as (1) the gate voltage of the transistor and the gain of the amplifier are in a power function relationship, it is difficult to increase the influence of the parasitic capacitance of the transistor on the exponential linear step (2), and the phase error of the variable gain amplifier is enlarged in different gain states, which makes the phase calibration of the phased array system complicated. (3) While ensuring a large adjustable range, the highest gain will be sacrificed seriously if a small and precise stepping precision is to be realized. (4) To eliminate the parasitic parameters between the cascodes to improve gain, inductors or transformers are often connected in series in the intermediate stages. This will greatly increase the chip area and increase the cost.

Disclosure of Invention

The invention aims to provide an ultrahigh frequency variable gain amplifier structure, provides an optimized multiple parallel equivalent structure aiming at the contradiction of gain adjustment range, highest gain and stepping precision in the conventional ultrahigh frequency variable gain amplifier, and realizes accurate stepping on the basis of ensuring the maximum gain and the adjustment range.

In addition to this, the inventive structure has the same output impedance and amplitude modulation additional phase shift in each gain state, and a phase selection of 180 ° can be achieved. Based on the structure, the invention finally realizes the 9-bit variable gain amplifier with high frequency, high precision, low amplitude modulation, additional phase and ultra wide band.

In order to solve the technical challenges, the invention adopts a technical scheme that: provide aThe ultrahigh frequency variable gain amplifier structure comprises a first partial circuit and a fourth partial circuit which are formed by a broadband transformer matching network; the parallel amplitude control modules form a second partial circuit and a third partial circuit, and the first partial circuit completes 50-ohm load to input impedance R_inMatching and realizing single-ended signal RF_inConversion to differential signals in + and in-; the second part of circuit is composed of 6 parallel basic gain units based on a differential common source amplifier with the normalized size of 1x to 32x, and sufficient gain control range and rough gain step adjustment are achieved; the third part of circuit is composed of 3 improved multiple parallel equivalent structures, and accurate stride control is realized; the fourth part of the circuit completes output impedance R_outMatching to a 50 ohm load and implementing differential signals out + and out-to single ended signal RF_outThe conversion of (1).

Further, the amplitude control module ensures that the gain adjustable range is greater than 15dB and provides 1dB steps; the amplitude control module promotes accurate stepping to 0.5 dB.

Furthermore, the first partial circuit is a broadband input transformer matching network and comprises a first transmission line, a second transmission line, a first transformer and a first capacitor, wherein the first transmission line and the second transmission line form a differential pair, the differential pair is connected with a secondary coil of the first transformer and respectively passes through a positive phase signal in + and a reverse phase signal in-, a primary coil of the first transformer is connected with an input signal RF after being connected with the first capacitor in parallel_in。

Further, the second part of circuit is composed of 6 common source transistor array units connected in parallel, the array unit is composed of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first inverter, the gates of the first and third transistors are connected to the positive terminal of the input signal of the first section, the gates of the second transistor and the fourth transistor are connected with the negative terminal of the input signal of the first partial circuit, the drains of the first transistor and the fourth transistor are connected with the positive terminal of the output signal of the second partial circuit, the drains of the second transistor and the third transistor are connected with the negative end of the output signal of the second partial circuit, the fifth transistor and the sixth transistor are used as switching tubes, the grid electrode of the fifth transistor is connected with a digital control signal, and the grid electrode of the sixth transistor is connected with the digital control signal after passing through the first phase inverter.

Further, the third partial circuit is composed of 3 optimized common-gate transistor array units connected in parallel, each array unit is composed of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first inverter and a second inverter, gates of the first transistor, the third transistor, the seventh transistor and the ninth transistor are connected with a positive terminal of an input signal of the first partial circuit, gates of the second transistor, the fourth transistor, the eighth transistor and the tenth transistor are connected with a negative terminal of the input signal of the first partial circuit, drains of the first transistor, the fourth transistor, the seventh transistor and the tenth transistor are connected with a positive terminal of an output signal of the second partial circuit, the drains of the second transistor, the third transistor, the eighth transistor and the ninth transistor are connected with the negative end of the output signal of the second partial circuit, the fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor are used as switch control transistors, the fifth transistor is connected with the output end of the first inverter, the sixth transistor and the eleventh transistor are connected with the output end of the second inverter, and the twelfth transistor is connected with the digital control signal.

Furthermore, the circuit composition and connection of the fourth partial circuit broadband output transformer matching network are the same as those of the first partial circuit.

Further, a center tap of a secondary coil of the transformer in the third partial circuit is connected with the bias voltage Vbias, and a center tap of a primary coil of the transformer in the fourth partial circuit is connected with the power supply VDD.

Further, the 6 common source transistor arrays of the second partial circuit are different in size.

Further, the 3 optimized common-source transistor arrays of the third partial circuit are different in size.

Furthermore, each array unit in the third partial circuit is composed of two similar and smaller basic gain units cell1 and cell2 which are connected in parallel through inverted digital signal control.

The invention has the beneficial effects that: the invention discloses an ultrahigh frequency variable gain amplifier structure, which provides an optimized multiple parallel equivalent structure and realizes accurate stepping on the basis of ensuring gain; the invention adopts the modularized design thinking, can efficiently complete the design and inspection work, and is convenient for the repeated use of other projects; the invention adopts a highly symmetrical design scheme, fully considers layout when a circuit is built, and has small layout parasitic, beautiful and simple appearance; the core module of the invention does not use passive devices, so that the layout area is extremely small, and the cost can be greatly reduced; each gain state of the structure has the same output impedance and amplitude modulation additional phase shift, so that the loss and the unbalance of each state can be greatly reduced; the transistor used in the invention has smaller size, thus having low power consumption and higher practical value.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1A is a schematic circuit diagram of an uhf variable gain amplifier;

FIG. 1B is a schematic diagram of a basic gain block including parasitic capacitances;

FIG. 2 is a graph of comparative simulation results using an optimized ultra-small size equivalent array;

FIG. 3 is a diagram showing simulation results of S-parameters in 32 states of positive phase of a variable gain amplifier;

fig. 4 is a graph showing simulation results of phase errors in 32 states of the positive phase of the variable gain amplifier.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are exemplary only, and the invention is not limited to these embodiments.

It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.

Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1 to 4, an embodiment of the present invention includes: the variable gain amplifier of the present invention relates to the application fields including: transmitter/receiver systems, 5G communications, satellite communications, phased array systems, and the like.

The structure of the ultrahigh frequency variable gain amplifier comprises a first partial circuit 100 and a fourth partial circuit 400 which are formed by a broadband transformer matching network; the parallel amplitude control modules form a second partial circuit 200 and a third partial circuit 300, and the first partial circuit 100 completes 50-ohm load to input impedance R_inMatching and realizing single-ended signal RF_inConversion to differential signals in + and in-; the second part is electricThe path 200 consists of 6 parallel basic gain units based on a differential common source amplifier with normalized size of 1x to 32x, realizing sufficient gain control range and coarse gain step adjustment; the third part of the circuit 300 consists of 3 improved multiple parallel equivalent structures, and the accurate stride control is realized; the fourth partial circuit 400 completes the output impedance R_outMatching to a 50 ohm load and implementing differential signals out + and out-to single ended signal RF_outThe conversion of (1).

The amplitude control module 200 ensures that the gain adjustable range is greater than 15dB and provides 1dB steps; the amplitude control module 300 promotes accurate stepping to 0.5 dB.

The first partial circuit 100 is a broadband input transformer matching network, and is composed of a first transmission line 101, a second transmission line 102, a first transformer 103 and a first capacitor 104, wherein the first transmission line 101 and the second transmission line 102 form a differential pair, are connected with a secondary coil of the first transformer 103 and respectively pass through a positive phase signal in + and a negative phase signal in-, a primary coil of the first transformer 103 is connected with an input signal RF after being connected in parallel with the first capacitor 104_in。

The second sub-circuit 200 is composed of 6 common-source transistor array units connected in parallel, the array units are composed of a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a fifth transistor 205, a sixth transistor 206 and a first inverter 207, the gates of the first transistor 201 and the third transistor 203 are connected with the positive terminal of the input signal of the first sub-circuit 100, the gates of the second transistor 202 and the fourth transistor 204 are connected with the negative terminal of the input signal of the first sub-circuit 100, the drains of the first transistor 201 and the fourth transistor 204 are connected with the positive terminal of the output signal of the second sub-circuit 200, the drains of the second transistor 202 and the third transistor 203 are connected with the negative terminal of the output signal of the second sub-circuit 200, the fifth transistor 205 and the sixth transistor 206 are used as switching tubes, the gate of the fifth transistor 205 is connected with a digital control signal, the gate of the sixth transistor 206 is connected to the digital control signal via the first inverter 207.

The third sub-circuit 300 is composed of 3 optimized common-gate transistor array units connected in parallel, each array unit is composed of a first transistor 301, a second transistor 302, a third transistor 303, a fourth transistor 304, a fifth transistor 305, a sixth transistor 306, a seventh transistor 307, an eighth transistor 308, a ninth transistor 309, a tenth transistor 310, an eleventh transistor 311, a twelfth transistor 312, a first inverter 313 and a second inverter 314, the gates of the first transistor 301, the third transistor 303, the seventh transistor 307 and the ninth transistor 309 are connected with the positive terminal of the input signal of the first sub-circuit 100, the gates of the second transistor 302, the fourth transistor 304, the eighth transistor 308 and the tenth transistor 310 are connected with the negative terminal of the input signal of the first sub-circuit 100, the drains of the first transistor 301, the fourth transistor 304, the seventh transistor 307 and the tenth transistor 310 are connected with the positive terminal of the output signal of the second sub-circuit 200, the drains of the second transistor 302, the third transistor 303, the eighth transistor 308 and the ninth transistor 309 are connected to the negative terminal of the output signal of the second sub-circuit 200, the fifth transistor 305, the sixth transistor 306, the eleventh transistor 311 and the twelfth transistor 312 are used as switching control transistors, the fifth transistor 305 is connected to the output terminal of the first inverter 313, the sixth transistor 306 and the eleventh transistor 311 are connected to the output terminal of the second inverter, and the twelfth transistor 312 is connected to the digital control signal.

The fourth partial circuit 400 is a wideband output transformer matching network, and the circuit composition and connection thereof are the same as those of the first partial circuit 100.

The center tap of the secondary winding of the transformer 103 in the third sub-circuit 300 is connected to the bias voltage Vbias, and the center tap of the primary winding of the transformer 403 in the fourth sub-circuit 400 is connected to the power supply VDD.

The transistor sizes of the 6 common source transistor array units of the second sub-circuit 200 are different.

Further, each array cell in the third sub-circuit 300 is composed of two basic gain cells cell1 and cell2 with different sizes, which are controlled in parallel by inverted digital signals.

Example 1:

as shown in fig. 1A, the schematic diagram of the structure of the uhf variable gain amplifier provided in the present invention includes input/output matching networks 100 and 400, and amplitude control modules 200 and 300 connected in parallel. The amplitude control module is formed by connecting 9 gain units with different sizes in parallel, and each unit is of a circuit structure based on a differential common source transistor. The invention uses an ultra-small size equivalent structure, and completes the precision improvement while ensuring the gain. The invention can cover the amplitude regulation range of 15dB, and the amplitude modulation is stepped to be accurate 0.5 dB.

As shown in fig. 1A, the first partial circuit 100 and the fourth partial circuit 400 in the present invention implement functions of signal synthesis and decomposition, single-end and double-end signal conversion, and input-output matching, and this section takes the first partial circuit as an example. The first part of the circuit consists of a transmission line 101, a transmission line 102, a transformer 103 and a parallel capacitor 104. The primary coil of the transformer 103 is connected in parallel with a capacitor 104 and then connected with an input signal RF_in. A center tap connection V of the secondary winding of the transformer 103_biasAnd providing a grid bias voltage for the common source amplifier.

As shown in fig. 1A, the second sub-circuit 200 of the present invention is formed by connecting in parallel 6 common-source transistor array units of different sizes, where one array unit includes a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a fifth switching transistor 205, a sixth switching transistor 206, and an inverter 207. The sources of the first transistor 201 and the second transistor 202 are connected to form a virtual ground and to the drain of the fifth switching transistor 205, the gates are connected to the positive terminal and the negative terminal of the differential input signal, respectively, and the drains are connected to the negative terminal and the positive terminal of the differential output signal, respectively, to form a first inverting amplified differential pair. The sources of the third and fourth transistors 204 are connected to form a virtual ground and to the drain of the sixth switching transistor 206, the gates are connected to the positive and negative terminals of the differential input signal, respectively, and the drains are connected to the positive and negative terminals of the differential output signal, respectively, to form a second positive-phase amplified differential pair. The common source differential structure can obtain the maximum voltage swing under lower power supply voltage and has better common mode rejection ratio. The fifth switching transistor 205 and the sixth switching transistor 206 have opposite switching logic, controlling the switching on and off of the tail current paths of the two differential pairs, respectively. In addition, the transistor size in the same array unit is the same, and the transistor size used by different array units is increased in a 2-system mode. The control method determines positive and negative phases of an array unit output signal.

Fig. 1B shows the main circuit structure and parasitic parameters of any unit in the common-source transistor array adopted in the present invention. Because the switch control logics of the two differential pairs are opposite, one pair always works in a common source amplification state, and the other pair is in an off state. The output differential current is: i is_on-I_offOr is (I)_on-I_off). Where negative signs represent opposite phases. Theoretically, the size of the differential current output by the arrays with different sizes is as follows, because the sizes of the transistors in the different arrays are increased in a binary mode: 2n (I)_on-I_off) Or-2 n (I)_on-I_off). By superposition in parallel, a range from-26 (I) can be achieved_on-I_off) To 26 (I)_on-I_off) Step size of 2 (I)_on-I_off) Linear control of (3). In addition, regardless of the control signal, two groups of common source amplifiers in the array unit are always turned on and off one pair, and the parasitic capacitance output to the ground is always a constant in theory: 2 (C)_gd,on+C_gd,off). While the output resistance is also a constant value.

When a 6-bit gain control module is considered, the minimum width of the process is adopted as the high precision required by the index which cannot be achieved by the normalized size. Adding a larger transistor array at this point will greatly reduce the maximum gain, requiring the introduction of ultra-small arrays that cannot be achieved by the process.

The third part circuit 300 of the invention adopts the design of an equivalent structure, and the size in the using process is equivalent to the precision effect brought by the ultra-small size.

As shown in fig. 1A, the third circuit part 300 of the present invention is composed of 3 ultra-small equivalent common source transistor array units with different sizes connected in parallel. An array unitThe transistor includes a first transistor 301, a second transistor 302, a third transistor 303, a fourth transistor 304, a seventh transistor 307, an eighth transistor 308, a ninth transistor 309, a tenth transistor 310, a fifth switching transistor 305, a sixth switching transistor 306, an eleventh switching transistor 311, a twelfth switching transistor 312, a first inverter 313, and a second inverter 314. Wherein the

transistors

301, 302, 303, 304, 305, 306 and the inverter 313 are the same size and form a basic array one as described in the second partial circuit;

transistors

307, 308, 309, 310, 311, 312 and inverter 314 are the same size and form a second basic array as described for the second partial circuit. The first array and the second array are similar in size and have opposite digital control logic. Considering the array-the minimum normalized size allowed by the process-and outputs the inverted signal, the output differential current is: - (I)_on-I_off) (ii) a Considering array two using a size 1.5 times the normalized size and outputting a positive phase signal, the output differential current is: 1.5 (I)_on-I_off). The output differential current of an array unit of the third sub-circuit 300 formed by connecting the two in parallel is 0.5 (I)_on-I_off). Whereby a smaller gain resolution can be achieved using one bit control bit. At the same time, the transistor sizes of the two arrays connected in parallel in the third sub-circuit 300 are both in the vicinity of the normalized minimum size, which reduces the loss of gain to some extent.

The invention has 32 gain states in common, and the method shown in the third part of circuit 300 ensures accurate and smaller gain steps among the amplitude modulation states on the premise of reducing gain loss. The method has wide applicability, and provides a new idea for using the design of an ultra-small module at high frequency.

In addition, the gain and phase performance in the positive and negative phase modes are balanced, and various indexes are nearly the same in each state. Therefore, the normal mode will be described in detail in fig. 3 and 4 as an example.

Fig. 2 is a graph of performance comparison simulation of the optimized small-sized equivalent structure and the general structure in a system. For ease of simulation verification, we will compare arrays one (by)Optimized equivalent structure of parallel connection of basic gain cells of 1x1.2 μm and 1x0.6 μm) and array two (basic gain cells of 1x0.6 μm) S-parameters in the overall circuit. L1 is shown as S when array one and array two are in inverting phase₂₁Parameter, L₂And L₃S when array one and array two are respectively connected into the whole circuit₂₁And (4) parameters. L is₃Full frequency band less than-30 dB and L₂And L₃Is less than 0.15 dB. This implies the feasibility and rationality of a small-sized equivalent circuit.

Fig. 3 is a simulation result of amplitude adjustment of a 9-bit variable gain amplifier. In the frequency range of the example, the variable gain amplifier can realize high-precision adjustment with the range of 15dB and the stepping of 0.5dB, which means that the invention realizes ultrahigh frequency amplitude modulation performance and has high-precision stepping control.

Fig. 4 is a simulation result of the amplitude modulation added phase of the 9-bit variable gain amplifier. The amplitude modulation additional phase is constant with increasing frequency, and the maximum amplitude modulation additional phase is about 3.22 degrees in the applicable frequency range. Meaning that the phase error between the gain states of the present invention is minimal.

The ultrahigh frequency variable gain amplifier structure has the following advantages:

firstly, the method comprises the following steps: by designing 3 optimized parallel common-gate transistor arrays in the third part of circuit, the stepping precision of the gain state is effectively improved under the condition of ensuring the output gain and the adjustment range.

Secondly, the method comprises the following steps: according to the scheme of positive and negative phase selective current output in the second partial circuit 200 and the third partial circuit 300, the 180-degree phase shifting function can be realized while the gain is controlled, the pressure is relieved for the design of a subsequent phase shifter, and the overall performance of the system is favorably improved.

Thirdly, the method comprises the following steps: the core structure of the invention adopts a differential common source amplifier, and parasitic parameters are easy to eliminate. Since the basic gain cell consists of two differential pairs, each gain state theoretically has the same output impedance and phase shift.

Fourthly: the modularized design idea of each gain unit can effectively improve the efficiency, so that the repeated use and adjustment of the structure in different projects become simple, the design method convenient for digital-analog combination can also improve the integration level, and the method has very high practical value. In addition, passive devices such as inductors and the like are not used in the core circuit, so that the size is extremely small, and the production cost is greatly reduced.

In a designed frequency band, the variable gain amplifier structure can realize gain control of 32 states of positive and negative phases of 9 bits, has accurate 0.5dB stepping precision in a 15dB adjusting range, and has amplitude modulation additional phase shift superior to 4 degrees.

Furthermore, it should be noted that in the present specification, "include" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed, or further includes elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should take the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.

Claims

1. The structure of the ultrahigh frequency variable gain amplifier is characterized by comprising a first partial circuit (100) and a fourth partial circuit (400) which are formed by a broadband transformer matching network; the parallel amplitude control modules form a second partial circuit (200) and a third partial circuit (300), and the first partial circuit (100) completes 50-ohm load to input impedance R_inMatching and realizing single-ended signal RF_inTo differential signals in + and in-Converting; the second partial circuit (200) consists of 6 parallel basic gain units based on a differential common source amplifier with normalized size of 1x to 32x, and realizes sufficient gain control range and rough gain step adjustment; the third part of circuit (300) is composed of 3 improved multiple parallel equivalent structures, and accurate stride control is achieved; the fourth partial circuit (400) completes the output impedance R_outMatching to a 50 ohm load and implementing differential signals out + and out-to single ended signal RF_outThe conversion of (1).

2. The structure of claim 1, wherein: the amplitude control module (200) ensures that the gain adjustable range is greater than 15dB and provides 1dB stepping; the amplitude control module (300) promotes accurate stepping to 0.5 dB.

3. The structure of claim 1, wherein: the first partial circuit (100) is a broadband input transformer matching network and comprises a first transmission line (101), a second transmission line (102), a first transformer (103) and a first capacitor (104), the first transmission line (101) and the second transmission line (102) form a differential pair, the differential pair is connected with a secondary coil of the first transformer (103) and respectively passes through a positive phase signal in + and a negative phase signal in-, a primary coil of the first transformer (103) is connected with the first capacitor (104) in parallel and then is connected with an input signal RF_in。

4. The structure of claim 1, wherein: the second partial circuit (200) is formed by connecting 6 common source transistor array units in parallel, the array units are formed by a first transistor (201), a second transistor (202), a third transistor (203), a fourth transistor (204), a fifth transistor (205), a sixth transistor (206) and a first inverter (207), the gates of the first transistor (201) and the third transistor (203) are connected with the positive end of the input signal of the first partial circuit (100), the gates of the second transistor (202) and the fourth transistor (204) are connected with the negative end of the input signal of the first partial circuit (100), the drains of the first transistor (201) and the fourth transistor (204) are connected with the positive end of the output signal of the second partial circuit (200), and the drains of the second transistor (202) and the third transistor (203) are connected with the negative end of the output signal of the second partial circuit (200), the fifth transistor (205) and the sixth transistor (206) are used as switching tubes, the grid electrode of the fifth transistor (205) is connected with a digital control signal, and the grid electrode of the sixth transistor (206) is connected with the digital control signal after passing through a first inverter (207).

5. The structure of claim 1, wherein: the third partial circuit (300) is formed by connecting 3 optimized common-gate transistor array units in parallel, each array unit is formed by a first transistor (301), a second transistor (302), a third transistor (303), a fourth transistor (304), a fifth transistor (305), a sixth transistor (306), a seventh transistor (307), an eighth transistor (308), a ninth transistor (309), a tenth transistor (310), an eleventh transistor (311), a twelfth transistor (312), a first inverter (313) and a second inverter (314), the gates of the first transistor (301), the third transistor (303), the seventh transistor (307) and the ninth transistor (309) are connected with the positive end of the input signal of the first partial circuit (100), and the gates of the second transistor (302), the fourth transistor (304), the eighth transistor (308) and the tenth transistor (310) are connected with the negative end of the input signal of the first partial circuit (100), the drains of the first transistor (301), the fourth transistor (304), the seventh transistor (307) and the tenth transistor (310) are connected with the positive end of the output signal of the second partial circuit (200), the drains of the second transistor (302), the third transistor (303), the eighth transistor (308) and the ninth transistor (309) are connected with the negative end of the output signal of the second partial circuit (200), the fifth transistor (305), the sixth transistor (306), the eleventh transistor (311) and the twelfth transistor (312) are used as switch control transistors, the fifth transistor (305) is connected with the output end of the first inverter (313), the sixth transistor (306) and the eleventh transistor (311) are connected with the output end of the second inverter, and the twelfth transistor (312) is connected with the digital control signal.

6. A uhf variable gain amplifier structure according to any one of claims 1 or 3, wherein: the fourth partial circuit (400) is a broadband output transformer matching network, and the circuit composition and connection of the fourth partial circuit are the same as those of the first partial circuit (100).

7. An ultra high frequency variable gain amplifier structure as claimed in any one of claims 1, 3 or 6, wherein: the center tap of the secondary coil of the transformer (103) in the third partial circuit (300) is connected with the bias voltage Vbias, and the center tap of the primary coil of the transformer (403) in the fourth partial circuit (400) is connected with the power supply VDD.

8. The structure of an ultra high frequency variable gain amplifier according to any of claims 1 or 4, characterized in that: the transistor sizes of the 6 common source transistor array units of the second partial circuit (200) are different.

9. The structure of an ultra high frequency variable gain amplifier according to any of claims 1 or 5, characterized by: the transistor sizes of the 3 optimized common source transistor array units of the third partial circuit (300) are different.

10. The structure of an ultra high frequency variable gain amplifier according to any of claims 1 or 5, characterized by: the third sub-circuit (300) is composed of two similar and smaller basic gain cells cell1 and cell2 which are connected in parallel through inverted digital signal control.