CN112039335A - Voltage generator and semiconductor device - Google Patents
Voltage generator and semiconductor device Download PDFInfo
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- CN112039335A CN112039335A CN202010847730.0A CN202010847730A CN112039335A CN 112039335 A CN112039335 A CN 112039335A CN 202010847730 A CN202010847730 A CN 202010847730A CN 112039335 A CN112039335 A CN 112039335A
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- charge pump
- clock signal
- delay circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A voltage generator, comprising: the charge pump circuit comprises N stages of charge pump units connected in parallel and N stages of delay circuits connected with the N stages of charge pump units in a one-to-one mode, wherein the N stages of delay circuits are connected in series; n is an integer greater than or equal to 2; an ith stage delay circuit in the N stages of delay circuits receives a clock signal from an i-1 th stage delay circuit, the clock signal is sent to an ith stage charge pump unit through a first output end of the ith stage delay circuit, and the clock signal is sent to an (i + 1) th stage delay circuit through a second output end of the ith stage delay circuit; and after receiving the clock signal, the ith-stage charge pump unit charges and discharges a capacitor of the ith-stage charge pump unit to generate an output voltage, wherein i takes any value from 1 to N.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a voltage generator and a semiconductor device.
Background
A charge pump (charge pump) uses a capacitor as an energy storage element, and in a semiconductor device, the charge pump pumps charge using the capacitor to generate an output voltage higher than a supply voltage. In embedded applications, the output of the conventional charge pump generates large ripple because the conventional charge pump charges and discharges the capacitor once in one clock cycle, as shown in fig. 1, the conventional charge pump is a conventional charge pumpTwo clock cycles output the waveform diagram of the voltage. In order to reduce the influence of ripple on the subsequent circuit, a larger voltage stabilizing capacitor C needs to be added at the output end of the charge pumpLThis seriously increases the area cost of the semiconductor device.
Disclosure of Invention
The present invention provides a voltage generator and a semiconductor device to solve at least the above technical problems in the prior art.
One aspect of the present invention provides a voltage generator, including:
the charge pump circuit comprises N stages of charge pump units connected in parallel and N stages of delay circuits connected with the N stages of charge pump units in a one-to-one mode, wherein the N stages of delay circuits are connected in series; n is an integer greater than or equal to 2;
an ith stage delay circuit in the N stages of delay circuits receives a clock signal from an i-1 th stage delay circuit, the clock signal is sent to an ith stage charge pump unit through a first output end of the ith stage delay circuit, and the clock signal is sent to an (i + 1) th stage delay circuit through a second output end of the ith stage delay circuit;
and after receiving the clock signal, the ith-stage charge pump unit pumps up the input voltage to generate an output voltage, wherein i takes any value from 1 to N.
Wherein, still include: and the clock starting module generates the clock signal according to a clock period and sends the clock signal to the 1 st stage delay circuit in the N stages of delay circuits.
And the Nth stage delay circuit in the N stages of delay circuits sends a clock signal to the clock starting module through a second output end of the Nth stage delay circuit.
The interval from the generation of the clock signal by the clock starting module to the reception of the clock signal returned by the Nth-stage delay circuit is one clock cycle.
The ith stage charge pump unit receives a clock signal from the (i-1) th stage delay circuit, and after a specific delay, the clock signal is sent to the (i + 1) th stage delay circuit through a second output end of the ith stage charge pump unit.
The specific time delays corresponding to the delay circuits of each stage are the same; the sum of the specific time delays corresponding to each stage of the delay circuit is the clock period.
The output voltage of the 1 st-stage to N-stage charge pump unit is subjected to voltage division feedback network to obtain an intermediate voltage, the intermediate voltage is input into the amplifier, and the intermediate voltage is compared with a reference voltage in the amplifier to obtain a feedback voltage.
And each stage of delay circuit receives the feedback voltage in sequence and adjusts the specific delay of the delay circuit according to the feedback voltage.
After receiving the clock signal, the i-th stage charge pump unit charges and discharges the capacitor of the i-th stage charge pump unit in a clock period corresponding to the clock signal to generate an output voltage.
In another aspect, the present invention further provides a semiconductor device including the above voltage generator.
According to the scheme of the invention, each stage of charge pump unit starts to work after receiving the clock signal, the charge pump unit is charged and discharged in one clock period, and the N stages of charge pump units are sequentially turned on in a delayed manner (turned on when receiving the clock signal), so that the arrival of the peak value of the output voltage of each stage of charge pump unit is different by one phase under the premise that the total capacitance is not changed, the output ripple wave is greatly reduced, and the voltage stabilizing capacitor C at the output end is providedLIt can be greatly reduced, and the area cost of the semiconductor device is greatly saved.
Drawings
Fig. 1 shows a waveform diagram of a conventional charge pump output voltage;
FIG. 2 is a schematic diagram of a voltage generator according to an embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating the output voltage of the voltage generator according to one embodiment of the present invention;
fig. 4 is a schematic structural diagram of a voltage generator according to another embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a voltage generator which comprises: the capacitor of the traditional charge pump is split into a plurality of small capacitors to form a corresponding number of charge pump units, each charge pump unit comprises one split small capacitor, and the total capacitance is kept unchanged. The charge pump units are controlled by one delay circuit in combination with the delay circuits with the same number, so that the charge pump units work in sequence in one clock period, the voltage output by each charge pump unit is the same, and the total voltage output by the charge pump units in one clock period is unchanged. However, as the actual operation time of each small capacitor is reduced and the relative operation frequency is increased, the ripple reflected at the output end of the voltage generator is also reduced. If the ripple of the output end is to be smaller, the capacitor can be split into a larger number of small capacitors.
Fig. 2 is a schematic structural diagram of a voltage generator according to an embodiment of the present invention, which includes:
the charge pump circuit comprises N stages of charge pump units 10 connected in parallel and N stages of delay circuits 20 connected with the N stages of charge pump units 10 in a one-to-one mode, wherein the N stages of delay circuits are connected in series; n is an integer greater than or equal to 2;
the ith stage delay circuit 20 in the N stages of delay circuits 20 receives the clock signal from the (i-1) th stage delay circuit 20, sends the clock signal to the ith stage charge pump unit 10 through the first output terminal of the ith stage delay circuit 20, and sends the clock signal to the (i + 1) th stage delay circuit 20 through the second output terminal of the ith stage delay circuit;
after receiving the clock signal, the i-th stage charge pump unit 10 pumps up the input voltage to generate an output voltage, where i is any value from 1 to N.
In this embodiment, a large capacitor of a conventional charge pump is split into N small capacitors to form N stages of charge pump units 10, each stage of charge pump unit 10 includes a small capacitor, and the total capacitance of the N stages of charge pump units 10 is the same as that of the large capacitor. N is an integer greater than or equal to 2, that is, the capacitance generator of the embodiment of the present invention includes at least 2 charge pump units 10.
A charge pump unit 10 is connected with a delay circuit 20, and the operation (capacitor charging and discharging) of the charge pump unit 10 is controlled by the delay circuit 20: after receiving the clock signal, the delay circuit 20 sends the clock signal to the connected charge pump unit 10 through its own first output terminal, and after receiving the clock signal, the charge pump unit 10 starts to charge and discharge the capacitor, that is, after pumping up the input voltage, the output voltage higher than the input voltage is generated, and the duration is one clock cycle.
The delay circuits 20 are connected in series, and the current delay circuit 20 sends the received clock signal to the next stage of delay circuit 20 through its second output terminal.
It should be noted that the clock signal of the stage 1 delay circuit comes from the clock start module 30, and the clock start module 30 generates the clock signal according to the clock cycle and sends the clock signal to the stage 1 delay circuit. The clock signals of the other delay circuits 20 come from the delay circuit 20 of the previous stage. The last stage of delay circuit 20, that is, the nth stage of delay circuit 20, sends the clock signal to the clock starting module 30 through its second output terminal.
Therefore, the clock signal is generated by the clock starting module 30, passes through a set of delay circuits 20 connected in series, and is finally fed back to the clock starting module 30 to form a loop, and the duration of the loop is one clock cycle, that is, the interval from the generation of the clock signal by the clock starting module 30 to the reception of the clock signal returned by the nth-stage delay circuit 20 is one clock cycle. Each stage of the delay circuits 20 receives a clock signal and sends the clock signal to the next stage of the delay circuit 20 after a specific delay, and the sum of the specific delays corresponding to each stage of the delay circuit 20 is one clock cycle. In one embodiment, the specific time delays corresponding to each stage of delay circuit 20 are equal, and the N stages of delay circuits 20 are each divided by one clock cycle.
As can be seen from the foregoing embodiments of the present invention, each stage of charge pump unit 10 starts to operate after receiving a clock signal, and charges and discharges in one clock cycle, and the N stages of charge pump units 10 are sequentially turned on in a delayed manner (turned on when receiving the clock signal), and the clock signals received by the no stage of charge pump units 10 have a phase difference, so that the arrival of the peak value of the output voltage of each stage of charge pump unit 10 has a phase difference on the premise that the total capacitance is not changed, as shown in fig. 3, 1. Compared with the existing charge pump which completes charging and discharging in one clock cycle (the waveform is shown as 2 in fig. 3), the output ripple of the voltage generator of the embodiment of the invention is greatly reduced, so that the voltage stabilizing capacitor C at the output endLIt can be greatly reduced, and the area cost of the semiconductor device is greatly saved.
Because the actual output voltage and the target output voltage have a difference, in order to ensure the stability of the output voltage of the charge pump, the actual output voltage needs to be adjusted to be stabilized at the target output voltage.
As shown in fig. 4, the voltage generator according to the embodiment of the present invention further includes a voltage division feedback network 40 and an amplifier 50, wherein the output voltage of the 1 st to N st stages of charge pump units is processed by the voltage division feedback network 40 to obtain an intermediate voltage, the intermediate voltage is input to the amplifier 50, and an input reference voltage is also present in the amplifier 50, the intermediate voltage and the reference voltage are compared in the amplifier 50 to obtain a feedback voltage, the feedback voltage sequentially acts on the delay circuit 20 of each stage to enable the delay circuit 20 of each stage to adjust its own specific delay, so as to change the clock period and the clock frequency, thereby achieving the purpose of adjusting the output voltage of the charge pump unit 10 of each stage, and the clock start module 30 can generate the clock signal according to the adjusted clock period.
Each stage of delay circuit 20 adjusts its own specific delay after receiving the feedback voltage, and includes:
if the feedback voltage represents that the reference voltage > the intermediate voltage, it means that the total output voltage of the 1 st-N stage charge pump units is lower than the target output voltage, then the feedback voltage acts on each stage of delay circuit 20, so that the specific delay of each stage of delay circuit 20 is reduced, thus the clock period is reduced, the clock frequency is increased, after each stage of charge pump unit receives the clock signal, the number of charging and discharging times in one clock period is increased, the purpose of raising the output voltage is achieved, and the output voltage is closer to the target output voltage.
If the feedback voltage represents the reference voltage < the intermediate voltage, it means that the total output voltage of the 1 st to N th stages of charge pump units is higher than the target output voltage, then the feedback voltage acts on each stage of delay circuit 20 to increase the specific delay of each stage of delay circuit 20, so that the clock period is increased, the clock frequency is decreased, and after each stage of charge pump unit receives the clock signal, the number of charging and discharging times in one clock period is decreased, thereby achieving the purpose of reducing the output voltage and making the output voltage closer to the target output voltage.
If the feedback voltage represents that the reference voltage is equal to the intermediate voltage, this means that the total output voltage of the 1 st to N th stages of charge pump units is the target output voltage calibrated by the reference voltage, and the delay circuit 20 of each stage can keep the specific delay unchanged according to the action of the feedback voltage.
As described above, the specific delay of each stage of the delay circuit 20 is adjusted by the feedback voltage, and the clock period is the sum of the specific delays of each stage. Since the number of stages is not changed, the phase relationship between the clock signals output to the charge pump units 10 of each stage is not changed, but the clock frequency is changed under the adjustment of the feedback voltage, so as to control the charge transfer frequency of the charge pump units of each stage (i.e. the number of charging and discharging times of the charge pump units 10 in one clock cycle), so that the output voltage can be adjusted by changing the reference voltage.
The voltage generator can be applied to a semiconductor device, and for this reason, the embodiment of the invention also provides a semiconductor device including the voltage generator.
The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.
The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
It should also be noted that in the devices, apparatuses, and methods of the present application, the components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered as equivalents of the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. A voltage generator, comprising:
the charge pump circuit comprises N stages of charge pump units connected in parallel and N stages of delay circuits connected with the N stages of charge pump units in a one-to-one mode, wherein the N stages of delay circuits are connected in series; n is an integer greater than or equal to 2;
an ith stage delay circuit in the N stages of delay circuits receives a clock signal from an i-1 th stage delay circuit, the clock signal is sent to an ith stage charge pump unit through a first output end of the ith stage delay circuit, and the clock signal is sent to an (i + 1) th stage delay circuit through a second output end of the ith stage delay circuit;
and after receiving the clock signal, the ith-stage charge pump unit charges and discharges a capacitor of the ith-stage charge pump unit to generate an output voltage, wherein i takes any value from 1 to N.
2. The voltage generator of claim 1, further comprising: and the clock starting module generates the clock signal according to a clock period and sends the clock signal to the 1 st stage delay circuit in the N stages of delay circuits.
3. Voltage generator according to claim 2,
and an Nth stage delay circuit in the N stages of delay circuits sends a clock signal to the clock starting module through a second output end of the Nth stage delay circuit.
4. Voltage generator according to claim 3,
the interval from the clock signal generated by the clock starting module to the clock signal returned by the Nth-stage delay circuit is one clock cycle.
5. The voltage generator of claim 4, wherein the i-th stage charge pump unit receives the clock signal from the i-1-th stage delay circuit, and after a certain delay, sends the clock signal to the i + 1-th stage delay circuit through its second output terminal.
6. The voltage generator of claim 5, wherein the specific time delays corresponding to the time delay circuits of each stage are the same; the sum of the specific time delays corresponding to each stage of the delay circuit is the clock period.
7. The voltage generator of claim 6, further comprising a voltage dividing feedback network and an amplifier, wherein the output voltage of the 1 st to N st stages of charge pump units is passed through the voltage dividing feedback network to obtain an intermediate voltage, the intermediate voltage is inputted to the amplifier, and the intermediate voltage is compared with a reference voltage in the amplifier to obtain a feedback voltage.
8. The voltage generator of claim 7, wherein each stage of the delay circuit receives the feedback voltage in turn and adjusts its own specific delay according to the feedback voltage.
9. The voltage generator according to claim 6 or 8, wherein the i-th stage charge pump unit charges and discharges its own capacitor in a clock cycle corresponding to the clock signal after receiving the clock signal, so as to generate the output voltage.
10. A semiconductor device comprising a voltage generator according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010847730.0A CN112039335A (en) | 2020-08-21 | 2020-08-21 | Voltage generator and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010847730.0A CN112039335A (en) | 2020-08-21 | 2020-08-21 | Voltage generator and semiconductor device |
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| CN112039335A true CN112039335A (en) | 2020-12-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010847730.0A Pending CN112039335A (en) | 2020-08-21 | 2020-08-21 | Voltage generator and semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636589A (en) * | 2020-12-31 | 2021-04-09 | 深圳市芯天下技术有限公司 | Circuit for reducing output voltage ripple of charge pump |
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| US20080191786A1 (en) * | 2007-02-12 | 2008-08-14 | Samsung Electronics Co., Ltd. | High voltage generation circuit and method for generating high voltage |
| US20100308901A1 (en) * | 2009-06-05 | 2010-12-09 | Jae-Hyuk Im | Internal voltage generating circuit |
| CN104541220A (en) * | 2012-07-09 | 2015-04-22 | 斯兰纳半导体美国股份有限公司 | Charge pump regulator circuit |
| CN108418419A (en) * | 2018-04-17 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | Charge pump |
| CN108964446A (en) * | 2016-05-25 | 2018-12-07 | 力旺电子股份有限公司 | Charge pump unit and charge pump circuit |
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2020
- 2020-08-21 CN CN202010847730.0A patent/CN112039335A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080191786A1 (en) * | 2007-02-12 | 2008-08-14 | Samsung Electronics Co., Ltd. | High voltage generation circuit and method for generating high voltage |
| US20100308901A1 (en) * | 2009-06-05 | 2010-12-09 | Jae-Hyuk Im | Internal voltage generating circuit |
| CN104541220A (en) * | 2012-07-09 | 2015-04-22 | 斯兰纳半导体美国股份有限公司 | Charge pump regulator circuit |
| CN108964446A (en) * | 2016-05-25 | 2018-12-07 | 力旺电子股份有限公司 | Charge pump unit and charge pump circuit |
| CN108418419A (en) * | 2018-04-17 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | Charge pump |
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| CN112636589A (en) * | 2020-12-31 | 2021-04-09 | 深圳市芯天下技术有限公司 | Circuit for reducing output voltage ripple of charge pump |
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