CN112038293A - Reverse adjustment method for P-type polysilicon resistor and P-type diffusion region resistor in CMOS (complementary Metal oxide semiconductor) process - Google Patents
Reverse adjustment method for P-type polysilicon resistor and P-type diffusion region resistor in CMOS (complementary Metal oxide semiconductor) process Download PDFInfo
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 145
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 145
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 64
- 230000008569 process Effects 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 230000000295 complement effect Effects 0.000 title abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 6
- 150000004706 metal oxides Chemical class 0.000 title abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- -1 fluorine ions Chemical class 0.000 claims abstract description 21
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 18
- 239000011737 fluorine Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 17
- 238000005468 ion implantation Methods 0.000 abstract description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
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- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
The invention provides a reverse adjustment method for a P-type polycrystalline silicon resistor and a P-type diffusion region resistor in a CMOS (complementary metal oxide semiconductor) process, which is used for forming a diffusion region of the P-type diffusion region resistor; forming a polysilicon structure of the P-type polysilicon resistor; in the process of ion implantation of a source drain region in a CMOS (complementary metal oxide semiconductor) process, fluorine ions with the energy of 8keV are implanted into a diffusion region and a polycrystalline silicon structure; covering a layer of SAB structure on the polysilicon structure, and exposing two ends of the polysilicon structure; covering a layer of SAB structure on the diffusion region, and exposing two ends of the diffusion region; contact holes are respectively formed in the exposed parts at the two ends of the polycrystalline silicon structure and the exposed parts at the two ends of the diffusion region. The invention adjusts the energy of the fluorine ions which are jointly injected in the forming process of the source and drain regions of the MOSFET device, and simultaneously changes the grain size in the P-type polycrystalline silicon and the concentration distribution of the boron ions in the diffusion region, thereby realizing the reverse adjustment of the resistance values of the P-type polycrystalline silicon resistor and the P-type diffusion region resistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a reverse adjustment method for a P-type polycrystalline silicon resistor and a P-type diffusion region resistor in a CMOS (complementary metal oxide semiconductor) process.
Background
Resistors are an important component of digital and analog CMOS integrated circuits, and their main functions are current limiting and voltage dividing. The resistor can be divided into an active resistor and a passive resistor, wherein the active resistor usually utilizes the resistance characteristic of the transistor in a specific working area, and the passive resistor is usually formed by doping, such as a polysilicon resistor, a diffusion area resistor, and the like. Since the passive resistor is not affected by the current voltage and has stable performance, the passive resistor is used in most integrated circuit designs.
The resistance of the passive resistor is mainly determined by doping and heat treatment processes. In a standard CMOS process, polysilicon resistors and diffusion resistors are typically formed by source drain ion implantation of the MOSFET device and separate polysilicon ion implantation, and for P-type resistors, the dopant element is typically boron. The resistance values of the P-type polycrystalline silicon resistor and the diffusion region resistor are in inverse proportion to the dosage of boron, namely the higher the dosage of boron is, the lower the resistance value of the resistor is. Therefore, adjusting the implantation conditions of the boron ions can increase or decrease the resistance values of the p-type polysilicon resistor and the p-type diffusion region at the same time, and the reverse adjustment of the resistance values of the two resistors cannot be realized.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for adjusting reverse resistance of a P-type polysilicon resistor and a P-type diffusion region in a CMOS process, so as to solve the problem that resistance values of the P-type polysilicon resistor and the P-type diffusion region in the CMOS process in the prior art are increased or decreased at the same time, so that the reverse adjustment of the resistance values of the two resistors cannot be realized.
In order to achieve the above and other related objects, the present invention provides a method for reverse adjusting P-type polysilicon resistance and P-type diffusion resistance in CMOS process, comprising the steps of:
providing a layout of a P-type polycrystalline silicon resistor and a layout of a P-type diffusion region resistor;
forming an active area of a CMOS device in a CMOS process, and forming a diffusion area of the P-type diffusion area resistor by using the layout of the P-type diffusion area resistor;
forming a polysilicon structure of the P-type polysilicon resistor by using the layout of the P-type polysilicon resistor while forming the gate polysilicon of the CMOS device in the CMOS process;
implanting fluorine ions into the diffusion region of the P-type diffusion region resistor and the polycrystalline silicon structure of the P-type polycrystalline silicon resistor in the process of implanting ions into the source and drain regions of the CMOS device in the CMOS process, wherein the implantation energy of the fluorine ions is 8 keV;
covering a layer of SAB structure on the polycrystalline silicon structure of the P-type polycrystalline silicon resistor by using the layout of the P-type polycrystalline silicon resistor, and exposing two ends of the polycrystalline silicon structure; covering a layer of SAB structure on the diffusion region of the diffusion region resistor by using the layout of the P-type diffusion region resistor, wherein two ends of the diffusion region are exposed;
sixthly, respectively forming contact holes in the parts exposed out of the two ends of the polycrystalline silicon structure by utilizing the layout of the P-type polycrystalline silicon resistor; and respectively forming contact holes in the parts exposed at the two ends of the diffusion region by utilizing the layout of the P-type diffusion region resistor.
Preferably, the layout of the P-type polysilicon resistor in the first step at least includes: a polysilicon layer, an SAB layer and a contact hole layer from bottom to top; the polycrystalline silicon layer comprises a rectangular polycrystalline silicon structure graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular polycrystalline silicon structure graph, and meanwhile, two ends of the polycrystalline silicon structure graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the polysilicon structure graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the polysilicon structure pattern.
Preferably, the layout of the P-type diffusion region resistor in the first step at least includes: a bottom-up diffusion region layer, an SAB layer, and a contact hole layer; the diffusion region layer comprises a rectangular diffusion region graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular diffusion region graph, and meanwhile, two ends of the diffusion region graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the diffusion region graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the diffusion region patterns.
Preferably, after a layer of SAB structure is formed on the polysilicon structure of the P-type polysilicon resistor and on the diffusion region of the P-type diffusion region resistor, respectively, a layer of metal silicide is formed on the polysilicon structure and the diffusion region except for the SAB structure.
Preferably, the method further comprises a seventh step of filling metal in the contact hole to form an electrode.
Preferably, the method further comprises the step eight of testing the resistance value of the P-type polycrystalline silicon resistor and the resistance value of the P-type diffusion region resistor by using the electrodes.
Preferably, the resistance value of the P-type polysilicon resistor tested in the step eight is 637 ohm/sqr.
Preferably, the resistance of the P-type diffusion region resistor tested in step eight is 269 ohm/sqr.
As described above, the method for adjusting reverse resistance of P-type polysilicon resistor and P-type diffusion region in CMOS process of the present invention has the following advantages: the invention adjusts the energy of the fluorine ions which are jointly injected in the forming process of the source and drain regions of the MOSFET device, and simultaneously changes the grain size in the P-type polycrystalline silicon and the concentration distribution of the boron ions in the diffusion region, thereby realizing the reverse adjustment of the resistance values of the P-type polycrystalline silicon resistor and the P-type diffusion region resistor.
Drawings
FIG. 1 is a schematic diagram of a layout of a P-type polysilicon resistor according to the present invention;
FIG. 2 is a schematic layout diagram of the P-type diffusion resistance of the present invention;
FIG. 3 is a schematic diagram of resistance values of polysilicon under different fluorine ion implantation energies;
FIG. 4 is a schematic diagram showing the resistance of the diffusion region under different fluorine ion implantation energies;
FIG. 5 is a flow chart of a method for reverse adjustment of P-type polysilicon resistance and P-type diffusion resistance in a CMOS process according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for reversely adjusting a P-type polysilicon resistor and a P-type diffusion region resistor in a CMOS (complementary metal oxide semiconductor) process, as shown in FIG. 5, FIG. 5 is a flow chart of the method for reversely adjusting the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process. The method at least comprises the following steps:
providing a layout of a P-type polycrystalline silicon resistor and a layout of a P-type diffusion region resistor; further, the layout of the P-type polysilicon resistor in the invention at least comprises: a polysilicon layer, an SAB layer and a contact hole layer from bottom to top; the polycrystalline silicon layer comprises a rectangular polycrystalline silicon structure graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular polycrystalline silicon structure graph, and meanwhile, two ends of the polycrystalline silicon structure graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the polysilicon structure graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the polysilicon structure pattern. In this embodiment, the layout of the P-type polysilicon resistor is as shown in fig. 1, the polysilicon layer, the SAB layer and the contact hole layer are sequentially stacked from bottom to top, wherein a rectangular polysilicon structure pattern (poly in fig. 1) is disposed on the polysilicon layer, the SAB layer includes a rectangular SAB structure pattern (SAB in fig. 1), two contact hole patterns (CT in fig. 1) are disposed on the contact hole layer, as shown in fig. 1, the rectangular SAB structure pattern (SAB) covers a middle section of the rectangular polysilicon structure pattern (poly), that is, other portions are covered by the SAB except for two ends of the poly, and a long side of the rectangular SAB structure pattern extends away from a long side of the polysilicon structure pattern. The contact hole patterns CT on the contact hole layer cover both ends of the exposed poly, and the CTs are projected to the range within the both end patterns of the exposed poly.
Further, the layout of the P-type diffusion region resistor in the first step at least comprises: a bottom-up diffusion region layer, an SAB layer, and a contact hole layer; the diffusion region layer comprises a rectangular diffusion region graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular diffusion region graph, and meanwhile, two ends of the diffusion region graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the diffusion region graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the diffusion region patterns.
In this embodiment, the layout of the P-type diffusion resistance is as shown in fig. 2, the diffusion layer, the SAB layer and the contact hole layer are sequentially stacked from bottom to top, wherein a rectangular diffusion region pattern (AA in fig. 2) is disposed on the diffusion layer, the SAB layer includes a rectangular SAB structure pattern (SAB in fig. 2), two contact hole patterns (CT in fig. 2) are disposed on the contact hole layer, as shown in fig. 2, the rectangular SAB structure pattern (SAB) covers a middle section of the rectangular diffusion region pattern (AA), that is, other parts except two end portions of the AA are covered by the SAB, and a long side of the rectangular SAB structure pattern extends away from a long side of the diffusion region pattern AA. The contact hole patterns CT on the contact hole layer cover two ends of the exposed AA, and the CT is projected to the range within the two end patterns of the exposed AA.
Forming an active area of a CMOS device in a CMOS process, and forming a diffusion area of the P-type diffusion area resistor by using the layout of the P-type diffusion area resistor; that is, the diffusion region of the P-type diffusion region resistor is formed by using the diffusion region pattern AA in the layout of the P-type diffusion region resistor as shown in fig. 2.
Forming a polysilicon structure of the P-type polysilicon resistor by using the layout of the P-type polysilicon resistor while forming the gate polysilicon of the CMOS device in the CMOS process; that is, the polysilicon structure of the P-type polysilicon resistor is formed by using the polysilicon structure pattern in the layout of the P-type polysilicon resistor as shown in fig. 1.
Implanting fluorine ions into the diffusion region of the P-type diffusion region resistor and the polycrystalline silicon structure of the P-type polycrystalline silicon resistor in the process of implanting ions into the source and drain regions of the CMOS device in the CMOS process, wherein the implantation energy of the fluorine ions is 8 keV; the fourth step of the invention increases the traditional fluorine ion implantation energy from 5KeV to 8keV, and the fourth step jointly implants the energy of the fluorine ions in the CMOS device source-drain ion implantation process. Fluorine ions act differently in polysilicon and in the diffusion region: fluorine ions in polysilicon can increase the grain size, which directly causes increased grain boundary carrier mobility and reduced polysilicon resistance. In the diffusion zone, on one hand, fluorine ions and vacancies are combined to form F-V clusters, and the clusters can trap gaps (boron is generally combined and diffused with the gaps in silicon), so that the diffusion of boron in silicon is inhibited, and the effective boron concentration is reduced; on the other hand, fluorine enhances the diffusion of boron ions in silicon dioxide and forms fluorine-boron clusters at the silicon dioxide-silicon interface, resulting in a loss of the effective dose of boron element in silicon and an increase in diffusion region resistance. Therefore, when the fluorine ion implantation energy is increased, namely the concentration peak value is deepened and the total dose is increased, the average grain size in the polycrystalline silicon is further increased, the resistance of the polycrystalline silicon is reduced, and meanwhile, the inhibition effect of fluorine in the diffusion area on boron is more obvious, namely, the effective boron concentration in silicon is further reduced, the resistance of the diffusion area is increased, and finally the resistance of p-type polycrystalline on the resistance and the resistance of p-type diffusion area are reversely adjusted. As shown in fig. 3 and 4, fig. 3 is a schematic diagram of resistance values of polysilicon under different fluorine ion implantation energies; fig. 4 is a diagram showing the resistance of the diffusion region under different fluorine ion implantation energies. Therefore, when the fluorine energy is increased from 5K to 8K, the polysilicon resistance is decreased from 717ohm/sqr to 637ohm/sqr by about 11%, and the diffusion resistance is increased from 264ohm/sqr to 269ohm/sqr by about 2%. The P-type polysilicon resistor and the P-type diffusion region resistor realize reverse regulation.
Covering a layer of SAB structure on the polycrystalline silicon structure of the P-type polycrystalline silicon resistor by using the layout of the P-type polycrystalline silicon resistor, and exposing two ends of the polycrystalline silicon structure; covering a layer of SAB structure on the diffusion region of the diffusion region resistor by using the layout of the P-type diffusion region resistor, wherein two ends of the diffusion region are exposed; forming a layer of SAB structure on the polysilicon structure of the P-type polysilicon resistor by using the SAB structure graph in the layout of the P-type polysilicon resistor; and forming a layer of SAB structure on the diffusion region of the diffusion region resistor by utilizing an SAB structure graph in the layout of the P-type diffusion region resistor, wherein the SAB structure on the polysilicon structure of the P-type polysilicon resistor and the SAB structure on the diffusion region of the P-type diffusion region resistor are formed synchronously.
Further, after a layer of SAB structure is formed on the polysilicon structure of the P-type polysilicon resistor and on the diffusion region of the P-type diffusion region resistor, respectively, a layer of metal silicide is formed on the polysilicon structure and the diffusion region except the SAB structure. The SAB structure in the present invention is an oxynitride used to block the formation of metal silicide, and therefore the metal silicide will not be formed in the area covered by the SAB structure.
Sixthly, respectively forming contact holes in the parts exposed out of the two ends of the polycrystalline silicon structure by utilizing the layout of the P-type polycrystalline silicon resistor; and respectively forming contact holes in the parts exposed at the two ends of the diffusion region by utilizing the layout of the P-type diffusion region resistor. Contact holes are respectively formed in the exposed parts at the two ends of the polycrystalline silicon structure by utilizing the contact hole patterns in the layout of the P-type polycrystalline silicon resistor; and respectively forming contact holes at the parts exposed at the two ends of the diffusion region by using the contact hole pattern in the layout of the P-type diffusion region resistor. The contact hole of the P-type polycrystalline silicon resistor and the contact hole of the P-type diffusion region resistor are formed synchronously.
Further, the method also comprises a seventh step of filling metal in the contact hole to form an electrode. And step eight, testing the resistance value of the P-type polycrystalline silicon resistor and the resistance value of the P-type diffusion region resistor by using the electrode. As shown in fig. 3 and 4, the resistance value of the P-type polysilicon resistor tested in step eight is 637 ohm/sql r. And the resistance value of the P-type diffusion region resistor tested in the step eight is 269 ohm/sqr.
The type polysilicon resistor and the p-type diffusion region resistor manufactured and formed by the invention are two independent resistors on the same die, and the two resistors are equivalent to two independent parasitic devices of a CMOS device in the invention. And increasing the energy of the fluorine ions in combined implantation in the ion implantation process of the source and drain regions of the CMOS device. In the diffusion region, the diffusion of boron ions can be further inhibited by increasing the implantation energy of fluorine ions, and more boron dose loss is caused, so that the effective boron concentration in the diffusion region is reduced, and the resistance is increased; in the polysilicon, increasing the fluorine ion implantation energy can increase the grain size, improve the grain boundary carrier mobility, and further reduce the polysilicon resistance.
In summary, the invention adjusts the energy of the fluorine ion combined injection in the process of forming the source and drain regions of the MOSFET device, and simultaneously changes the grain size in the P-type polycrystalline silicon and the concentration distribution of boron ions in the diffusion region, thereby realizing the reverse adjustment of the resistance values of the P-type polycrystalline silicon resistor and the P-type diffusion region resistor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for reversely adjusting a P-type polysilicon resistor and a P-type diffusion region resistor in a CMOS process is characterized by at least comprising the following steps:
providing a layout of a P-type polycrystalline silicon resistor and a layout of a P-type diffusion region resistor;
forming an active area of a CMOS device in a CMOS process, and forming a diffusion area of the P-type diffusion area resistor by using the layout of the P-type diffusion area resistor;
forming a polysilicon structure of the P-type polysilicon resistor by using the layout of the P-type polysilicon resistor while forming the gate polysilicon of the CMOS device in the CMOS process;
implanting fluorine ions into the diffusion region of the P-type diffusion region resistor and the polycrystalline silicon structure of the P-type polycrystalline silicon resistor in the process of implanting ions into the source and drain regions of the CMOS device in the CMOS process, wherein the implantation energy of the fluorine ions is 8 keV;
covering a layer of SAB structure on the polycrystalline silicon structure of the P-type polycrystalline silicon resistor by using the layout of the P-type polycrystalline silicon resistor, and exposing two ends of the polycrystalline silicon structure; covering a layer of SAB structure on the diffusion region of the diffusion region resistor by using the layout of the P-type diffusion region resistor, and exposing two ends of the diffusion region;
sixthly, respectively forming contact holes in the parts exposed out of the two ends of the polycrystalline silicon structure by utilizing the layout of the P-type polycrystalline silicon resistor; and respectively forming contact holes in the parts exposed at the two ends of the diffusion region by utilizing the layout of the P-type diffusion region resistor.
2. The method of claim 1, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: in the first step, the layout of the P-type polysilicon resistor at least comprises: a polysilicon layer, an SAB layer and a contact hole layer from bottom to top; the polycrystalline silicon layer comprises a rectangular polycrystalline silicon structure graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular polycrystalline silicon structure graph, and meanwhile, two ends of the polycrystalline silicon structure graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the polysilicon structure graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the polysilicon structure pattern.
3. The method of claim 2, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: the layout of the P-type diffusion region resistor in the first step at least comprises the following steps: a bottom-up diffusion region layer, an SAB layer, and a contact hole layer; the diffusion region layer comprises a rectangular diffusion region graph, the SAB layer comprises a rectangular SAB structure graph, and the contact hole layer comprises two contact hole graphs; the rectangular SAB structure graph covers the middle section of the rectangular diffusion region graph, and meanwhile, two ends of the diffusion region graph are exposed; the long edge of the SAB structure graph extends out of the long edge of the diffusion region graph; and the two contact hole patterns on the contact hole layer are respectively overlapped above the two exposed ends of the diffusion region patterns.
4. The method of claim 1, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: and fifthly, after a layer of SAB structure is respectively formed on the polysilicon structure of the P-type polysilicon resistor and the diffusion region of the P-type diffusion region resistor, a layer of metal silicide is formed on the polysilicon structure and the diffusion region except the SAB structure.
5. The method of claim 1, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: the method further comprises a seventh step of filling metal in the contact hole to form an electrode.
6. The method of claim 5, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: the method further comprises the step eight of testing the resistance value of the P-type polycrystalline silicon resistor and the resistance value of the P-type diffusion region resistor by using the electrode.
7. The method of claim 6, wherein the reverse adjustment of the P-type polysilicon resistor and the P-type diffusion region resistor in the CMOS process comprises: and the resistance value of the P-type polycrystalline silicon resistor tested in the step eight is 637 ohm/sqr.
8. The method of claim 7, wherein the reverse adjustment of the P-type polysilicon resistance and the P-type diffusion resistance in the CMOS process comprises: and the resistance value of the P-type diffusion region resistor tested in the step eight is 269 ohm/sqr.
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| CN202010878375.3A CN112038293B (en) | 2020-08-27 | 2020-08-27 | Reverse adjustment method for P-type polysilicon resistor and P-type diffusion region resistor in CMOS (complementary metal oxide semiconductor) process |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0908947A2 (en) * | 1997-09-29 | 1999-04-14 | Matsushita Electronics Corporation | Method for fabricating semiconductor device with pMIS transistor |
| US7776675B1 (en) * | 2007-10-29 | 2010-08-17 | Newport Fab, Llc | Method for forming a reduced resistivity poly gate and related structure |
| US20110266637A1 (en) * | 2010-04-29 | 2011-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Precise Resistor on a Semiconductor Device |
| CN103094109A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0908947A2 (en) * | 1997-09-29 | 1999-04-14 | Matsushita Electronics Corporation | Method for fabricating semiconductor device with pMIS transistor |
| US7776675B1 (en) * | 2007-10-29 | 2010-08-17 | Newport Fab, Llc | Method for forming a reduced resistivity poly gate and related structure |
| US20110266637A1 (en) * | 2010-04-29 | 2011-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Precise Resistor on a Semiconductor Device |
| CN103094109A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
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