CN112037700A - Stress testing device and stress testing method for display panel - Google Patents
Stress testing device and stress testing method for display panel Download PDFInfo
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- CN112037700A CN112037700A CN202010844444.9A CN202010844444A CN112037700A CN 112037700 A CN112037700 A CN 112037700A CN 202010844444 A CN202010844444 A CN 202010844444A CN 112037700 A CN112037700 A CN 112037700A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
The invention provides a stress testing device and a stress testing method of a display panel, wherein the stress testing device is used for testing stress of the display panel in a bending state, the display panel comprises a bending area, the stress testing device comprises a data processing unit and at least one testing thin film transistor electrically connected with the data processing unit, the testing thin film transistor is arranged in the bending area, and the data processing unit is used for receiving output current of the testing thin film transistor in the bending area and calculating the stress of the display panel in the bending area according to the output current.
Description
Technical Field
The present invention relates generally to the field of display technologies, and more particularly, to a stress testing apparatus and a stress testing method for a display panel.
Background
An Organic Light Emitting Diode (OLED) is an autonomous light emitting technology, and compared with a Liquid Crystal Display (LCD), the OLED has the advantages of fast response speed, high contrast, wide viewing angle, low power consumption, flexibility, light weight, thin thickness, simple structure, low cost, and the like, and thus is generally seen in the industry. Among them, the Active-matrix organic light emitting diode (AMOLED) is particularly regarded as important, and besides the advantages of self-luminous property and vivid color, it is also an important feature that it can construct a foldable display panel.
However, in the development of such foldable display panels, a problem of abnormal brightness in the bending region of the display panel is frequently encountered. This is because the display panel is bent by the stress, and thus the conductive characteristics in the bent region are also changed by the stress, resulting in abnormal brightness of the display panel. In addition, in the art, there is no method suitable for testing the stress magnitude of the display panel in the bending region, and thus the above-mentioned brightness abnormality cannot be solved well.
Therefore, it is desirable to provide a measurement means to test the magnitude of the stress experienced by the display panel in its bending region.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a stress testing apparatus and a stress testing method for a display panel, which can calculate the stress level of the display panel in the bending region by measuring the current level generated by the conductive characteristic change of the active layer in the display panel.
In order to achieve the above and other related objects, the present invention provides a stress testing apparatus for a display panel, configured to test a stress applied to the display panel in a bent state, where the display panel includes a bending region, the stress testing apparatus includes a data processing unit and at least one testing thin film transistor electrically connected to the data processing unit, the testing thin film transistor is disposed in the bending region, and the data processing unit is configured to receive an output current of the testing thin film transistor located in the bending region, and calculate the stress applied to the display panel in the bending region according to the output current.
In some embodiments, the display panel comprises a display area and a non-display area adjacent to the display area, the display panel comprises a substrate layer, and the test thin film transistor is arranged on the substrate layer and located in the non-display area;
the thin film transistor for testing includes:
the grid metal layer is arranged on the substrate layer and comprises a grid and a grid signal input end connected with the grid;
an active layer disposed on the substrate layer;
the grid electrode insulating layer is arranged on the substrate layer and is arranged between the grid electrode metal layer and the active layer;
the interlayer dielectric layer is arranged on the substrate layer, the active layer and the grid metal layer; and
and the source and drain electrode layer is arranged on the interlayer dielectric layer and comprises a source electrode, a drain electrode, a signal input end connected with the source electrode and a current collecting end connected with the drain electrode, two ends of the active layer are respectively connected with the source electrode and the drain electrode, and the current collecting end is connected with the data processing unit.
In some embodiments, the display panel includes at least one bending axis located in the bending region, and at least one thin film transistor for testing is correspondingly disposed at any one of the bending axes.
In some embodiments, one of the thin film transistors for testing is disposed at one of the bending axes, and the active layer in the thin film transistor for testing is disposed on the substrate layer with the bending axis as a symmetry axis.
In some embodiments, a plurality of the thin film transistors for testing are correspondingly arranged at one bending axis, and the active layer in the plurality of the thin film transistors for testing is arranged on the substrate layer with the bending axis as a symmetry axis.
In some embodiments, the gate metal layer further includes a bridging trace disposed on the substrate layer, and the current collecting terminal is connected to the data processing unit through the bridging trace.
In some embodiments, a via hole is formed in the interlayer dielectric layer, one end of the bridging wire penetrates through the via hole to be connected with the current collecting end, and the other end of the bridging wire is connected with the data processing unit.
Another aspect of the present invention provides a method for testing stress of a display panel, in which a stress testing apparatus for a display panel is used to test stress applied to the display panel, the method including the following steps:
enabling the display panel to be in a bent state, driving the thin film transistor for testing, and detecting the output current of the thin film transistor for testing in the bent area;
and calculating the stress of the display panel in the bending area according to the output current.
In some embodiments, the driving the test thin film transistor includes: and inputting a data signal at the signal input end of the source drain layer, and inputting a driving signal at the gate signal input end of the gate metal layer.
In some embodiments, the calculating the stress σ applied to the display panel in the bending region according to the output current includes calculating a stress σ applied to the display panel in the bending region:
σ＝2Ids/K1*cox(W/L)(Vgs-Vth)2
and Ids is the output current, K1 is a proportionality coefficient, cox is a unit gate oxide capacitance, W/L is the width-to-length ratio of the channel of the thin film transistor for testing, Vgs is the voltage between the gate and the source, and Vth is the threshold voltage of the thin film transistor for testing.
According to the stress testing device and the stress testing method for the display panel, when the display panel is in a bent state due to stress, the magnitude of current generated by the change of the conductive characteristic of the active layer of the thin film transistor for testing in the bent area can be detected, the data processing unit is used for receiving the output current, and the stress of the display panel in the bent area is calculated according to the output current.
Drawings
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which it is noted that the drawings are not necessarily to scale and that, for purposes of clarity of illustration, some features may be exaggerated or minimized in the drawings, in which:
fig. 1 is a schematic view of a stress testing apparatus of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged top view of a stress testing apparatus according to an embodiment of the present invention;
FIG. 3 is an enlarged sectional view taken along line A-A of FIG. 2;
FIG. 4 is a flow chart for forming the stress testing apparatus shown in FIG. 2 according to one embodiment of the present invention;
fig. 5 is a circuit configuration diagram of a stress testing apparatus of a display panel according to an embodiment of the present invention;
FIG. 6 is a diagram for explaining the relationship between the mobility of an active layer and stress in a stress testing apparatus; and
fig. 7 is a flowchart of a stress testing method of a display panel according to an embodiment of the present invention.
The reference numerals appearing in the figures relate to the following technical features:
100 display panel
101 display area
102 non-display area
110 stress testing device
Thin film transistor for 200 test
201 gate metal layer
202 active layer
203 gate insulating layer
204 interlayer dielectric layer
205 source drain layer
211 gate signal input terminal
212 signal input terminal
213 Current collecting terminal
S401-S407 steps
501 signal input terminal
502 gate signal input terminal
503 current collection terminal
504 data processing unit
510 grid electrode
511 Source
512 drain electrode
S701-S703.
Detailed Description
Aspects and advantages of the invention will be set forth in, or will be apparent from, the following detailed description taken in conjunction with the accompanying drawings, or may be learned by practice of embodiments of the invention.
Reference in the specification to "an embodiment" or "one embodiment" is intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "an embodiment" or "one embodiment" that may be present in various places throughout this specification are not necessarily referring to the same embodiment, but may instead refer to different embodiments. Furthermore, the particular configurations, structures, or features defined in this specification may be combined in any suitable manner, even in ways other than those presented. Reference numerals and spatial references (such as "upper", "lower", etc.) are used herein for convenience only and thus do not limit the scope of protection or the scope of the embodiments. In the drawings, the same reference numerals are used to designate elements similar to or technically equivalent to each other.
Reference now will be made in detail to embodiments of the invention, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the invention, not limitation of the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For instance, features illustrated or described as part of one embodiment, can be used with another embodiment to yield a still further embodiment. It is therefore intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
In the embodiment of the invention, when the display panel is stressed and bent, the active layer of the thin film transistor for testing in the stress testing device is deformed, so that the mobility μ of the active layer is changed, thereby causing the current in the thin film transistor for testing to be changed. Therefore, the magnitude of the stress applied to the display panel in the bending region can be calculated by measuring the magnitude of the current generated by the change of the conductive characteristics of the active layer.
Fig. 1 is a schematic view of a stress testing apparatus 110 of a display panel according to the present invention. As shown, the display panel 100 includes a display area 101 and a non-display area 102 adjacent to the display area 101. Let the lateral direction in fig. 1 be X and the vertical direction be Y. Then, in the non-display area 102 of the display panel 100, 5 stress test devices 110 are provided in total, wherein in the non-display area 102 of the lower side of the display panel 100, 3 stress test devices 110 are provided in the lateral direction X. In the non-display area 102 on the right side of the display panel 100, 2 stress test devices 110 are disposed in the vertical direction Y.
It should be noted that the number and orientation of the stress testing devices 110 arranged in fig. 1 are merely exemplary and can be modified as desired.
As shown in fig. 1, in the bent state, the display panel 100 may be bent along a bending axis C1 or C2 (shown by a dotted line in fig. 1), so that a bending region is formed on both sides of the bending axis C1 or C2, and the stress testing device 110 is disposed in the bending region and oriented parallel to the bending axis C1 or C2, and by detecting the current in the stress testing device 110 in the bending region of the display panel 100, the magnitude of the stress applied to the display panel 100 in the bending region can be calculated.
Hereinafter, the detailed description will be made with reference to fig. 2 to 6.
Fig. 2 is an enlarged top view of a stress testing apparatus 110 according to the present invention. In one embodiment of the present invention, the stress testing apparatus 110 includes a data processing unit 504 (described in detail later with reference to fig. 5) and at least one testing thin film transistor 200 (in fig. 2, 4 testing thin film transistors 200 are shown) electrically connected to the data processing unit 504. The display panel 100 includes a substrate layer, and the testing thin film transistor 200 is disposed on the substrate layer and located in the non-display region 102. The thin film transistor 200 for test includes: a gate metal layer 201 disposed on the substrate layer, the gate metal layer 201 including a gate 510 (shown in fig. 5) and a gate signal input terminal 211 connected to the gate 510; an active layer 202 disposed on the substrate layer; a gate insulating layer 203 arranged on the substrate layer, wherein the gate insulating layer 203 is arranged between the gate metal layer 201 and the active layer 202; the interlayer dielectric layer 204 is arranged on the substrate layer, the active layer 202 and the grid metal layer 201; and a source/drain layer 205 disposed on the interlayer dielectric layer 204 and including a source 511, a drain 512 (shown in fig. 5), a signal input terminal 212 connected to the source 511, and a current collecting terminal 213 connected to the drain 512, wherein two ends of the active layer 205 are respectively connected to the source 511 and the drain 512, and the current collecting terminal 213 is connected to the data processing unit 504.
It should be noted that the display panel 100 includes at least one bending axis located in the bending region, and at least one testing thin film transistor 200 is correspondingly disposed at any bending axis. Preferably, one thin film transistor 200 for testing is correspondingly disposed at one bending axis, and the active layer 202 in the thin film transistor 200 for testing is disposed on the substrate layer with the bending axis as a symmetry axis. Alternatively, a plurality of thin film transistors 200 for testing are correspondingly arranged at one bending axis, and the active layer 202 in the plurality of thin film transistors 200 for testing is arranged on the substrate layer with the bending axis as a symmetry axis. When a plurality of test tfts 200 are provided corresponding to one bending axis, the calculation can be performed by obtaining the average value of the current output from each test tft 200 at the time of detection.
In addition, in the embodiment shown in fig. 2, the stress testing apparatus 110 includes four testing thin film transistors 200, which may be formed in a symmetrical structure with respect to the bending axis and oriented parallel to the bending axis C1, and at the time of detection, calculation is performed by taking an average value of the current output from each of the testing thin film transistors 200.
However, this is merely exemplary, and the number and arrangement of the test thin film transistors 200 can be changed as necessary.
In addition, the gate metal layer 201 further includes a bridge trace 206 (shown in fig. 3) disposed on the substrate layer, and the current collecting terminal 213 is connected to the data processing unit 504 through the bridge trace 206. Specifically, as shown in fig. 3, fig. 3 is an enlarged cross-sectional view taken along line a-a in fig. 2, a via V is disposed on the interlayer dielectric layer 204, one end of the bridging trace 206 passes through the via V to be connected to the current collecting end 213, and the other end of the bridging trace 206 is connected to the data processing unit 504.
Fig. 4 is a flow chart for forming the stress testing apparatus 110 shown in fig. 2 according to the present invention, in step S401, a substrate is provided, and a substrate layer is deposited on the substrate. In some embodiments, the substrate can be a glass substrate, and the substrate layer can be SiO2。
Next, in step S402, on the substrate layer, a gate metal layer 201 is formed by deposition and photolithography processes.
Next, in steps S403 to S405, the gate insulating layer 203, the active layer 202, and the interlayer dielectric layer 204 are formed by deposition, a photolithography process, and the like, wherein the gate insulating layer 203 is disposed between the gate metal layer 201 and the active layer 202. Preferably, the active layer 202 is a polysilicon layer. Alternatively, the gate metal layer 201, the active layer 202, and the gate insulating layer 203 are formed on the same plane on the substrate layer.
Next, in step S406, the source drain layer 205 is formed by deposition and photolithography processes.
Thereby, the stress test apparatus 110 shown in fig. 2 is formed. Preferably, the stress test apparatus 110 is formed at the same time as the thin film transistor panel of the display panel is formed.
Hereinafter, a method of testing the stress applied to the display panel 100 by the stress testing apparatus 110 will be described with reference to fig. 5 to 7. Fig. 5 is a circuit configuration diagram of the stress testing apparatus 110 for the display panel 100 according to the present invention; fig. 6 is a schematic diagram for explaining the relationship between the mobility of the active layer and the stress in the stress testing apparatus 110; fig. 7 is a flowchart of a stress testing method of a display panel according to an embodiment of the present invention.
As shown in fig. 5, the stress testing apparatus 110 includes a signal input terminal 501, a gate signal input terminal 502, a current collecting terminal 503, and a data processing unit 504. In addition, the stress testing apparatus 110 further includes a gate 510, a source 511, and a drain 512. The data processing unit 504 is electrically connected to at least one test thin film transistor 200 (6 in fig. 5), and the data processing unit 504 is configured to receive an output current of the test thin film transistor 200 located in the bending region and calculate a stress in the bending region according to the output current.
When the display panel 100 is bent along a bending line (for example, the dashed line C1 in fig. 1), the stress test device 110 located in the bending region on both sides of the bending line is stressed, so that the active layer 202 at the position of the stress test device 110 is deformed, and the mobility μ thereof changes, thereby causing the current detected by the current collecting terminal 503 to change.
In the stress testing method of the display panel, as shown in fig. 7, the method includes the following steps: s701, the display panel 100 is in a bent state, specifically, the display panel 100 is bent along a bending axis under the action of stress, and bending regions are formed on two sides of the bending axis; s702, driving the thin film transistor 200 for testing, wherein the thin film transistor 200 for driving testing is located in the bending region of the display panel 100; s703, detecting an output current of the thin film transistor 200 for testing in the bending region; and S704, calculating the stress of the display panel 100 in the bending region according to the output current. The step of driving the thin film transistor 200 for testing may further include: a data signal is input to the signal input terminal 212 of the source-drain layer 205, and a drive signal is input to the gate signal input terminal 211 of the gate metal layer 201.
Specifically, as shown in fig. 5, by inputting voltages to the signal input terminal 501 and the gate signal input terminal 502, the thin film transistor 200 for testing in the stress testing device 110 can be turned on, and the thin film transistor 200 for testing can be operated in the saturation region. In some embodiments, the thin film transistor 200 for testing is a p-type transistor, the active layer 202 is polysilicon, the input gate voltage Vg is-2 v, the signal input terminal voltage Vd is 4v, and the current Ids in the saturation region satisfies the following formula 1:
Ids＝1/2μcox(W/L)(Vgs-Vth)2(formula 1) of (A) and (B),
where μ is the mobility of polysilicon, cox is the unit gate-oxide capacitance, W/L is the width-to-length ratio of the thin film transistor 200 for testing, Vgs is the voltage between the gate and source, and Vth is the threshold voltage of the thin film transistor 200 for testing. In some embodiments, the width W of the test TFT 200 is 5-20 μm and the length L is 5-10 μm.
From equation 1, the mobility μ of polysilicon and the saturation region current Ids are approximately linear.
Fig. 6 is a schematic diagram for explaining the relationship between the mobility μ of polysilicon and the stress σ in the stress testing device 110. In some embodiments, the graph can be developed in advance through experimentation. It can be seen that the stress σ and the mobility μ exhibit a substantially linear relationship when the thin film transistor 200 for testing is subjected to compressive stress. Therefore, the relationship between the stress σ and the mobility μ is the following equation 2:
μ -K1 σ (formula 2),
where K1 is a scaling factor.
Combining equation 1 and equation 2, the relationship between stress σ and current Ids can be obtained:
σ＝μ/K1＝2Ids/K1*cox(W/L)(Vgs-Vth)2(formula 3) of the reaction mixture,
wherein the voltage Vgs remains constant at each test, and the threshold voltage Vth, the width-to-length ratio W/L, and the unit gate oxide capacitance Cox are fixed. Similarly, the tensile stress applied to the thin film transistor 200 for testing can also be calculated by the above method.
Therefore, the stress σ applied to the display panel 100 can be calculated by using the stress testing apparatus 110 under different stresses and detecting the magnitude of the output current Ids in the bending region from the current collecting terminal 213.
In summary, the present invention provides a stress testing apparatus and a stress testing method for a display panel, where the stress testing apparatus is configured to test a stress applied to the display panel in a bent state, the display panel includes a bending region, the stress testing apparatus includes a data processing unit and at least one testing thin film transistor electrically connected to the data processing unit, the testing thin film transistor is disposed in the bending region, and the data processing unit is configured to receive an output current of the testing thin film transistor located in the bending region, and calculate the stress applied to the display panel in the bending region according to the output current.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
Claims (10)
1. The stress testing device for the display panel is used for testing the stress of the display panel in a bending state, the display panel comprises a bending area, the stress testing device comprises a data processing unit and at least one testing thin film transistor electrically connected with the data processing unit, the testing thin film transistor is arranged in the bending area, and the data processing unit is used for receiving the output current of the testing thin film transistor located in the bending area and calculating the stress of the display panel in the bending area according to the output current.
2. The stress testing device of the display panel according to claim 1, wherein the display panel comprises a display area and a non-display area adjacent to the display area, the display panel comprises a substrate layer, and the thin film transistor for testing is arranged on the substrate layer and located in the non-display area;
the thin film transistor for testing includes:
the grid metal layer is arranged on the substrate layer and comprises a grid and a grid signal input end connected with the grid;
an active layer disposed on the substrate layer;
the grid electrode insulating layer is arranged on the substrate layer and is arranged between the grid electrode metal layer and the active layer;
the interlayer dielectric layer is arranged on the substrate layer, the active layer and the grid metal layer; and
and the source and drain electrode layer is arranged on the interlayer dielectric layer and comprises a source electrode, a drain electrode, a signal input end connected with the source electrode and a current collecting end connected with the drain electrode, two ends of the active layer are respectively connected with the source electrode and the drain electrode, and the current collecting end is connected with the data processing unit.
3. The device for testing the stress of the display panel according to claim 2, wherein the display panel comprises at least one bending axis located in the bending region, and at least one thin film transistor for testing is correspondingly arranged at any one bending axis.
4. The stress testing device of claim 3, wherein one of the testing thin film transistors is disposed at one of the bending axes, and the active layer of the testing thin film transistor is disposed on the substrate layer with the bending axis as a symmetry axis.
5. The stress testing apparatus of claim 3, wherein a plurality of testing thin film transistors are correspondingly disposed at one bending axis, and the active layer of the testing thin film transistors is disposed on the substrate layer with the bending axis as a symmetry axis.
6. The device for testing the stress of the display panel according to claim 2, wherein the gate metal layer further comprises a bridging trace disposed on the substrate layer, and the current collecting terminal is connected to the data processing unit through the bridging trace.
7. The stress testing device of the display panel according to claim 6, wherein a via hole is formed in the interlayer dielectric layer, one end of the bridging wire penetrates through the via hole to be connected with the current collecting end, and the other end of the bridging wire is connected with the data processing unit.
8. A stress test method of a display panel, wherein a stress test device of the display panel according to any one of claims 1 to 7 is used to test the stress applied to the display panel, and the method comprises the following steps:
enabling the display panel to be in a bent state, driving the thin film transistor for testing, and detecting the output current of the thin film transistor for testing in the bent area;
and calculating the stress of the display panel in the bending area according to the output current.
9. The stress test method of the display panel according to claim 8, wherein the step of driving the test thin film transistor comprises: and inputting a data signal at the signal input end of the source drain layer, and inputting a driving signal at the gate signal input end of the gate metal layer.
10. The stress testing method of claim 8, wherein the calculating the stress on the display panel in the bending region according to the output current comprises calculating a stress σ on the display panel in the bending region:
σ＝2Ids/K1*cox(W/L)(Vgs-Vth)2
and Ids is the output current, K1 is a proportionality coefficient, cox is a unit gate oxide capacitance, W/L is the width-to-length ratio of the channel of the thin film transistor for testing, Vgs is the voltage between the gate and the source, and Vth is the threshold voltage of the thin film transistor for testing.
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| CN109585513A (en) * | 2018-12-06 | 2019-04-05 | 京东方科技集团股份有限公司 | A kind of flexible display substrates, display device and its control method |
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