CN112019187B - Automatic frequency calibration circuit - Google Patents
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Abstract
The invention discloses an automatic frequency calibration circuit, which comprises an AFC module, a counting module, an adder, a frequency divider, a phase discriminator and a numerical control oscillator, wherein the AFC module is respectively connected with the numerical control oscillator, the counting module and the adder, the phase discriminator is connected to the numerical control oscillator through the adder, the numerical control oscillator is connected with the counting module through the frequency divider, and the counting module is respectively connected with the AFC module and the phase discriminator; the AFC module is used for carrying out high-order or medium-order calibration on an input target frequency control word FCW according to the count value obtained by the counting module, calibrating one bit in each period, finally realizing coarse adjustment and medium adjustment, the control oscillator generates a frequency signal according to the calibrated frequency control word, the frequency divider divides the frequency signal, the counting module counts the rising edge and the falling edge of the frequency signal after the frequency divider divides the frequency signal, the count value is sent to the AFC module during coarse adjustment and medium adjustment, the count value is sent to the phase discriminator during fine adjustment, and the phase discriminator realizes fine adjustment according to the count value. The invention has the advantages of high calibration speed and high calibration precision.
Description
Technical Field
The present invention relates to digital circuit technology, and more particularly, to an automatic frequency calibration circuit.
Background
An automatic frequency calibration circuit is a module that allows a phase locked loop to lock quickly and can be used to determine the coarse (or medium) control word of the phase locked loop. Under the deep submicron process, compared with the traditional process curve, the capacitance-voltage curve of the MOS tube is narrower in the linear region, the gradient delta C/delta V is larger, and the high-capacitance region and the low-capacitance region are flatter. According to the principle, the capacitance value of the MOS transistor can be controlled by discrete voltage signals. The Digital Controlled Oscillator (DCO) is a varactor array formed by a series of independent MOS capacitors, and the capacitance values of the MOS capacitors can be controlled according to respective digital control words. The equal-weight capacitor array has only a single frequency resolution, so that a large number of capacitor arrays are needed to realize a large output frequency range, and a large chip area is occupied, so that a design method of a plurality of capacitor sub-arrays is generally adopted by DCO nowadays.
The concept of automatic frequency calibration is introduced from an analog phase-locked loop, in which a dichotomy method is adopted to realize the quick locking of the phase-locked loop, the middle sub-band of the tuning sub-band is selected each time, the output frequency of the VCO is compared with the reference frequency, and if the frequency is higher, the middle sub-band is selected downwards by the dichotomy method, otherwise, the middle sub-band is selected upwards. Unlike analog phase-locked loops, digital phase-locked loops may have multiple frequency resolutions due to the different capacitive subarrays, and conventional automatic frequency calibration methods are not suitable for achieving fast locking of the digital phase-locked loop. The method is generally adopted at present, and specifically operates to adjust the output frequency control word by comparing the DCO gain (the ratio of the output frequency variation to the frequency control word) of the ideal case and the actual case, and the method has the defects that a multi-bit divider is required, and the calibration accuracy is limited by the TDC accuracy.
Disclosure of Invention
The invention aims to: aiming at the problems existing in the prior art, the invention provides the automatic frequency calibration circuit which has high calibration speed and high calibration precision.
The technical scheme is as follows: the automatic frequency calibration circuit comprises an AFC module, a counting module, an adder, a frequency divider and a phase discriminator, wherein the AFC module is respectively connected with a numerical control oscillator, the counting module and the adder, the phase discriminator is connected to the numerical control oscillator through the adder, the numerical control oscillator is connected with the counting module through the frequency divider, and the counting module is respectively connected with the AFC module and the phase discriminator; the AFC module is used for carrying out high-order calibration or middle-order calibration on an input target frequency control word FCW according to the count value acquired by the counting module, calibrating one bit in each period to finally realize coarse adjustment and middle adjustment, the controlled oscillator is used for generating a frequency signal according to the calibrated frequency control word, the frequency divider is used for dividing the frequency signal, the counting module is used for counting the rising edge and the falling edge of the frequency signal after the frequency divider divides the frequency signal, the count value is sent to the AFC module when the coarse adjustment and the middle adjustment are carried out, the count value is sent to the phase discriminator when the coarse adjustment and the middle adjustment are carried out, and the phase discriminator is used for realizing fine adjustment according to the count value.
Further, the AFC module comprises a down counter, an AFC logic controller, a DMUX unit, a first stage AFC unit, a second stage AFC unit, a RAM, an adder and a 2-selected 1MUX unit, wherein the AFC logic controller is respectively connected with the counting module, the down counter, the DMUX unit and the 2-selected 1MUX unit, the first stage AFC unit and the second stage AFC unit are respectively connected with the DMUX unit, the RAM is connected with the first stage AFC unit, the adder is connected with the second stage AFC unit and the RAM, and the 2-selected 1MUX unit is respectively connected with the first stage AFC unit, the adder and the numerically controlled oscillator; the working phase of the AFC module comprises an initialization phase, a stabilization phase, a quantization phase, an AFC phase and a reset phase, wherein the countdown counter enters the initialization phase after receiving an externally transmitted starting signal, the count value is set to be an initialization time S1, and the AFC logic controller controls initialization and directly transmits an externally transmitted target frequency control word FCW to the numerical control oscillator; after the count value of the down counter is reduced to 0, entering a stable stage, resetting the count value to enable the numerical control oscillator to start oscillation for the time S2, and waiting for the numerical control oscillator to start oscillation; after the count value is reduced to 0 again, entering a quantization stage, resetting the count value to be the count time S3 of the counting module, sending a count start signal to the counting module by the AFC logic controller, and sending a count end signal to the counting module when the count value is reduced to 0, wherein a DMUX unit waits for receiving an AFC trigger signal, a rising edge count value and a falling edge count value sent by the counting module; when the AFC logic controller receives an AFC trigger signal and enters an AFC stage, a counter reset count value is an AFC time S4, the AFC logic controller controls high-order calibration of the FCW and then middle-order calibration, if the high-order calibration of the FCW is performed at this time, the AFC logic controller controls a DMUX unit to output an input FCW, a rising edge count value and a falling edge count value to a first-stage AFC unit, the first-stage AFC unit calibrates the FCW according to the rising edge count value and the falling edge count value, stores a calibrated calibration frequency control word in a RAM and outputs the calibrated calibration frequency control word to a numerical control oscillator through a 2-selected 1MUX unit, if the middle-order calibration of the FCW is performed at this time, the AFC logic controller controls a DMUX unit to output the input FCW, the rising edge count value and the falling edge count value to a second-stage AFC unit, the second-stage AFC unit calibrates a target frequency control word FCW according to the rising edge count value and the falling edge count value, and the middle-order calibration frequency control word is added to the high-order of the calibrated calibration frequency control word stored in the RAM through an adder, and then the numerical control oscillator is output to the numerical control oscillator through the 1-selected 1-MUX unit; and then entering a reset stage, resetting the count value to be the reset time S5, controlling the AFC module to reset by the AFC logic controller, and sending a reset signal to the counting module.
Further, the first stage AFC unit specifically includes a first target frequency calculation subunit, a first actual frequency calculation subunit, a first comparator, and a first frequency control word output subunit, where:
the first target frequency calculating subunit is configured to calculate a target frequency according to the FCW by using the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the first actual frequency calculating subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Is the frequency dividing ratio of the frequency divider, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the first comparator is used for comparing the magnitude of the target frequency and the actual frequency;
the first frequency control word output subunit is configured to obtain a bit to be calibrated of a frequency control word, update the bit to be calibrated of the local calibration frequency control word to be 1 when the target frequency is greater than the actual frequency, and update the bit to be calibrated of the local calibration frequency control word to be 0 when the target frequency is less than the actual frequency, where an initial value of the calibration frequency control word is FCW, and the bit to be calibrated is updated one bit at a time from a highest bit until an intermediate bit is updated.
Further, the second stage AFC unit specifically includes a second target frequency calculation subunit, a second actual frequency calculation subunit, a second comparator, and a second frequency control word output subunit, where:
the second target frequency calculating subunit is configured to calculate a target frequency according to the FCW by using the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the second actual frequency calculation subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Is the frequency dividing ratio of the frequency divider, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the second comparator is used for comparing the magnitude of the target frequency and the magnitude of the actual frequency;
and when the target frequency is smaller than the actual frequency, updating the bit to be calibrated of the local calibration frequency control word to 0, wherein the initial value of the calibration frequency control word is FCW, and the bit to be calibrated is updated one bit at a time from the middle until the last bit.
Further, the counting module specifically comprises a logic controller, an AND gate, a rising edge counting unit, a falling edge counting unit and a DMUX unit, wherein the logic controller is connected with the AFC module, one input end of the AND gate is connected with the logic controller, the other input end of the AND gate is connected with a frequency divider, the output end of the AND gate is respectively connected with the rising edge counting unit and the falling edge counting unit, the input end of the DMUX unit is respectively connected with the logic controller, the rising edge counting unit and the falling edge counting unit, and the output end of the DMUX unit is respectively connected with the phase discriminator and the AFC module; after the AFC module completes coarse adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count the rising edge and the falling edge of the input frequency signals after frequency division, and after the counting is completed, the DMUX unit is controlled to send the rising edge counting value, the falling edge counting value and an AFC trigger signal to the AFC module, and after the AFC module completes coarse adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count the rising edge and the falling edge of the input frequency signals after frequency division, and after the counting is completed, the DMUX unit is controlled to send the rising edge counting value, the falling edge counting value and a feedback loop second trigger signal to the phase discriminator to trigger the phase discriminator to realize fine adjustment.
Further, the rising edge counting unit specifically includes a plurality of D flip-flops connected in series, wherein, the clock input end of each D flip-flop is connected with the Q non-end of the last D flip-flop, if the D flip-flop is first, the clock input end is connected with the output end of the and gate, the Q non-end is also connected with the D end of the D flip-flop in a feedback manner, the reset end is connected with the AFC module, and the Q end forms a rising edge count value according to the serial sequence.
Further, the falling edge counting unit specifically includes an inverter and a plurality of D flip-flops connected in series, wherein, the clock input end of each D flip-flop is connected with the Q non-end of the last D flip-flop, if the D flip-flop is first, the clock input end is connected with the output end of the and gate through the inverter, the Q non-end is also connected with the D end of the D flip-flop in a feedback manner, the reset end is connected with the AFC module, and the Q end forms the falling edge count value according to the serial sequence.
Further, only the first start of the AFC module will enter the initialization phase, and each subsequent cycle of the working phase will enter the stabilization phase of the next cycle after the completion of the reset phase.
Further, in calibrating the last bit of the high order, the first comparator needs to compare the difference between the last calculated actual frequency and the target frequency with the frequency difference between the last actual frequency and the target frequency, if the last frequency difference is small, the first frequency control word output subunit updates the bit of the local calibration frequency control word to 1 and outputs the bit, and if the last frequency difference is small, the first frequency control word output subunit outputs the local calibration frequency control word.
The beneficial effects are that: compared with the prior art, the invention has the remarkable advantages that: 1. compared with the existing automatic frequency calibration circuit, the automatic frequency calibration circuit has the performance advantages of high speed, high calibration precision, high portability, smaller area, lower design difficulty, less time and the like. 2. Compared with the traditional counter circuit, the improved ripple digital counter has smaller area, can stably work at a higher frequency, is designed by a semi-custom method, and has the characteristics of an all-digital circuit.
Drawings
FIG. 1 is a circuit block diagram of one embodiment of the present invention;
FIG. 2 is a block diagram of the AFC module of FIG. 1;
FIG. 3 is a block schematic diagram of the first stage AFC unit of FIG. 2;
FIG. 4 is a block schematic diagram of the second stage AFC unit of FIG. 2;
fig. 5 is a circuit diagram of the counting module of fig. 1.
Detailed Description
The embodiment provides an automatic frequency calibration circuit, as shown in fig. 1, comprising an AFC module, a counting module, an adder, a frequency divider and a phase discriminator, wherein the AFC module is respectively connected with a numerical control oscillator, the counting module and the adder, the phase discriminator is connected with the numerical control oscillator through the adder, the numerical control oscillator is connected with the counting module through the frequency divider, and the counting module is respectively connected with the AFC module and the phase discriminator; the frequency divider is used for counting the rising edge and the falling edge of the frequency signal after the frequency division of the frequency divider, and sending the count value to the phase discriminator when the coarse adjustment and the middle adjustment are completed, and the phase discriminator is used for realizing the fine adjustment according to the count value.
As shown in fig. 2, the AFC module includes a down counter, an AFC logic controller, DMUX units, a first stage AFC unit, a second stage AFC unit, a RAM, an adder, and a 2-to-1 MUX unit, the AFC logic controller is connected to the count module, the down counter, the DMUX units, and the 2-to-1 MUX unit, respectively, the first stage AFC unit and the second stage AFC unit are connected to the DMUX units, the RAM is connected to the first stage AFC unit, the adder is connected to the second stage AFC unit and the RAM, and the 2-to-1 MUX unit is connected to the first stage AFC unit, the adder, and the numerically controlled oscillator, respectively. The working phase of the AFC module comprises an initialization phase, a stabilization phase, a quantization phase, an AFC phase and a reset phase, wherein a down counter enters the initialization phase after receiving an externally transmitted starting signal, a count value is set to be an initialization time S1, an AFC logic controller controls initialization and directly transmits an externally transmitted target frequency control word FCW to a numerical control oscillator, the initialization is specifically a 9-bit buffer deburring, the FCW is specifically 100001000 (which represents that a DCO rough adjustment capacitor array and a medium adjustment capacitor array are provided with half access circuits, and the output frequency of DCO is the middle value of the output range); after the count value of the down counter is reduced to 0, entering a stable stage, resetting the count value to enable the numerical control oscillator to start oscillation, wherein the time S2 of the reset count value is specifically 3, namely three reference frequency periods, and waiting for the numerical control oscillator to start oscillation; after the count value is reduced to 0 again, entering a quantization stage, resetting the count value to be the count time S3 of the counting module, sending a count start signal to the counting module by the AFC logic controller, and sending a count end signal to the counting module when the count value is reduced to 0, wherein a DMUX unit waits for receiving an AFC trigger signal, a rising edge count value and a falling edge count value sent by the counting module; when the AFC logic controller receives an AFC trigger signal and enters an AFC stage, a counter reset count value is an AFC time S4, the AFC trigger signal is specifically three reference frequency periods and is used for triggering the execution of the AFC, the AFC logic controller controls the high-order calibration of the FCW and then the middle-order calibration, if the high-order calibration of the FCW is performed at this time, the AFC logic controller controls the DMUX unit to output the input FCW, the rising edge count value and the falling edge count value to the first-stage AFC unit, the first-stage AFC unit calibrates the FCW according to the rising edge count value and the falling edge count value, the calibrated calibration frequency control word is stored in the RAM and is output to the numerical control oscillator through the 2-choice 1MUX unit, if the middle-order calibration of the FCW is performed at this time, the AFC logic controller controls the DMUX unit to output the input FCW, the rising edge count value and the falling edge count value to the second-order AFC unit, the second-stage AFC unit calibrates the target frequency control word W according to the rising edge count value and the falling edge count value, and the calibrated middle-order frequency control word is added to the high-order oscillator through the 1-choice-of the AFC unit, and the numerical control oscillator is output to the 1-choice-of the high-order oscillator after the calibration word is added to the AFC unit; and then entering a reset stage, resetting the count value to be the reset time S5, controlling the AFC module to reset by the AFC logic controller, and sending a reset signal to the counting module. After one cycle period is completed, the steps are repeated, and the cycle is performed, wherein one bit is calibrated every time, however, the AFC module only starts for the first time and enters an initialization stage, and then enters a stabilization stage of the next cycle after the completion of a reset stage, the first stage AFC unit can complete the calibration of all high bits and stores the calibration in a RAM, and the second stage AFC unit can complete the calibration of all medium bits and form a calibration frequency control word after being combined with the high bits in the RAM and outputting the calibration frequency control word to the DCO.
As shown in fig. 3, the first stage AFC unit specifically includes a first target frequency calculation subunit, a first actual frequency calculation subunit, a first comparator, and a first frequency control word output subunit, where:
the first target frequency calculating subunit is configured to calculate a target frequency according to the FCW by adopting the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the first actual frequency calculating subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Is the frequency dividing ratio of the frequency divider, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the first comparator is used for comparing the magnitude of the target frequency and the actual frequency;
the first frequency control word output subunit is used for acquiring a to-be-calibrated bit of the frequency control word, updating the to-be-calibrated bit of the locally-stored calibration frequency control word to be 1 when the target frequency is greater than the actual frequency, and updating the to-be-calibrated bit of the locally-stored calibration frequency control word to be 0 when the target frequency is less than the actual frequency, wherein the initial value of the calibration frequency control word is FCW, and the to-be-calibrated bit is updated one bit at a time from the highest bit until the to-be-calibrated bit is updated to the middle bit. In the first calibration of the upper bits, the highest bit and the next highest bit are calibrated at a time, and one bit is calibrated at a time, that is, if the target frequency is greater than the actual frequency, the highest position 1 and the next highest position 1 are output calibration frequency control words 110001000, and if the target frequency is less than the actual frequency, the highest position 0 and the next highest position 1 are output calibration frequency control words 010001000. In addition, in the calibration of the last bit of the upper bits, the first comparator needs to compare the difference between the actual frequency and the target frequency calculated last time with the frequency difference between the actual frequency and the target frequency last time, if the last frequency difference is small, the first frequency control word output subunit updates the bit of the local calibration frequency control word to 1 and outputs the bit, and if the last frequency difference is small, the first frequency control word output subunit outputs the local calibration frequency control word. The final first stage AFC unit will complete the calibration of the first five bits of the frequency control word.
As shown in fig. 4, the second stage AFC unit specifically includes a second target frequency calculation subunit, a second actual frequency calculation subunit, a second comparator, and a second frequency control word output subunit, where:
the second target frequency calculating subunit is configured to calculate a target frequency according to the FCW by using the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the second actual frequency calculating subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Frequency dividing ratio of digital control oscillator output, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the second comparator is used for comparing the magnitude of the target frequency and the actual frequency;
and updating the bit to be calibrated of the local calibration frequency control word to 1 when the target frequency is greater than the actual frequency, and updating the bit to be calibrated of the local calibration frequency control word to 0 when the target frequency is less than the actual frequency, wherein the initial value of the calibration frequency control word is FCW, and the bit to be calibrated is updated one bit at a time from the middle until the last bit. The final second stage AFC unit will complete the calibration of the last 4 bits of the frequency control word.
The process of fine tuning the phase detector is the same as in the prior art, and will not be described in detail here.
As shown in fig. 5, the counting module specifically includes a logic controller, an and gate, a rising edge counting unit, a falling edge counting unit and a DMUX unit, where the logic controller is connected with the AFC module, one input end of the and gate is connected with the logic controller, the other input end is connected with the frequency divider, the output end is connected with the rising edge counting unit and the falling edge counting unit respectively, the input end of the DMUX unit is connected with the logic controller, the rising edge counting unit and the falling edge counting unit respectively, and the output end is connected with the phase discriminator and the AFC module respectively; after the AFC module completes coarse adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count rising edges and falling edges of the input frequency signals after frequency division, after the counting end signal of the AFC module is received, the logic controller ends counting, and controls the DMUX unit to send the rising edge count value Pos_cnt, the falling edge count value neg_cnt and an AFC trigger signal to the AFC module, and after the AFC module completes coarse adjustment and medium adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count rising edges and falling edges of the input frequency signals after frequency division, and after the counting is finished, the DMUX unit is controlled to send the rising edge count value Pos_cnt, the falling edge count value neg_cnt and a feedback loop second trigger signal to the phase detector to trigger the phase detector to realize fine adjustment. The rising edge counting unit specifically comprises a plurality of D triggers which are connected in series, wherein the clock input end of each D trigger is connected with the Q non-end of the last D trigger, if the D trigger is the first one, the clock input end is connected with the output end of the AND gate, the Q non-end is also connected with the D end of the D trigger in a feedback manner, the reset end is connected with the AFC module, and the Q end forms a rising edge count value Pos_cnt according to the serial sequence. The falling edge counting unit specifically comprises an inverter and a plurality of D triggers connected in series, wherein the clock input end of each D trigger is connected with the Q non-end of the last D trigger, if the D trigger is the first one, the clock input end is connected with the output end of an AND gate through the inverter, the Q non-end is also connected with the D end of the D trigger in a feedback manner, the reset end is connected with an AFC module, and the Q end forms a falling edge count value neg_cnt according to the serial sequence.
The above disclosure is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention, which is defined by the appended claims.
Claims (8)
1. An automatic frequency calibration circuit, characterized by: the phase detector is connected to the numerical control oscillator through the adder, the numerical control oscillator is connected with the counting module through the frequency divider, and the counting module is respectively connected with the AFC module and the phase detector;
the AFC module is used for carrying out high-order calibration or middle-order calibration on an input target frequency control word FCW according to the count value acquired by the counting module, calibrating one bit in each period to finally realize coarse adjustment and middle adjustment, the numerical control oscillator is used for generating a frequency signal according to the calibrated frequency control word, the frequency divider is used for dividing the frequency signal, the counting module is used for counting the rising edge and the falling edge of the frequency signal after the frequency division of the frequency divider, the count value is sent to the AFC module during coarse adjustment and middle adjustment, the count value is sent to the phase discriminator after the coarse adjustment and the middle adjustment are finished, and the phase discriminator is used for realizing fine adjustment according to the count value;
the AFC module comprises a down counter, an AFC logic controller, a DMUX unit, a first-stage AFC unit, a second-stage AFC unit, a RAM, an adder and a 2-selected 1MUX unit, wherein the AFC logic controller is respectively connected with the counting module, the down counter, the DMUX unit and the 2-selected 1MUX unit, the first-stage AFC unit and the second-stage AFC unit are respectively connected with the DMUX unit, the RAM is connected with the first-stage AFC unit, the adder is connected with the second-stage AFC unit and the RAM, and the 2-selected 1MUX unit is respectively connected with the first-stage AFC unit, the adder and the numerically controlled oscillator;
the working phase of the AFC module comprises an initialization phase, a stabilization phase, a quantization phase, an AFC phase and a reset phase, wherein the countdown counter enters the initialization phase after receiving an externally transmitted starting signal, the count value is set to be an initialization time S1, and the AFC logic controller controls initialization and directly transmits an externally transmitted target frequency control word FCW to the numerical control oscillator; after the count value of the down counter is reduced to 0, entering a stable stage, resetting the count value to enable the numerical control oscillator to start oscillation for the time S2, and waiting for the numerical control oscillator to start oscillation; after the count value is reduced to 0 again, entering a quantization stage, resetting the count value to be the count time S3 of the counting module, sending a count start signal to the counting module by the AFC logic controller, and sending a count end signal to the counting module when the count value is reduced to 0, wherein a DMUX unit waits for receiving an AFC trigger signal, a rising edge count value and a falling edge count value sent by the counting module; when the AFC logic controller receives an AFC trigger signal and enters an AFC stage, a counter reset count value is an AFC time S4, the AFC logic controller controls high-order calibration of the FCW and then middle-order calibration, if the high-order calibration of the FCW is performed at this time, the AFC logic controller controls a DMUX unit to output an input FCW, a rising edge count value and a falling edge count value to a first-stage AFC unit, the first-stage AFC unit calibrates the FCW according to the rising edge count value and the falling edge count value, stores a calibrated calibration frequency control word in a RAM and outputs the calibrated calibration frequency control word to a numerical control oscillator through a 2-selected 1MUX unit, if the middle-order calibration of the FCW is performed at this time, the AFC logic controller controls a DMUX unit to output the input FCW, the rising edge count value and the falling edge count value to a second-stage AFC unit, the second-stage AFC unit calibrates a target frequency control word FCW according to the rising edge count value and the falling edge count value, and the middle-order calibration frequency control word is added to the high-order of the calibrated calibration frequency control word stored in the RAM through an adder, and then the numerical control oscillator is output to the numerical control oscillator through the 1-selected 1-MUX unit; and then entering a reset stage, resetting the count value to be the reset time S5, controlling the AFC module to reset by the AFC logic controller, and sending a reset signal to the counting module.
2. The automatic frequency calibration circuit of claim 1, wherein: the first-stage AFC unit specifically comprises a first target frequency calculation subunit, a first actual frequency calculation subunit, a first comparator and a first frequency control word output subunit, wherein:
the first target frequency calculating subunit is configured to calculate a target frequency according to the FCW by using the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the first actual frequency calculating subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Is the frequency dividing ratio of the frequency divider, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the first comparator is used for comparing the magnitude of the target frequency and the actual frequency;
the first frequency control word output subunit is configured to obtain a bit to be calibrated of a frequency control word, update the bit to be calibrated of the local calibration frequency control word to be 1 when the target frequency is greater than the actual frequency, and update the bit to be calibrated of the local calibration frequency control word to be 0 when the target frequency is less than the actual frequency, where an initial value of the calibration frequency control word is FCW, and the bit to be calibrated is updated one bit at a time from a highest bit until an intermediate bit is updated.
3. The automatic frequency calibration circuit of claim 1, wherein: the second-stage AFC unit specifically comprises a second target frequency computing subunit, a second actual frequency computing subunit, a second comparator and a second frequency control word output subunit, wherein:
the second target frequency calculating subunit is configured to calculate a target frequency according to the FCW by using the following formula:
f target ＝FCW·f ref
wherein f ref Representing a reference frequency;
the second actual frequency calculation subunit is configured to calculate an actual frequency according to the rising edge count value and the falling edge count value by adopting the following steps:
wherein N is div Is the frequency dividing ratio of the frequency divider, N c For the count value of the counting module, pos_cnt is the rising edge count value, neg_cnt is the falling edge count value, S4 is AFC time, i.e. the number of periods of the AFC phase,
the second comparator is used for comparing the magnitude of the target frequency and the magnitude of the actual frequency;
and when the target frequency is smaller than the actual frequency, updating the bit to be calibrated of the local calibration frequency control word to 0, wherein the initial value of the calibration frequency control word is FCW, and the bit to be calibrated is updated one bit at a time from the middle until the last bit.
4. The automatic frequency calibration circuit of claim 1, wherein: the counting module specifically comprises a logic controller, an AND gate, a rising edge counting unit, a falling edge counting unit and a DMUX unit, wherein the logic controller is connected with the AFC module, one input end of the AND gate is connected with the logic controller, the other input end of the AND gate is connected with a frequency divider, the output end of the AND gate is respectively connected with the rising edge counting unit and the falling edge counting unit, the input end of the DMUX unit is respectively connected with the logic controller, the rising edge counting unit and the falling edge counting unit, and the output end of the DMUX unit is respectively connected with the phase discriminator and the AFC module;
after the AFC module completes coarse adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count the rising edge and the falling edge of the input frequency signals after frequency division, and after the counting is completed, the DMUX unit is controlled to send the rising edge counting value, the falling edge counting value and an AFC trigger signal to the AFC module, and after the AFC module completes coarse adjustment, the rising edge counting unit and the falling edge counting unit are controlled to start to count the rising edge and the falling edge of the input frequency signals after frequency division, and after the counting is completed, the DMUX unit is controlled to send the rising edge counting value, the falling edge counting value and a feedback loop second trigger signal to the phase discriminator to trigger the phase discriminator to realize fine adjustment.
5. The automatic frequency calibration circuit of claim 4, wherein: the rising edge counting unit specifically comprises a plurality of D triggers which are connected in series, wherein the clock input end of each D trigger is connected with the Q non-end of the last D trigger, if the D trigger is the first one, the clock input end is connected with the output end of the AND gate, the Q non-end is also connected with the D end of the D trigger in a feedback manner, the reset end is connected with the AFC module, and the Q end forms a rising edge counting value according to the serial sequence.
6. The automatic frequency calibration circuit of claim 4, wherein: the falling edge counting unit specifically comprises an inverter and a plurality of D triggers which are connected in series, wherein the clock input end of each D trigger is connected with the Q non-end of the last D trigger, if the D trigger is the first one, the clock input end is connected with the output end of an AND gate through the inverter, the Q non-end is also connected with the D end of the D trigger in a feedback manner, the reset end is connected with an AFC module, and the Q end forms a falling edge count value according to the serial sequence.
7. The automatic frequency calibration circuit of claim 1, wherein: only the first start of the AFC module will enter the initialization phase, and each subsequent cycle of the working phase will enter the stabilization phase of the next cycle after the completion of the reset phase.
8. The automatic frequency calibration circuit of claim 2, wherein: in the calibration of the last bit of the high order, the first comparator needs to compare the difference between the actual frequency and the target frequency calculated last time with the frequency difference between the actual frequency and the target frequency last time, if the last frequency difference is small, the first frequency control word output subunit updates the bit of the local calibration frequency control word to 1 and outputs the bit, and if the last frequency difference is small, the first frequency control word output subunit outputs the local calibration frequency control word.
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