CN112018224B - Die bonding method and display panel - Google Patents

Die bonding method and display panel Download PDF

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CN112018224B
CN112018224B CN202010943381.2A CN202010943381A CN112018224B CN 112018224 B CN112018224 B CN 112018224B CN 202010943381 A CN202010943381 A CN 202010943381A CN 112018224 B CN112018224 B CN 112018224B
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chips
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CN112018224A (en
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杨山伟
马俊杰
陈振彰
卢元达
岂林霞
赵加伟
熊志军
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BOE Technology Group Co Ltd
BOE Jingxin Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages

Abstract

The invention discloses a die bonding method and a display panel, wherein the die bonding method comprises the following steps: acquiring spectrum information of a plurality of light-emitting chips, and calculating color coordinate ranges of the plurality of light-emitting chips; determining the step length of grading the light-emitting chips, and dividing the grades of the light-emitting chips; and selecting part of the grade light-emitting chips to be distributed on the substrate. The display panel adopts the die bonding method to fix at least three light-emitting chips with different light-emitting colors, the number of the light-emitting chips with each light-emitting color is multiple, and the light-emitting chips with each light-emitting color have multiple grades. The die bonding method provided by the invention grades a plurality of light-emitting chips according to XY color coordinates, can select continuous grade light-emitting chips for die bonding, has uniform chromaticity, can effectively avoid the problem of chromatic aberration caused by grading the light-emitting chips according to wavelength, and allows the use of multi-grade light-emitting chips on the premise of ensuring the picture quality, thereby providing a Mini/Micro LED Micro display technology with better display screen performance, higher yield and lower cost.

Description

Die bonding method and display panel
Technical Field
The invention relates to the technical field of display, in particular to a die bonding method and a display panel.
Background
In recent years, a COB (Chip On Board) display technology has gradually gained market acceptance, and a main application of the COB-based Mini/Micro LED Micro display technology developed by various enterprises at present is a PCB substrate. However, the conventional PCB substrate has problems of high power consumption, poor heat dissipation, limited substrate size due to poor flatness, high substrate price, and the like. In contrast, a display technology based On COG (Chip On Glass) is proposed, and compared with the existing PCB substrate, the Glass substrate has low power consumption, good heat dissipation and good flatness, so that the substrate area is larger, the substrate price is lower, and the influence of unevenness of the PCB substrate On the display effect can be overcome.
However, at present, the influence of the uniformity of the chip color on the display effect is more significant, the chips adopted in the prior art adopt wavelength Bin (level), the color points of the chips belonging to the same wavelength Bin level but coming from different wafers still have different degree of deviation, and the problem of color difference is generated when the chips are applied to a display panel. Even if a single Bin-level chip is used, the problem of chromatic aberration in the existing display screen cannot be completely solved. What is worse, the Bin level range of the available chips in the display screen is very small because the used chips are of single Bin level, so that the material cost of the chips is very high.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a die bonding method and a display panel.
In a first aspect, the present invention provides a die bonding method, including:
acquiring spectrum information of a plurality of light-emitting chips, and calculating color coordinate ranges of the plurality of light-emitting chips;
determining the step length of grading the light-emitting chips, and dividing the grades of the light-emitting chips;
and selecting part of the grade light-emitting chips to be distributed on the substrate.
Preferably, the acquiring the spectrum information of the light emitting chips and the calculating the color coordinate ranges of the plurality of light emitting chips includes:
constructing a spectrum composite Gaussian function, and calculating a tristimulus value of the light-emitting chip under a first CIE color coordinate system;
calculating a first color coordinate of the light-emitting chip based on a tristimulus value of the light-emitting chip under a first CIE color coordinate system;
and determining the color coordinate ranges of the plurality of light-emitting chips according to the first color coordinate of each light-emitting chip.
Preferably, the spectral complex gaussian function is represented by:
Figure BDA0002674421530000021
the formula for calculating the tristimulus values of the light-emitting chip is as follows:
Figure BDA0002674421530000022
Figure BDA0002674421530000023
Figure BDA0002674421530000024
a first color coordinate (CIE _ X) of the light emitting chip C ，CIE_Y C ) The calculation formula of (2) is as follows:
CIE_X C ＝X C /(X C +Y C +Z C )，
CIE_Y C ＝Y C /(X C +Y C +Z C )；
the color coordinate ranges of the plurality of light emitting chips are as follows:
X C ∈[CIE_X Cmin ～CIE_X Cmax ]，Y C ∈[CIE_Y Cmin ～CIE_Y Cmax ]；
wherein the spectral information comprises a dominant wavelength c λ and a peak wavelength λ C And half wave width HW C ；
Figure BDA0002674421530000025
And
Figure BDA0002674421530000026
respectively CIE color response functionAnd v is the maximum visual performance.
Preferably, the determining the step size of the light emitting chip in the grading, and the dividing the grade to which the light emitting chip belongs includes:
converting the first color coordinate of the light-emitting chip into a second color coordinate under a second CIE color coordinate system according to a color coordinate conversion formula;
calculating a color difference value under a second CIE color coordinate system and judging whether the color difference value is smaller than a preset allowable value or not;
if the color difference value is smaller than the preset allowable value, determining the step length of the grading of the light-emitting chip;
and dividing the grade of the light-emitting chip based on the color coordinate range and the step length.
Preferably, the color coordinate conversion formula is:
CIE_u＝4CIE_X C /(-2CIE_X C +12CIE_Y C +3)，
CIE_v＝4CIE_Y C /(-2CIE_X C +12CIE_Y C +3)；
the calculation formula of the color difference value is as follows:
Figure BDA0002674421530000031
the step length of the light-emitting chip grading comprises an abscissa step length delta X C And a step size Δ Y of ordinate C ，ΔX C ＝X C_k+1 -X C_k ，ΔY C ＝Y C_p+1 -Y C_p ；
X C_k And X C_k+1 ∈[CIE_X Cmin ～CIE_X Cmax ]，X C_k <X C_k+1 ；
Y C_p And Y C_p+1 ∈[CIE_Y Cmin ～CIE_Y Cmax ]，Y C_p <Y C_p+1 ；
Wherein (CIE _ X) C ，CIE_Y C ) Is a first color coordinate of the light emitting chip, (CIE _ u, CIE _ v) is a second color coordinate of the light emitting chip; (X) C_k ，Y C_p ) Is converted into (CIE _ u) by the color coordinate conversion formula k ，CIE_u p )，(X C_k+1 ，Y C_p+1 ) Is converted into (CIE _ u) by the color coordinate conversion formula k+1 ，CIE_u p+1 )。
Preferably, the arrangement of the light emitting chips of the selected partial grades on the substrate includes:
selecting light-emitting chips of partial grades as chips to be die-bonded according to a preset die-bonding scheme;
and bonding the chip to be die bonded at the corresponding level at the corresponding position of the substrate through die bonding glue.
Preferably, the selecting of the light emitting chips of partial grades as the chips to be die bonded includes: and selecting a plurality of light-emitting chips with continuous grades as chips to be die-bonded.
Preferably, the number of the chips to be die bonded in each stage of the substrate bonding is equal to the ratio.
In a second aspect, the present invention provides a display panel, wherein at least three light emitting chips with different light emitting colors are fixed by the above die bonding method, the number of the light emitting chips with each light emitting color is multiple, and the light emitting chips with each light emitting color have multiple levels.
Preferably, a plurality of light emitting units distributed in an array are arranged in a display area of the display panel, each light emitting unit includes the at least three light emitting chips with different colors, only one light emitting chip of each light emitting color is arranged in each light emitting unit, and the light emitting chips with the same color in adjacent light emitting units have different levels.
Compared with the prior art, the die bonding method provided by the invention has the advantages that the light-emitting chips on the whole wafer are graded according to XY color coordinates, the light-emitting chips with continuous grades can be selected for die bonding, the chromaticity is uniform, the problem of chromatic aberration caused by grading the light-emitting chips according to the wavelength can be effectively avoided, the light-emitting chips with multiple grades are allowed to be used on the premise of ensuring the picture quality, and thus the Mini/Micro LED Micro display technology with better display screen performance, higher yield and lower cost is provided.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a flow chart of a die bonding method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a predetermined die bonding scheme according to an embodiment of the present invention;
fig. 3 to fig. 5 are schematic process diagrams of the die bonding method according to the embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The embodiment of the invention provides a die bonding method, as shown in fig. 1, comprising the following steps:
s10: acquiring spectrum information of a plurality of light-emitting chips, and calculating color coordinate ranges of the plurality of light-emitting chips;
s20: determining the step length of grading the light-emitting chips, and dividing the grades of the light-emitting chips;
s30: and selecting part of the grade light-emitting chips to be distributed on the substrate.
The substrate in the die bonding method of the embodiment is preferably a glass substrate, and the flatness is good; the plurality of light emitting chips are light emitting chips with the same light emitting color, such as red light chips, and the red light chips with a plurality of grades can be arranged on the substrate by the die bonding method. If the plurality of light-emitting chips are green chips, the green chips of a plurality of grades can be arranged on the substrate by the die bonding method; if the plurality of light-emitting chips are blue light chips, the blue light chips of a plurality of grades can be arranged on the substrate by the die bonding method.
In the die bonding method provided in this embodiment, the light emitting chip is first turned on, for example, in a photoluminescence or electroluminescence manner, and at present, the light emitting chip is mainly caused to emit light in a photoluminescence manner, and then the optical analog processing system obtains the spectrum information of the light emitting chip.
The die bonding method provided by the embodiment divides the light emitting chips into Bin based on XY color coordinates, the step S20 can divide the light emitting chips into P levels, the light emitting chips of the P levels are selected and arranged on the substrate in the step S30, and P is less than or equal to P, so that the problem of chromatic aberration can be effectively solved, the method is not limited to a single Bin level chip, the Bin level range of the used chips can be expanded, and the cost is reduced.
Further, step S10: acquiring spectral information of the light emitting chips, and calculating color coordinate ranges of the plurality of light emitting chips includes:
constructing a spectrum composite Gaussian function, and calculating a tristimulus value of the light-emitting chip under a first CIE color coordinate system;
calculating a first color coordinate of the light-emitting chip based on a tristimulus value of the light-emitting chip under a first CIE color coordinate system;
and determining the color coordinate ranges of the plurality of light-emitting chips according to the first color coordinate of each light-emitting chip.
In this example, the spectral complex gaussian function is represented as:
Figure BDA0002674421530000051
the formula for calculating the tristimulus values of the light-emitting chip is as follows:
Figure BDA0002674421530000052
Figure BDA0002674421530000053
Figure BDA0002674421530000054
first color coordinate (CIE _ X) of light emitting chip C ，CIE_Y C ) The calculation formula of (c) is:
CIE_X C ＝X C /(X C +Y C +Z C )，
CIE_Y C ＝Y C /(X C +Y C +Z C )；
the color coordinate ranges of the plurality of light emitting chips are:
X C ∈[CIE_X Cmin ～CIE_X Cmax ]，Y C ∈[CIE_Y Cmin ～CIE_Y Cmax ]；
wherein the spectral information comprises a dominant wavelength c lambda and a peak wavelength lambda C And half wave width HW C ；
Figure BDA0002674421530000061
And
Figure BDA0002674421530000062
respectively CIE color response functions, and v is the maximum visual performance. The maximum visual efficacy v is at present preferably 683, in lm/w units.
For example, if the plurality of light emitting chips are a plurality of red light emitting chips on a whole Wafer, the complex gaussian function of the spectrum is expressed as:
Figure BDA0002674421530000063
obtaining the tristimulus value X of the red light chip under the first color coordinate system R 、Y R And Z R ，
Figure BDA0002674421530000064
The first color coordinate of each red light chip can be obtained by using a calculation formula of the first color coordinate, and the corresponding first color coordinate is as follows:
CIE_X R ＝X R /(X R +Y R +Z R )，
CIE_Y R ＝Y R /(X R +Y R +Z R )。
taking an example that 500 red light chips can be obtained by processing a whole Wafer, 500 WLDs (R) can be obtained by using a spectral complex gaussian function, 500 groups of tristimulus values are correspondingly obtained, and then 500 first color coordinates are obtained, so that color coordinate ranges (X) of a plurality of red light chips can be determined R ，Y R ) Expressed as:
Figure BDA0002674421530000065
Y R ∈[CIE_Y Rmin ～CIE_Y Rmax ]。
if the light emitting chips are green chips, the same method can be used to obtain the color coordinate ranges of a plurality of green chips as follows:
Figure BDA0002674421530000066
Y G ∈[CIE_Y Gmin ～CIE_Y Gmax ]。
if the light emitting chip is a blue light chip, the same method can be used to obtain the color coordinate ranges of a plurality of blue light chips as follows:
Figure BDA0002674421530000071
Y B ∈[CIE_Y Bmin ～CIE_Y Bmax ]。
further, step S20: determining the step length of grading the light-emitting chips, and dividing the grades of the light-emitting chips comprises the following steps:
converting the first color coordinate of the light-emitting chip into a second color coordinate under a second CIE color coordinate system according to a color coordinate conversion formula;
calculating a color difference value under a second CIE color coordinate system and judging whether the color difference value is smaller than a preset allowable value or not;
if the color difference value is smaller than a preset allowable value, determining the step length of grading the light-emitting chip;
and dividing the grade to which the light-emitting chip belongs based on the color coordinate range and the step length.
In this embodiment, the color coordinate conversion formula is:
CIE_u＝4CIE_X C /(-2CIE_X C +12CIE_Y C +3)，
CIE_v＝4CIE_Y C /(-2CIE_X C +12CIE_Y C +3)；
the formula for calculating the color difference value is as follows:
Figure BDA0002674421530000072
the step size of the grading of the light-emitting chip comprises an abscissa step size delta X C And a step size Δ Y of ordinate C ，ΔX C ＝X C_k+1 -X C_k ，ΔY C ＝Y C_p+1 -Y C_p ；
X C_k And X C_k+1 ∈[CIE_X Cmin ～CIE_X Cmax ]，X C_k <X C_k+1 ；
Y C_p And Y C_p+1 ∈[CIE_Y Cmin ～CIE_Y Cmax ]，Y C_p <Y C_P+1 ；
Wherein (CIE _ X) C ，CIE_Y C ) Is a first color coordinate of the light emitting chip, (CIE _ u, CIE _ v) is a second color coordinate of the light emitting chip; (X) C_k ，Y C_p ) Converted into (CIE _ u) by a color coordinate conversion formula k ，CIE_u p )，(X C_k+1 ，Y C_p+1 ) Converted into (CIE _ u) by a color coordinate conversion formula k+1 ，CIE_u p+1 )。
The preset allowable value in this embodiment is preferably 0.005 to determine an appropriate step size, so that the light emitting chips of an appropriate Bin level are selected to ensure uniformity of display.
In the application, the first color coordinate system is preferably CIE1931 chromaticity coordinate, the second color coordinate system is preferably CIE1976 chromaticity coordinate, wherein the CIE1931 chromaticity diagram is uneven and inconsistent with human vision, and the CIE1976 color space uniformity is improved and is more consistent with human vision results, so that the step size for calculating the grading of the light emitting chips under the CIE1976 chromaticity coordinate is selected.
For example, the light emitting chip is a red chip, and after determining the excellent coordinate range, step S20 is performed to determine the step size. Suppose step size Δ X R′ And Δ Y R， Selecting the color coordinates (X) of two Bin levels before and after C_k ，Y C_p ) And (X) C_k+1 ，Y C_p+1 ) Obtaining corresponding color coordinates (CIE _ u) through a color coordinate conversion formula k ，CIE_u p ) And (CIE _ u) k+1 ，CIE_u p+1 ) Calculating the color difference value through a color difference value calculation formula, and if the color difference value is smaller than a preset allowable value, calculating the delta X R′ And Δ Y R′ Is determined as a step size Δ X R And Δ Y R (ii) a If the color difference value is not less than the preset allowable value, the step length delta X is determined again R′ And Δ Y R′ Repeating the above process to calculate the color difference value until the color difference value is smaller than a preset allowable value, and determining the step length delta X R And Δ Y R 。
Or, calculating that the color difference value is smaller than a preset allowable value by using a color difference value calculation formula, and performing color coordinate conversion on the color difference value by using a color coordinate conversion formula pair (CIE _ u) k ，CIE_u p ) And (CIE _ u) k+1 ，CIE_u p+1 ) Proceed backward to obtain (X) C_k ，Y C_p ) And (X) C_k+1 ，Y C_p+1 ) Then, the step size DeltaX is obtained R And Δ Y R 。
Based on step size Δ X R And Δ Y R And color coordinate range (X) R ，Y R ) And determining the Bin level of each red light chip on one Wafer so as to obtain the number of the level levels of a plurality of red light chips.
If the light emitting chip is a green light chip, the step length Δ X can be obtained by the same method G And Δ Y G Determining the Bin level of each green chip on the Wafer to obtain the Bin level number of the green chips;
if the light emitting chip is a blue light chip, the step length Δ X can be obtained by the same method B And Δ Y B And determining the Bin level of each blue light chip on one Wafer to obtain the Bin level number of the blue light chips.
Further, selecting some of the light emitting chips of the grade to arrange on the substrate includes:
selecting light-emitting chips of partial grades as chips to be die-bonded according to a preset die-bonding scheme;
and bonding the chip to be die bonded at the corresponding level at the corresponding position of the substrate through die bonding glue.
For example, it is determined through steps S10 and S20 that the red chip has M levels;
step S30 is implemented, according to a preset die bonding scheme, M levels of red light chips are selected as chips to be die bonded, and M is less than or equal to M;
and bonding the red light chips to be die-bonded of corresponding grades at corresponding positions of the substrate through die bonding glue.
In addition, the green chips can be determined to have N levels through the steps S10 and S20, the green chips with the N levels are selected as the chips to be die-bonded in the step S30, and N is less than or equal to N; the blue chips can be determined to have K grades through the steps S10 and S20, the green chips with the K grades are selected as the chips to be die bonded in the step S30, and K is less than or equal to K. And selecting red light chips, green light chips and blue light chips of partial grades to form a solid crystal scheme according to requirements so as to achieve a better Bin mixing effect.
Compared with the existing mode of dividing the chips into bins according to the wavelength, the method can effectively solve the problem that the color points of the chips from different wafers have different deviation degrees.
Further, selecting the light emitting chips of partial grades as the chips to be die bonded includes: and selecting a plurality of light-emitting chips with continuous grades as chips to be die-bonded. For example, m levels of red chips are selected as the chips to be bonded, the levels of the m levels of red chips are continuous, and the uniformity of color development is ensured while using a plurality of levels of red chips. Similar schemes are adopted for the selection of the green chip and the blue chip.
Furthermore, the quantity of the chips to be die bonded in each grade of substrate bonding is in equal proportion. For example, the red light chips to be die-bonded have m levels, the number of the red light chips to be die-bonded of the m levels is in equal proportion, and the green light chips and the blue light chips are designed similarly, so that the uniformity of the display color gamut and the brightness can be further improved.
Based on the die bonding method provided by the above embodiment, an embodiment of the present invention further provides a display panel, where at least three light emitting chips with different light emitting colors are fixed by using the die bonding method, the number of the light emitting chips with each light emitting color is multiple, and the light emitting chip with each light emitting color has multiple levels.
Furthermore, a plurality of light emitting units distributed in an array are arranged in a display area of the display panel, each light emitting unit comprises at least three light emitting chips with different colors, only one light emitting chip with each light emitting color is arranged in each light emitting unit, and the light emitting chips with the same color in the adjacent light emitting units have different grades.
For example, a red light chip, a green light chip and a blue light chip are arranged on the display panel, and a red light chip, a green light chip and a blue light chip are arranged in each light-emitting unit;
in a plurality of light emitting units distributed in an array manner in a display area, red light chips of m grades are arranged in a crossed manner, green light chips of n grades are arranged in a crossed manner, blue light chips of k grades are arranged in a crossed manner, the grades of the red light chips in adjacent light emitting units are different, the grades of the green light chips in adjacent light emitting units are different, and the grades of the blue light chips in adjacent light emitting units are different. The design ensures the uniformity of display color gamut and brightness.
Further, based on that the human eye has a much higher visual sensitivity to green light than red light and blue light, and has a much lower visual sensitivity to blue light than red light and green light, m =1,n =2,k =2 can be designed to improve the visual effect of the human eye.
Of course, m = n = k, the number of the light emitting chips of each color is consistent, the design of the die bonding scheme is facilitated, and the convenience of the die bonding process is improved.
In the invention, after the red light chip is divided into Bin, the green light chip is divided into Bin and the blue light chip is divided into Bin through the steps S10 and S20, a high color gamut display is used for simulating a spliced screen (such as 27 inch) with a specific size to respectively observe the mixed Bin effect of R, G, B three colors, so as to obtain a preset die bonding scheme. The display used here has a pixel size of 155.4 μm, and about 6*6 display pixels ≈ 1 tiled screen pixel. The red light chips of m grades, the green light chips of n grades and the blue light chips of k grades are selected to be respectively filled in each position of the display according to a certain rule, and the arrangement rule can be carried out in various modes such as cross arrangement, complete randomness, random optimization and the like.
For example, during die bonding, the number of Bin levels of a red chip, a green chip and a blue chip is 3. Taking red chips as an example, 3 Bin levels are represented as Bin1 R 、Bin2 R And Bin3 R Then, they are arranged crosswise as Bin1 R 、Bin2 R And Bin3 R The Bin is arranged in a crossed manner, and the situation that the same Bin is adjacent is avoided; completely random is to place Bin1 in a random manner R 、Bin2 R And Bin3 R (ii) a Random optimization is also to place Bin1 in a random manner R 、Bin2 R And Bin3 R However, more than three adjacent bins need to be avoided. In each arrangement, the total amount of Bin1 R 、Bin2 R And Bin3 R The ratio of (1).
The simulation effect takes the high color gamut display viewing effect as an evaluation criterion, and observes the display effect within a specified distance (such as 0.5m or 1m, which is determined according to the manufactured end product). Here, the viewing effect of a single Bin filled high color gamut display is used as a reference for judging the color coordinate solidification scheme, namely, the color gamut NTFC is more than or equal to 110%, and the brightness uniformity is more than 90%. The simulated 27inch spliced screen has excellent uniformity effect when being arranged in a cross way; when the cotton fibers are arranged in a completely random mode, the uniformity is poor, and the cotton-shaped color difference is obvious; when random optimization arrangement is adopted, the uniformity effect is slightly improved compared with that of complete random arrangement, but still obvious chromatic aberration exists. And comparing the three schemes, and selecting the optimal cross arrangement mode for the display effect.
As shown in FIG. 2, the pre-set die bonding scheme has 3 levels for the red, green and blue chips，Bin1 R 、Bin2 R And Bin3 R Denotes a red chip, bin1 G 、Bin2 G And Bin3 G Denotes a green chip, bin1 B 、Bin2 B And Bin3 B Representing a blue chip.
In the die bonding method provided in this embodiment, the processing on the light emitting chip includes a front-stage process and a back-stage process for die bonding on the light emitting chip. In the front-stage process, after growing each layer of the whole Wafer by MOCVD (metal organic chemical vapor deposition) technology, plating a metal electrode on the Wafer, and then grinding the whole Wafer so as to thin the sapphire substrate to the required thickness; splitting the thinned Wafer into single chip individuals by using laser equipment; and finally, transferring all chips after the splitting is finished to the UV film to be delivered completely. Compared with the existing traditional chip manufacturing process, three processes of point measurement, sorting and AOI (automatic optical inspection) are not needed, the three reduced processes can save 20-30% of labor cost, and the full Bin delivery mode can reduce the material cost of the chip by 40-50% in total.
The entire red Wafer red chip was transferred to a UV film by the front end of line process. As shown in fig. 3, a laser with a wavelength of 525nm is used to perform Photoluminescence (PL) on red chips, the color coordinates of each red chip to be used can be obtained in step S10, and the obtained color coordinates are compared with M levels of the red chips, so as to determine the level to which each red chip belongs, and NG products are directly classified as defective products. After the PL test on the whole UV film is completed to confirm the Bin level of each red light chip, according to a preset die bonding scheme, the ejector pins on the die bonding machine are used for sequentially placing red light chips which accord with the Bin level on the red light bonding pads of the glass substrate in a zigzag mode.
The entire green Wafer green chip was transferred to a UV film by the front end process. As shown in FIG. 4, the green chip is Photoluminescence (PL) by using laser with a wavelength of 525nm, the color coordinates of each green chip to be used are obtained by step S10, and the obtained color coordinates are compared with M grades of the green chip, so that the grade of each green chip is determined, and the NG products are directly classified into defective products. After the PL test on the whole UV film is completed to confirm the Bin level of each green chip, according to a preset die bonding scheme, the ejector pins on the die bonding machine are used for sequentially placing the green chips which accord with the Bin level on the green bonding pads of the glass substrate in a zigzag mode.
The entire blue Wafer blue chip was transferred to a UV film by the front end process. As shown in fig. 5, photoluminescence (PL) is performed on the blue chips by using laser with a wavelength of 525nm, the color coordinates of each blue chip to be used are obtained in step S10, and the obtained color coordinates are compared with M grades of the blue chips, so that the grade to which each blue chip belongs is determined, and NG products are directly classified into defective products. After the PL test on the whole UV film is completed to confirm the Bin level of each blue light chip, according to a preset die bonding scheme, the thimble on the die bonding machine is used for sequentially placing the blue light chips which accord with the Bin level on the blue light bonding pad of the glass substrate in a zigzag mode.
According to the preset die bonding scheme, the Mini/Micro LED Micro display technology with better display screen performance, higher yield and lower cost is provided through die bonding of the red light chip, die bonding of the green light chip and die bonding of the blue light chip.
The foregoing description is only exemplary of the preferred embodiments of the invention and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the spirit of the invention. For example, the above features and (but not limited to) features having similar functions disclosed in the present invention are mutually replaced to form the technical solution.

Claims (7)

1. A die bonding method is characterized by comprising the following steps:
constructing a spectrum composite Gaussian function, and calculating tristimulus values of the plurality of light-emitting chips under a first CIE color coordinate system;
calculating a first color coordinate of the light-emitting chip based on a tristimulus value of the light-emitting chip under a first CIE color coordinate system;
determining the color coordinate ranges of the plurality of light-emitting chips according to the first color coordinate of each light-emitting chip;
converting the first color coordinate of the light-emitting chip into a second color coordinate under a second CIE color coordinate system according to a color coordinate conversion formula;
calculating a color difference value under a second CIE color coordinate system and judging whether the color difference value is smaller than a preset allowable value or not;
if the color difference value is smaller than the preset allowable value, determining the step length of the grading of the light-emitting chip;
dividing the grade of the light-emitting chip based on the color coordinate range and the step length;
selecting part of grade light-emitting chips to be distributed on the substrate;
the first CIE color coordinate system is CIE1931 color coordinate, and the second CIE color coordinate system is CIE1976 color coordinate.
2. The die bonding method according to claim 1, wherein the spectral complex gaussian function is represented as:
Figure FDA0003711978330000011
the formula for calculating the tristimulus values of the light-emitting chip is as follows:
Figure FDA0003711978330000012
Figure FDA0003711978330000013
Figure FDA0003711978330000014
the first color of the light emitting chipCoordinates (CIE _ X) C ，CIE_Y C ) The calculation formula of (2) is as follows:
CIE_X C ＝X C /(X C +Y C +Z C )，
CIE_Y C ＝Y C /(X C +Y C +Z C )；
the color coordinate ranges of the plurality of light emitting chips are as follows:
X C ∈[CIE_X Cmin ～CIE_X Cmax ]，Y C ∈[CIE_Y Cmin ～CIE_Y Cmax ]；
wherein the spectral information comprises a dominant wavelength c lambda and a peak wavelength lambda C And half wave width HW C ；
Figure FDA0003711978330000021
And
Figure FDA0003711978330000022
respectively CIE color response functions, and v is the maximum visual performance.
3. The die bonding method according to claim 1,
the color coordinate conversion formula is as follows:
CIE_u＝4CIE_X C /(-2CIE_X C +12CIE_Y C +3)，
CIE_v＝4CIE_Y C /(-2CIE_X C +12CIE_Y C +3)；
the calculation formula of the color difference value is as follows:
Figure FDA0003711978330000023
the step length of the grading of the light-emitting chip comprises an abscissa step length delta X C And a step size Δ Y of ordinate C ，ΔX C ＝X C_k+1 -X C_k ，ΔY C ＝Y C_p+1 -Y C_p ；
X C_k And X C_k+1 ∈[CIE_X Cmin ～CIE_X Cmax ]，X C_k ＜X C_k+1 ；
Y C_p And Y C_p +1∈[CIE_Y Cmin ～CIE_Y Cmax ]，Y C_p ＜Y C_p +1；
Wherein (CIE _ X) C ，CIE_Y C ) Is a first color coordinate of the light emitting chip, (CIE _ u, CIE _ v) is a second color coordinate of the light emitting chip; (X) C_k ，Y C_p ) Is converted into (CIE _ u) by the color coordinate conversion formula k ，CIE_u p )，(X C_k+1 ，Y C_p+1 ) Is converted into (CIE _ u) by the color coordinate conversion formula k+1 ，CIE_u p+1 )。
4. The die bonding method according to claim 1, wherein the arranging the light emitting chips of the selected partial levels on the substrate comprises:
selecting light-emitting chips of partial grades as chips to be die-bonded according to a preset die-bonding scheme;
and bonding the chip to be die bonded at the corresponding level at the corresponding position of the substrate through die bonding glue.
5. The die bonding method according to claim 4, wherein the selecting of the light emitting chips of partial grades as the chips to be die bonded comprises: and selecting a plurality of light-emitting chips with continuous grades as chips to be die-bonded.
6. The die bonding method according to claim 5, wherein the number of the die to be bonded in each stage of the substrate bonding is in equal proportion.
7. A display panel, characterized in that at least three light emitting chips with different light emitting colors are fixed by the die bonding method according to any one of claims 1 to 6, the number of the light emitting chips with each light emitting color is multiple, and the light emitting chips with each light emitting color have multiple levels;
the display panel is characterized in that a plurality of light emitting units distributed in an array mode are arranged in a display area of the display panel, each light emitting unit comprises at least three light emitting chips with different colors, only one light emitting chip with each light emitting color is arranged in each light emitting unit, and the light emitting chips with the same color in the adjacent light emitting units are different in grade.
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