CN112017987B - Semiconductor test structure - Google Patents

Abstract

The invention provides a semiconductor test structure, which comprises a plurality of local areas arranged on a semiconductor substrate, wherein each local area defines an effective area and a plurality of redundant areas arranged around the effective area through a groove isolation structure formed in the semiconductor substrate, the effective area is provided with a test element, the test element is connected with an electrode in a mode of measuring electrical characteristics, and the redundant areas are distributed in a mode that the pattern density of the local areas is different from each other. By using the semiconductor test structure, the lower limit value of the pattern density of the local area when the chemical mechanical polishing process is carried out can be obtained by measuring the electrical characteristics of the test element of each local area and comparing the electrical characteristic results corresponding to different local areas, thereby being beneficial to selecting proper pattern density and optimizing the effect of the chemical mechanical polishing process.

Description

Semiconductor test structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor test structure.

Background

Chemical Mechanical Polishing (CMP) process is applied as a semiconductor silicon wafer surface planarization technology. The polishing rate of a CMP process is known to be related to the pattern density of the planarized surface design to be formed on the surface of a semiconductor silicon wafer. For example, in order to prevent current leakage between adjacent regions and to ensure the voltage resistance of the regions, when a Shallow Trench Isolation (STI) structure is fabricated in a semiconductor silicon wafer, a CMP process is used to make the upper surface of the STI structure flush with the upper surface of an adjacent active region. Specifically, the polishing rate is low in a region where the active area density is high and the groove area is relatively small (referred to as a high density pattern region), and the polishing rate is high in a region where the active area density is low and the groove area is relatively large (referred to as a low density pattern region), which easily causes over-polishing (polishing) or under-polishing during the polishing process, and further easily affects the characteristics of the fabricated region.

US patent (US 6,737,721) discloses that dishing will occur when over-polishing occurs in low density pattern areas where large area isolation trenches are present during the formation of the upper surface of STI structures using a CMP process. Such recessing can result in parasitic transistors being formed at the ends of the transistor region. The parasitic transistor, especially for the micro transistor, may cause the threshold voltage Vth of the micro transistor to decrease.

In order to solve the problem of non-uniform polishing speed, as disclosed in U.S. patent No. 2012/0256273, one solution is to increase the active area density by forming a dummy pattern (dummy patterns) of the same material as the actual active area in the groove region of the low-density pattern region, and then performing a CMP process to prevent the occurrence of over-polishing. The pattern density of a local region of a semiconductor silicon wafer formed with a redundant pattern can be represented by the ratio of the sum of the area of the redundant pattern in the local region and the area of an active region for manufacturing a functional element in the local region divided by the total area of the local region.

It is important how to arrange the redundant pattern to obtain a suitable pattern density in the local area, if the pattern density is too high, the polishing speed is reduced to cause insufficient polishing, and if the pattern density is too low, the problem of parasitic transistor cannot be solved. US patent (US 7,250,644) discloses a method of determining an upper limit value of pattern density in a local area, in which a silicon nitride layer is formed on a silicon substrate, trenches in the silicon substrate and the silicon nitride layer are covered with a silicon oxide layer, the design of a redundant pattern is adjusted to obtain local areas of different pattern densities, and chemical mechanical polishing is performed, and the upper limit value of pattern density can be determined by measuring the thickness of the silicon oxide layer remaining in an evaluation area.

However, it may be desirable in semiconductor device design to provide active regions on a substrate with a lower pattern density. For example, it is sometimes necessary to provide resistance elements formed of a large area well region such as a polysilicon resistance element (polysilicon) around the transistor, and the density of the active region around these resistance elements should be set low. Therefore, it is still an important task to determine the lower limit of the pattern density (in the active area) suitable for the chemical mechanical polishing process.

Disclosure of Invention

The invention provides a semiconductor test structure which can be used for obtaining a lower limit value of local area pattern density corresponding to a CMP (chemical mechanical polishing) process, and further contributes to optimizing the effect of the CMP process.

The semiconductor test structure provided by the invention comprises a plurality of local areas arranged on a semiconductor substrate, wherein each local area defines an effective area and a plurality of redundant areas arranged around the effective area through a groove isolation structure formed in the semiconductor substrate, the effective area is provided with a test element, the test element is connected with an electrode in a mode of being capable of measuring electrical characteristics, and the redundant areas are distributed in a mode of enabling the pattern density of the local areas to be different from each other.

Optionally, the pattern density of the plurality of local regions is distributed in a range of 5% to 80%.

In addition, the arrangement distance between two adjacent redundant regions is in the range of 1/100-1/5 of the side length of the local region.

Optionally, the size of each of the redundant regions is in a range from above 1/10 to below 9/10 of the set pitch.

Optionally, in the same local region, the redundant regions are arranged at intervals of a fixed arrangement pitch.

Optionally, the upper surface of the trench isolation structure is obtained in each local region through the same chemical mechanical polishing process, and the heights of the upper surfaces of the trench isolation structures are not completely the same among the multiple local regions.

Optionally, in a plurality of the local regions, the sizes of the active regions are the same, and the positions where the test elements are arranged in the corresponding active regions are the same and the sizes are the same.

Optionally, the test element is a MOSFET, and the semiconductor test structure is used to determine a threshold voltage and/or a saturation drain current of the MOSFET.

Optionally, the gate electrode of the MOSFET is arranged to extend to the surface of the trench isolation structure outside the corresponding active area.

Optionally, the area of the local region is set to be 100 μm × 100 μm to 500 μm × 500 μm.

By using the semiconductor test structure, the lower limit value of the pattern density of the local area when the chemical mechanical polishing process is carried out can be obtained by measuring the electrical characteristics of the test element of each local area and comparing the electrical characteristic results corresponding to different local areas, thereby being beneficial to selecting proper pattern density and optimizing the effect of the chemical mechanical polishing process.

Drawings

Fig. 1 is a schematic view of a semiconductor substrate in an embodiment of the invention.

FIG. 2 is a schematic plan view of a local region of a semiconductor test structure in accordance with an embodiment of the present invention.

Fig. 3 is a schematic sectional view taken along a-a direction in fig. 2.

FIG. 4 is a schematic plan view of a local region of a semiconductor test structure in accordance with an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view taken along the direction B-B in fig. 4.

FIGS. 6-15 are cross-sectional views illustrating the fabrication of a semiconductor test structure according to an embodiment of the present invention.

FIGS. 16 and 17 are enlarged cross-sectional views of semiconductor test structures according to embodiments of the present invention.

Fig. 18 shows an exemplary measurement result of a relationship between a threshold voltage and a pattern density of a MOSFET provided in an active region according to an embodiment of the present invention.

Fig. 19 is a graph illustrating an exemplary measurement of a relationship between a saturation drain current and a pattern density of a MOSFET disposed in an active area according to an embodiment of the present invention.

Description of reference numerals:

100-a semiconductor substrate; 102-a semiconductor test structure; 104-a local area; 20-an active area; 22-redundant area; 30-an oxide layer; a 32-nitride layer; 34-a filling layer; 36-a gate insulating layer; 38-a gate electrode; 40-a diffusion layer; 42-a side wall; 44-source regions; 46-the drain region.

Detailed Description

The semiconductor test structure of the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, but merely as a convenient and clear aid in describing embodiments of the invention, which should not be construed as limited to the specific shapes of regions illustrated in the drawings. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted.

As shown in fig. 1, a semiconductor substrate 100 of an embodiment of the present invention has a semiconductor test structure 102. A semiconductor test structure 102 is formed on a surface of a semiconductor substrate 100. The semiconductor test structure 102 is used to ascertain the effect of the CMP process performed on the surface of the semiconductor substrate 100 on the surface of the semiconductor substrate, and in particular, the semiconductor test structure 102 may be used to obtain a lower limit value of the local area pattern density corresponding to the CMP process for forming the upper surface of the trench isolation structure (i.e., obtaining the active area range) as described in the background art, thereby optimizing the effect of the CMP process.

The semiconductor test structure 102 includes a plurality of local regions 104. As shown in fig. 2 to 4, each of the partial regions 104 is formed with an effective region 20 and a redundant region 22, the effective region 20 is provided with a test element connected to an electrode so as to be able to measure an electrical characteristic, and the redundant region 22 is arranged so that the pattern density of the plurality of partial regions 104 is different from each other. Here, the ranges of the active region 20 and the redundant region 22 are defined by a Trench Isolation structure, such as Shallow Trench Isolation (STI) or Deep Trench Isolation (DTI).

In the embodiment of the present invention, the distribution of the redundant area 22 in the plurality of local areas 104 has a difference, so that the local areas 104 have different pattern densities, respectively. That is, among the plurality of partial regions 104, the redundant region 22 is set in structure, size, interval, and distance from the active region 20 such that each partial region 104 has a different pattern density.

The term "local region" in this embodiment refers to a region in which the active region 20 and the redundant region 22 are formed on the surface of the semiconductor substrate 100 in order to understand the influence of the CMP process. The area of each local region 104 is set to 100 μm × 100 μm to 500 μm × 500 μm, for example, in which the polishing effect can be easily studied.

In addition, the "pattern density" in the present embodiment refers to a ratio of the sum of the area of the region in each local region 104 where the effective region 20 is formed and the area of the region in which the redundant region 22 is formed divided by the total area of the local regions. The region for forming the active region 20 and the region for forming the redundant region 22 refer to an upper surface region of the semiconductor substrate 100, which is defined after a planarization process, such as a CMP process, is performed on the surface of the semiconductor substrate 100 to obtain an upper surface of the trench isolation structure during the manufacturing process of the trench isolation structure. Optionally, the upper surface of the trench isolation structure in each local region 104 is preferably obtained by the same chemical mechanical polishing process, and the heights of the upper surfaces of the trench isolation structures between a plurality of local regions 104 are not completely the same so as to compare polishing effects. In addition, the plurality of local regions 104 may be arranged, in each local region 104, the size of the active region 20 is the same, and the position and size of the test element arranged in the active region 20 are substantially the same, so as to compare the influence of the CMP process on the upper surface region (as an active region for manufacturing the test element) of the semiconductor substrate 100 by measuring the electrical characteristics of the test element, and further obtain a lower limit value of the local region pattern density (when the lower limit value is lower than the lower limit value, after the CMP process, a parasitic transistor is formed on the test element due to a high polishing speed, and the electrical performance of the test element is significantly changed by the parasitic transistor).

The test elements disposed in the active area 20 may be various devices that facilitate testing of electrical performance, such as transistors, triodes, and the like, for example, MOSFETs are used as the test elements in the present embodiment, and specifically, the semiconductor test structure 102 may be used to measure electrical characteristics of the MOSFETs in each local area 104, such as threshold voltage Vth, saturated drain current Idsat, and the like, and compare the electrical characteristic results obtained from different local areas 104 to obtain a lower limit value of the local area pattern density when the CMP process is performed. Furthermore, as shown in fig. 3 to 5, one or both ends of the gate electrode 38 of the MOSFET may be arranged to extend outside the corresponding active area 20, i.e., the width in at least one direction is larger than the width of the active area 20 in that direction, so that a portion of the gate electrode 28 is arranged to cover the surface of the trench isolation structure. Thus, when the trench isolation structure has a lower upper surface due to a high polishing rate, the gate electrode 38 also serves as a gate electrode of a parasitic transistor formed, which has a significant influence on the electrical characteristics of the test element. In the embodiment shown in fig. 2 to 5, the source and drain regions of the MOSFET may be arranged in the Y direction in the active area 20 on both sides of the gate electrode 38.

In the semiconductor test structure 102 according to the embodiment of the present invention, the pattern density of the plurality of local regions 104 may vary in the entire range of 5% or less to 80% or more. For example, eight local regions 104 may be provided, and the pattern densities thereof may be set to less than 5%, 10%, 25%, 35%, 45%, 60%, 80%, respectively. In an embodiment, the pattern density of the local regions 104 is in a range from 0.1% to 80%, and further, the distribution range of the pattern density may be appropriately narrowed based on the actual polishing effect of the CMP process, for example, in an embodiment, the pattern density of the local regions is in a range from 5% to 80%. The distribution range and specific arrangement of the pattern density are not critical, as long as the influence of the polishing speed on the electrical characteristics of the test element in each local region 104 with different pattern densities when the CMP process is performed can be reflected.

The redundant regions 22 may be arranged at a fixed arrangement pitch within the same local region 104. The specific redundant area 22 may be provided in the shape of a square or a rectangle or the like provided at equal intervals in the lateral direction (X direction) and the longitudinal direction (Y direction) of the partial area 104. However, the shape of the redundant area 22 is not limited thereto, and may be provided in other shapes such as a circle, an ellipse, and the like.

The arrangement pitch (for example, Px or Py in fig. 2 and 4) of the redundant area 22 may be set in a range from 1/100 or more to 1/5 or less of the side length (for example, Wx or Wy in fig. 2 and 4) of the partial area 104. The set pitch here refers to the center-to-center distance between two adjacent redundant areas 22. In the example of fig. 2 to 5, the local region 104 is square, the X-direction side length Wx of the local region 104 is equal to the Y-direction side length Wy of the local region 104, and the X-direction setting pitch Px of the redundant region 22 is equal to the Y-direction setting pitch Py of the redundant region 22. However, the present invention is not limited thereto, and the X-direction side length Wx of the local region 104 may be different from the Y-direction side length Wy of the local region 104. The X-direction arrangement pitch Px of the redundant area 22 may be different from the Y-direction arrangement pitch Py of the redundant area 22.

Further, the effective area 20 may be set to have the same set pitch (Px, Py) as the redundant area 22. That is, one of the positions in the array of the redundant area 22 may be set as the active area 20. In the local area 104, a plurality of redundant areas 22 are preferably provided so as to be disposed around the active area 20, in order to adjust the pattern density.

The size of the redundant area 22 (e.g., Sx, Sy in fig. 2 and 4) may be set to be in a range of 1/10 or more and 9/10 or less at the set pitch (e.g., Px, Py in fig. 2 and 4). In the example of fig. 2 to 5, the redundant area 22 is square, and the X-direction dimension Sx and the Y-direction dimension Sy of the redundant area 22 are equal. However, the present invention is not limited thereto, and the X-direction dimension Sx of the redundant area 22 may be different from the Y-direction dimension Sy. The X-direction side Wx of the local region 104 may be different from the Y-direction side Wy of the local region 104. Further, when the redundant area 22 is circular or elliptical, the diameter (major axis or minor axis direction) of the redundant area 22 is preferably set to be in the range of 1/10 or more and 9/10 or less of the respective arrangement pitches. In the case where the redundant area 22 takes other shapes, it is also preferable to set the size of the redundant area 22 in the range of 1/10 or more and 9/10 or less of the set pitch.

FIGS. 6-15 are cross-sectional views illustrating the fabrication of a semiconductor test structure according to an embodiment of the present invention. Wherein the direction of the cross-section may be the X-direction or the Y-direction in fig. 2 to 5. In the interest of clarity, the dimensions of the structures in fig. 6-15 may differ from the actual dimensions. The following fabrication process is merely exemplary, and the semiconductor test structure 102 of the present invention may be fabricated by other methods. The following describes a process for fabricating the semiconductor test structure 102 described above with reference to fig. 6 to 15.

Referring to fig. 6, an oxide layer 30 and a nitride layer 32 are first formed on the surface of a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon (Si) substrate. When the semiconductor substrate 100 is a silicon substrate, the oxide layer 30 is preferably a silicon oxide layer (SiO layer)₂). The thickness of the oxide layer 30 may be set to 5nm or more and 20nm or less. The method of forming the oxide layer 30 is not particularly limited, and oxygen (O) gas may be introduced while heating the semiconductor substrate 100₂) Thermal oxidation method (2). When the semiconductor substrate 100 is a silicon substrate, the nitride layer 32 is a silicon nitride film (Si)₃N₄). A nitride layer 32 is formed on the surface of the oxide layer 30. The nitride layer 32 may be set to a thickness of 60nm or more and 200nm or less. The method of forming the nitride layer 32 is not particularly limited, and Silane (SiH) may be introduced while heating the semiconductor substrate 100₄) Silicon-containing gas and ammonia (NH)₃) And the like, mixed gas containing nitrogen gas. The thicknesses of the oxide layer 30 and the nitride layer 32 are not limited to the above ranges as long as they are set within a range suitable for the semiconductor test structure 102 described below to perform a test function.

Referring to fig. 7, the oxide layer 30 and the nitride layer 32 are then etched. The etching processing method of the oxide layer 30 and the nitride layer 32 is not particularly limited, and a photolithography method using a reticle may be employed, specifically, a photoresist layer having an opening is formed on the surface of the nitride layer 32 and the oxide layer 30 and the nitride layer 32 are etched in the opening area of the photoresist layer. The photoresist layer is formed to cover the extent of the active area 20 and the redundant area 22. For example, in a range corresponding to the partial region 104, photoresist layer covering regions having sizes Sx and Sy in the X direction and the Y direction, respectively, are formed at set pitches Px and Py in the X direction and the Y direction, respectively, and the remaining regions are opening regions. The arrangement pitch and size of the plurality of local regions 104 are such that the pattern densities of the local regions 104 are different from each other in such a manner as to satisfy the above-described condition. The etching of the local region 104 may be performed by conventional wet chemical etching, reactive ion etching, plasma etching, and the like.

Referring to fig. 8, a trench T is then formed in the semiconductor substrate 100. The trench T is formed corresponding to a region of the surface of the semiconductor substrate 100 not covered with the oxide layer 30 and the nitride layer 32. The depth D of the trench T is, for example, 200nm to 500 nm. The trench T may be formed by dry etching such as Reactive Ion Etching (RIE) of the area of the semiconductor substrate 100 not covered with the oxide layer 30 and the nitride layer 32 using the oxide layer 30 and the nitride layer 32 as masks. For example, CF can be used₄、CHF₃、SF₆The trench T is formed by reactive ion etching with a fluorine-containing gas.

Referring to fig. 9, a filling layer 34 is then formed by filling the trench T with an insulating material. The filling layer 34 is formed to fill not only the trenches T provided in the semiconductor substrate 100 but also to cover the surfaces of the oxide layer 30 and the nitride layer 32. The filling layer 34 can be formed by using Silane (SiH), for example₄) Silicon-containing gas and oxygen (O)₂) Mixed gas of oxygen-containing gas or use of organic silane such as tetraethoxysilane (Si (OC)₂H₅)₄TEOS) is formed by performing a Chemical Vapor Deposition (CVD) process. In addition, it may also be formed using a High Density Plasma Chemical Vapor Deposition (HDPCVD) process. The thickness of the filling layer 34 is not limited as long as it is sufficient to fill the trench T. In addition, before the filling layer 34 is formed, the surface of the semiconductor substrate 100 (including the inner surface of the trench T) may be subjected to thermal oxidation treatment.

Referring to fig. 10, the excess portion of the fill layer 34 is then removed by a planarization process. This treatment is achieved by a Chemical Mechanical Polishing (CMP) process. For example, the SiO-containing material is continuously supplied to the surface of the semiconductor substrate 100₂、AL₂O₃、CeO₂、Mn₂O₃And particles (having a particle diameter of several tens to several hundreds nanometers) such as diamond, are brought into contact with the semiconductor substrate 100, and the polishing pad and the semiconductor substrate 100 are simultaneously rotated, thereby removing the excess filling layer 34. In actual practice, the fill layer 34 may have a lower surface than the nitride layer 32 due to the non-uniform polishing rate.

Referring to fig. 11, the oxide layer 30 and the nitride layer 32 are then removed. The method of removing the oxide layer 30 and the nitride layer 32 is not particularly limited, and wet etching or dry etching may be appropriately selected. In some embodiments, after the fifth step and the sixth step are performed on the partial local area 104, the resulting surface is as shown in fig. 11, and the height difference between the upper surface of the filling layer 34 and the upper surface of the semiconductor substrate 100 is small and substantially flush.

Through the above steps, a trench isolation structure is formed in the semiconductor substrate 100 corresponding to the region of the filling layer 34, with which an active region 20 and a plurality of redundant regions 22 (refer to fig. 2 to 5) disposed around the active region 20 are defined in a plurality of partial regions of the semiconductor substrate 100.

Referring to fig. 12, a gate insulating layer 36 is then formed on the surface of the semiconductor substrate 100. The gate insulating layer 36 may be a silicon oxide layer (SiO)₂) Silicon nitride layer (Si)₃N₄) Silicon oxynitride film (SiO)_xN_y). The gate insulating layer 36 is formed on the surface of the semiconductor substrate 100 filled with the filling layer 34 in the trench T. The thickness of the gate insulating layer 36 may be set to 1.5nm or more and 20nm or less. The formation method of the gate insulating layer 36 is not particularly limited, and the use of oxygen (O) may be employed₂) Equal oxygen-containing gas, nitrogen (N)₂) And thermal oxidation of nitrogen-containing gas.

Referring to fig. 13, a gate electrode 38 is then formed on the gate insulating layer 36. The gate electrode 38 may employ a polysilicon layer, a metal layer, a salicide, or a stacked structure including at least one of them. The gate electrode 38 may be laminated on the surface of the semiconductor substrate 100 on which the gate insulating layer 36 is formed by photolithography or the like. That is, the gate electrode 38 is formed in the active region 20Is formed on the gate electrode. The formation method of the gate electrode 38 is not particularly limited, and in the case of a polysilicon layer, use of Silane (SiH) may be employed₄) And Chemical Vapor Deposition (CVD) of a silicon-containing gas. When the gate electrode 38 uses a metal layer, a vapor deposition method, a sputtering method, a chemical vapor deposition method, or the like can be used. When salicide is used for the gate electrode 38, a method of depositing a refractory metal such as titanium (Ti) or tantalum (Ta) over polysilicon and then performing heat treatment, a method of depositing a refractory metal by sputtering silicon at the same time, or another method can be used. Further, the gate insulating layer 36 is removed as much as possible by the over-etching performed by the gate electrode etching process except for the region under the gate electrode 38, or remains as a residual film. Alternatively, as shown in fig. 2 to 5, the gate electrode 38 may be sized to extend beyond the active region 20 at one or both ends in a certain direction, that is, a part of the gate electrode 38 is located on the remaining filling layer 34 of the trench isolation structure, so that when the upper surface of the filling layer 34 is lower due to the fast polishing speed, the gate electrode 38 also serves as a gate electrode of the formed parasitic transistor, and the parasitic transistor has a significant influence on the electrical characteristics of the test element.

Referring to fig. 14, a diffusion layer 40 is then formed on the surface of the semiconductor substrate 100, and sidewalls 42 are formed on the sides of the gate electrode 38. The diffusion layer 40 functions as a so-called Lightly Doped Drain (LDD) region. The diffusion layer 40 may be formed by implanting dopant ions through a mask and then annealing for thermal diffusion. The ion implantation energy, dopant implantation density, and thermal diffusion conditions may be set according to the characteristics of the test elements to be formed in the active area 20. When the test element to be formed is an N-type MOSFET, ion implantation of an N-type dopant (such As phosphorus P or arsenic As) may be performed on the surface of the semiconductor substrate 100, and then the dopant is diffused by annealing, thereby forming the diffusion layer 40. For example, the implantation dose is first 1 × 10¹³/cm²~2×10¹⁵/cm²Ion implantation is performed, and then annealing is performed at a high temperature of about 1000 ℃, thereby forming the diffusion layer 40. When the test element to be formed is a P-type MOSFET, it can be formed on the surface of the semiconductor substrate 100P-type dopant (boron B or boron difluoride BF)₂) And then forming the diffusion layer 40 by annealing. For example, the implantation dose is first 1 × 10¹³/cm²~2×10¹⁵/cm²The boron B of (a) is ion-implanted, and then annealed at a high temperature of about 1000 ℃ to diffuse the dopant, thereby forming the diffusion layer 40.

After that, a sidewall 42 is formed at the side of the gate electrode 38. The sidewall 42 is formed of a silicon oxide layer (SiO)₂) And the like. Here, the sidewalls 42 may be formed by forming a silicon oxide layer on the entire surface of the semiconductor substrate 100 by a method such as chemical vapor deposition, and then by anisotropic etching so that the silicon oxide layer remains only on the side surfaces of the gate electrodes 38.

Referring to fig. 15, source regions 44 and drain regions 46 are then formed. The source region 44 and the drain region 46 serve as the source and drain, respectively, of the test element fabricated in the active area 20. Source region 44 and drain region 46 may be formed by masked implantation of dopant ions followed by annealing for thermal diffusion. The ion implantation energy, dopant implantation density, and thermal diffusion conditions may be set according to the characteristics of the test device. When the test element to be formed is an N-type MOSFET, ion implantation of an N-type dopant (phosphorus P or arsenic As) may be performed on the surface of the semiconductor substrate 100, and then the dopant is diffused by annealing, thereby forming the source region 44 and the drain region 46. For example, the implantation dose is first 1 × 10¹⁵/cm²~5×10¹⁵/cm²Is ion implanted and then annealed at a high temperature of about 1000 c to form source and drain regions 44 and 46. When the test device to be formed is a P-type MOSFET, a P-type dopant (boron B or boron difluoride BF) can be applied to the surface of the semiconductor substrate 100₂) Followed by annealing to form source region 44 and drain region 46. For example, the implantation dose is first 1 × 10¹⁵/cm²~5×10¹⁵/cm²Is ion implanted and then annealed at a high temperature of about 1000 c to diffuse the dopants, thereby forming source and drain regions 44 and 46. Source regionA source electrode and a drain electrode are formed in the region 44 and the drain region 46, respectively.

In the above manner, the semiconductor test structure 102 described in this embodiment mode can be formed. That is, semiconductor test structures 102 may be formed within a plurality of local regions 104 such that the local regions have redundant regions 22 arranged in a manner that forms a different pattern density.

FIGS. 16 and 17 are enlarged cross-sectional views of semiconductor test structures according to embodiments of the present invention. Specifically, the embodiment of fig. 16 is suitable for setting the pattern density of the local region when performing the cmp process. For the local region 104 with the proper pattern density in the semiconductor test structure 102, when performing the cmp process under the set conditions, since the pattern density is appropriate and the polishing speed is within the set range, the excess filling layer 34 can be removed within the set time without being excessively removed, and thus, substantially no Dishing (Dishing) is formed in the filling layer 34. In contrast, the embodiment of fig. 17 is not suitable for performing the cmp process with the pattern density of the local region set to be less than the lower limit. For the case represented by fig. 17, when performing the cmp under the set conditions, the pattern density in the semiconductor test structure 102 is small, so that the filling layer 34 is excessively thinned, thereby forming a recess (Dishing) with a depth X in the filling layer 34. Such a recess may become a cause of an influence of the parasitic transistor Trp on the active region 20 formed thereat.

Fig. 18 shows an exemplary measurement result of a relationship between a threshold voltage Vth of a MOSFET provided in an active region and a pattern density according to an embodiment of the present invention. Fig. 19 shows exemplary measurement results of the relationship between the saturated drain current Idsat and the pattern density of the MOSFET disposed in the active area according to an embodiment of the present invention.

Referring to fig. 17 and 19, in a high pattern density region where the pattern density is 25% or more, both the threshold voltage Vth and the saturated drain current Idsat exhibit flatness with respect to the pattern density, as compared to a low pattern density region where the pattern density is less than 25%. In contrast, in a low pattern density region where the pattern density is less than 25%, the threshold voltage Vth is greatly reduced and the saturated drain current Idsat is greatly increased with a change in the pattern density, and thus the degree of dependence on the pattern density is large. The characteristic variation in the low pattern density region indicates that the implementation of the chemical mechanical polishing process results in the formation of parasitic transistors for the active region 20. Therefore, in the embodiment shown in fig. 18 and 19, the lower limit value of the pattern density for the chemical mechanical polishing method is preferably set to 25%.

In summary, by using the semiconductor test structure of the embodiment of the invention, the lower limit of the pattern density for the chemical mechanical polishing process can be properly determined. Accordingly, a semiconductor device designer can make an appropriate design rule.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A semiconductor test structure comprising a plurality of local regions provided on a semiconductor substrate, each of the local regions defining an effective region and a plurality of redundant regions provided around the effective region by a trench isolation structure formed in the semiconductor substrate, wherein the effective region is provided with a test element connected to an electrode in such a manner that an electrical characteristic can be measured, and the redundant regions are distributed in such a manner that a pattern density of the plurality of local regions is different from each other; the semiconductor test structure is used for comparing the electrical characteristic results obtained by different local areas by measuring the electrical characteristics of the test element to obtain a lower limit value of the pattern density corresponding to the chemical mechanical polishing process.

2. The semiconductor test structure of claim 1, wherein a pattern density of the plurality of local regions is distributed in a range of 5% to 80%.

3. The semiconductor test structure of claim 1, wherein a disposition pitch of two adjacent redundancy regions is in a range of from above 1/100 to below 1/5 of a side length of the local region.

4. The semiconductor test structure of claim 3, wherein a size of each of the redundant regions is in a range of 1/10 up to 9/10 down of the set pitch.

5. The semiconductor test structure of claim 3, wherein the redundant regions are spaced at a fixed set pitch within the same local region.

6. The semiconductor test structure of any of claims 1 to 5, wherein each of the local regions has an upper surface of the trench isolation structure obtained by a same chemical mechanical polishing process, and the heights of the upper surfaces of the trench isolation structures are not completely the same between a plurality of the local regions.

7. The semiconductor test structure of any of claims 1 to 5, wherein the active areas are the same size among a plurality of the local areas, and the test elements are the same size and the same position where the corresponding active areas are disposed.

8. The semiconductor test structure of any one of claims 1 to 5, wherein the test element is a MOSFET and the semiconductor test structure is used to determine a threshold voltage and/or a saturation drain current of the MOSFET.

9. The semiconductor test structure of claim 8, wherein gate electrodes of the MOSFETs are arranged to extend to the surface of the trench isolation structure outside the respective active area.

10. The semiconductor test structure of any of claims 1 to 5, wherein an area of the local region is set to 100 μm x 100 μm to 500 μm x 500 μm.

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