CN112016258A

CN112016258A - Automatic energy-saving circuit for multi-memory SOC system

Info

Publication number: CN112016258A
Application number: CN202010858957.5A
Authority: CN
Inventors: 何学文; 李宇昂; 张雷; 张恩勤
Original assignee: Suzhou Sasama Semiconductor Co ltd
Current assignee: Suzhou Sasama Semiconductor Co ltd
Priority date: 2020-08-24
Filing date: 2020-08-24
Publication date: 2020-12-01

Abstract

The invention discloses an automatic energy-saving circuit for a multi-memory SOC (system on chip) system, which comprises an address prejudging device, a memory power supply controller and a voltage comparator, wherein the address prejudging device is connected with the memory power supply controller, the memory power supply controller is connected with a plurality of voltage selectors, the voltage selectors are all connected with the same memory power supply generator, the voltage selectors and the memory power supply generator are all connected with the voltage comparator, the voltage comparator is connected with the memory power supply controller, the voltage selectors are connected with a plurality of memories in a one-to-one correspondence manner, and the memories are in bidirectional connection with the system memory controller; the invention has the beneficial effects that: 1. the hardware automatically completes the power switching of a plurality of memories to achieve the effect of energy saving; 2. software is not needed to participate, and better energy-saving efficiency can be achieved; 3. most circuits are designed for digital logic and a small number of analog circuits, which are easy to implement in circuit design.

Description

Automatic energy-saving circuit for multi-memory SOC system

Technical Field

The invention relates to the field of integrated circuit design and application, in particular to an automatic energy-saving circuit for a multi-memory SOC system.

Background

In the current chip application field, the requirement of low power consumption is higher and higher; as an important component of a chip, the dynamic power consumption of a memory is usually a major component of the power consumption of a system-on-chip.

According to the characteristics of the memory, a relatively high supply voltage (operating voltage) is only required when access operation is performed, and in a static state, a value of the memory can be ensured not to be lost (holding voltage) only by a relatively low holding voltage; for NVM memories, the holding voltage may be 0V.

For the memory SOC system, the current power saving scheme is mostly based on software control, when a certain memory needs to be operated, the memory is configured to be active in advance, and the temporarily unused memory is switched to be inactive, as shown in fig. 1.

However, this method has obvious technical problems: 1. software participation and uniform allocation are required, so that the software overhead is increased; 2. automatic control cannot be realized, and energy saving efficiency is not good enough.

Disclosure of Invention

The present invention is directed to an automatic power saving circuit for a multi-memory SOC system, so as to solve the problems mentioned in the background art.

In order to achieve the purpose, the invention provides the following technical scheme:

an automatic energy-saving circuit for a multi-memory SOC system comprises an address prejudging device, a memory power supply controller and a voltage comparator, wherein the address prejudging device is connected with the memory power supply controller, the memory power supply controller is connected with a plurality of voltage selectors, the voltage selectors are connected with the same memory power supply generator, the voltage selectors and the memory power supply generator are connected with the voltage comparator, the voltage comparator is connected with the memory power supply controller, the voltage selectors are connected with a plurality of memories in one-to-one correspondence, and the memories are bidirectionally connected with the system memory controller; the address pre-judging device and the system memory controller are also connected with the address pre-judging device.

The system memory controller is provided with a control bus, a data bus and an address bus, and the address bus is also connected with the address prejudging device.

As a preferred embodiment of the present invention: the address pre-judging device has three judging methods, namely a boundary judging method, a use frequency judging method and a hysteresis keeping method; the method specifically comprises the following steps: 1. boundary judgment method: when the current operation address is close to a certain memory boundary, informing the adjacent memory to enter an active state; when the current operation address is far away from the boundary, informing the adjacent memory to enter an inactive state; 2. using a frequency judging method: when the use frequency of a certain memory is high, the memory can be locked and kept in an active state until the use frequency of the memory is reduced to a certain degree; 3. hysteresis holding method: when an operation address jumps out of a certain memory block, the memory block can be kept in an active state for a period of time, and the memory block can be put into an inactive state if the memory block is not reused in the period of time.

Compared with the prior art, the invention has the beneficial effects that: 1. the hardware automatically completes the power switching of a plurality of memories to achieve the effect of energy saving;

2. software is not needed to participate, and better energy-saving efficiency can be achieved;

3. most circuits are designed for digital logic and a small number of analog circuits, which are easy to implement in circuit design.

Drawings

FIG. 1 is a circuit diagram of a conventional power saving scheme for a memory.

Fig. 2 is a schematic circuit diagram of the present invention.

FIG. 3 is a diagram illustrating a power switching process of the memory according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

referring to fig. 2, an automatic energy saving circuit for a multi-memory SOC system includes an address pre-judging device, a memory power supply controller and a voltage comparator, the address pre-judging device is connected to the memory power supply controller, the memory power supply controller is connected to a plurality of voltage selectors, the plurality of voltage selectors are all connected to a same memory power generator, the plurality of voltage selectors and the memory power generator are all connected to the voltage comparator, the voltage comparator is connected to the memory power supply controller, the plurality of voltage selectors are connected to a plurality of memories in one-to-one correspondence, and the memories are connected to the system memory controller in a bidirectional manner; when the circuit works, the point source generator is led to be taken out to output the operation voltage and the holding voltage to the voltage selector, the voltage comparator is output with the reference voltage, the voltage comparator outputs a power-on completion signal to the power supply controller of the memory, and the power supply controller and the address prejudging device carry out signal exchange; the voltage values at this time are in the order of memory operation voltage > reference voltage (the lowest safe voltage required for memory operation) > memory holding voltage; the address pre-judging device and the system memory controller are also connected with the address pre-judging device, and when the address pre-judging device works, the address pre-judging device sends an operation permission signal to the system memory controller.

Meanwhile, the system memory controller is provided with a control bus, a data bus and an address bus, and the address bus is also connected with the address prejudging device.

The address prejudging device is used for prejudging the operation address of the system memory controller, ensuring that the currently operated memory is in an active state (an operation voltage power supply state), predicting the next memory needing to enter the active state, and timely informing the memory power supply controller to switch the operation voltage in advance, wherein other memories without correlation are maintained in a voltage holding state.

The memory power supply controller, the voltage selector and the voltage comparator complete the switching and control of all memory power supplies, and the power consumption of the whole memory is reduced to the maximum extent on the premise of ensuring the correct memory access operation.

When the address prejudging device requests a certain memory to enter an active state, the power supply controller of the memory controls the corresponding voltage selector to switch the power supply, and simultaneously selects the power supply of the memory to carry out threshold judgment on the voltage comparator.

As shown in fig. 3, when the power supply voltage of the memory exceeds the reference voltage, the active state of the memory is considered to be powered on completely, and a power-on completion signal is obtained, the memory power supply controller feeds back the information of the power-on completion of the target memory to the address pre-judging device, and then the address pre-judging device sends an operation permission signal to the memory controller of the system to allow the memory controller to operate the memory; if the memory controller of the system does not obtain the operation permission signal when operating a certain memory, the system needs to wait until the address prejudging device confirms that the target memory is powered on and sends out the operation permission signal.

In addition, the operating voltage, the holding voltage, and the reference voltage of each memory may be different in different chip systems, and at this time, the memory power generator is required to generate multiple operating voltages, holding voltages, and reference voltages for the chip systems to use, so as to further complete the energy saving design of the present invention.

Example 2:

on the basis of the embodiment 1, the address pre-judging device has three judging methods, namely a boundary judging method, a use frequency judging method and a hysteresis keeping method; the method specifically comprises the following steps: 1. boundary judgment method: when the current operation address is close to a certain memory boundary, informing the adjacent memory to enter an active state; when the current operation address is far away from the boundary, informing the adjacent memory to enter an inactive state; 2. using a frequency judging method: when the use frequency of a certain memory is high, the memory can be locked and kept in an active state until the use frequency of the memory is reduced to a certain degree; 3. hysteresis holding method: when an operation address jumps out of a certain memory block, the memory block can be kept in an active state for a period of time, and the memory block can be put into an inactive state if the memory block is not reused in the period of time.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. The automatic energy-saving circuit is characterized by comprising an address prejudging device, a storage power supply controller and a voltage comparator, wherein the address prejudging device is connected with the storage power supply controller, the storage power supply controller is connected with a plurality of voltage selectors, the voltage selectors are all connected with the same storage power supply generator, the voltage selectors and the storage power supply generator are all connected with the voltage comparator, the voltage comparator is connected with the storage power supply controller, the voltage selectors are connected with a plurality of storages in one-to-one correspondence, and the storages are in bidirectional connection with the system storage controller.

2. The automatic power saving circuit for multi-memory SOC system of claim 1, wherein the address pre-decider and system memory controller are further connected to the address pre-decider.

3. The automatic power saving circuit for a multi-memory SOC system of claim 1 or 2, wherein the system memory controller has a control bus, a data bus and an address bus.

4. The automatic power saving circuit for a multi-memory SOC system of claim 3, wherein the address bus is further connected with an address pre-decider.

5. The automatic power saving circuit for multi-memory SOC system of claim 1 or 2, wherein the address pre-decider has three judgments, respectively, a boundary judgments, a usage frequency judgments and a hysteresis holding method.

6. The automatic power saving circuit for a multi-memory SOC system of claim 5, wherein the boundary determination method: when the current operation address is close to a certain memory boundary, informing the adjacent memory to enter an active state; when the current operation address is far away from the boundary, the adjacent memory is informed to enter an inactive state.

7. The automatic power saving circuit for a multi-memory SOC system of claim 5, wherein the usage frequency determination method: when a memory is used with a high frequency, the memory can be locked out from being active until the memory usage frequency drops to a certain level.

8. The automatic power saving circuit for a multi-memory SOC system of claim 5, wherein the hysteresis hold method: when an operation address jumps out of a certain memory block, the memory block can be kept in an active state for a period of time, and the memory block can be put into an inactive state if the memory block is not reused in the period of time.