CN112015610A - Test sequence generation method, device, equipment and medium - Google Patents
Test sequence generation method, device, equipment and medium Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The embodiment of the invention discloses a method, a device, equipment and a medium for generating a test sequence. The method comprises the following steps: determining an equivalent circuit model of a system to be tested according to a plurality of modules to be tested in the system to be tested; determining a complex network model of the system to be tested according to the equivalent circuit model; and determining the importance factor of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factors. The technical scheme of the embodiment of the invention can improve the test precision and reduce the test time.
Description
Technical Field
The present invention relates to testing technologies, and in particular, to a method, an apparatus, a device, and a medium for generating a test sequence.
Background
With the continuous development of industrial equipment, the functions of the industrial equipment are more and more advanced, and when the industrial equipment is tested, various test indexes are mutually influenced and mutually constrained. How to reasonably set a test flow becomes an important step for carrying out system test on industrial equipment.
At present, testing of each system (such as a communication and navigation system in an aircraft) of industrial equipment is mainly realized by combining an online testing technology and a fault diagnosis technology, and testing of the whole system is completed by testing functions of each module in the system step by step.
However, with the advent of artificial intelligence technology, particularly methods such as knowledge engineering and expert system, the coupling between modules is becoming stronger and stronger, and when the existing test diagnosis method is used to perform coordination integrated test on each module, the influence of the correlation between modules on the test result cannot be dealt with, thereby resulting in the reduction of test precision and the increase of test time.
Disclosure of Invention
The embodiment of the invention provides a method, a device, equipment and a medium for designing a test sequence, which improve the test precision and reduce the test time.
In a first aspect, an embodiment of the present invention provides a method for generating a test sequence, including:
determining an equivalent circuit model of a system to be tested according to a plurality of modules to be tested in the system to be tested;
determining a complex network model of the system to be tested according to the equivalent circuit model;
and determining the importance factor of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factor.
In a second aspect, an embodiment of the present invention further provides a device for generating a test sequence, including:
the equivalent circuit model determining module is used for determining an equivalent circuit model of the system to be tested according to a plurality of modules to be tested in the system to be tested;
the complex network model determining module is used for determining a complex network model of the system to be tested according to the equivalent circuit model;
and the test sequence generation module is used for determining the importance factor of each module to be tested in the complex network model and generating a test sequence comprising a plurality of modules to be tested according to the importance factor.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
one or more processors;
storage means for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors implement the method for generating the test sequence provided by any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for generating a test sequence according to any embodiment of the present invention.
The embodiment of the invention provides a method, a device, equipment and a medium for generating a test sequence, wherein an equivalent circuit model equivalent to the structure of a system to be tested is correspondingly generated according to the distribution of a plurality of modules to be tested in the system to be tested, the equivalent circuit model is converted into a complex network model, the importance factors of each module to be tested in the complex network model are determined, the test sequence for testing the plurality of modules to be tested is generated according to the ordering of the importance factors, the test sequence integrates the functions of the modules to be tested in the system to be tested, the coupling among the modules to be tested and the relationship between the modules to be tested and other devices in the system to be tested, and the incidence relationship is used as a reference factor in the test process. The method solves the problem that the correlation among the modules cannot be dealt with to influence the test result when the existing test diagnosis method is used for carrying out the coordination integrated test on each module, and achieves the effects of improving the test precision and reducing the test time.
Drawings
Fig. 1 is a flowchart of a method for generating a test sequence according to an embodiment of the present invention;
fig. 2a is a flowchart of a method for generating a test sequence according to a second embodiment of the present invention;
fig. 2b is a schematic structural diagram of a relational topology according to a second embodiment of the present invention;
fig. 2c is a schematic structural diagram of a weighted topology according to a second embodiment of the present invention;
fig. 3a is a flowchart of a method for generating a test sequence according to a third embodiment of the present invention;
fig. 3b is a schematic structural diagram of a relational topology according to a third embodiment of the present invention;
fig. 3c is a schematic structural diagram of a weighted topology according to a third embodiment of the present invention;
fig. 3d is a schematic structural diagram of an equivalent circuit model according to a third embodiment of the present invention;
fig. 3e is a schematic diagram of an equivalent circuit structure for calculating correlation according to a third embodiment of the present invention;
fig. 4 is a flowchart of a method for generating a test sequence according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a test sequence generation apparatus according to a fifth embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to a sixth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a flowchart of a method for generating a test sequence according to an embodiment of the present invention, where this embodiment is applicable to a situation of performing test sequencing on multiple modules to be tested, typically, multiple modules to be tested belong to the same system to be tested, and there is an association relationship between the modules to be tested. The method can be executed by the generation device of the test sequence provided by the embodiment of the invention, and the device can be realized in a software and/or hardware manner and can be integrated in the electronic equipment.
As shown in fig. 1, the method of this embodiment specifically includes:
The system under test may be a system that is relied upon when a certain function is implemented in the industrial equipment, for example, a communication system in the flight equipment. The module to be tested is a module for specifically implementing system functions in a system to be tested, for example, in a Communication system of a flight device, the module to be tested includes a Very High Frequency Omnidirectional navigation (VOR) module, a course Beacon (LOC) module, a Glide Beacon (Glide Slope, G/S) module, a Communication Frequency Modulation (COMM FM) module, a Communication Amplitude Modulation (COMM AM) module, a COMM AM (COMM AM) module, a Selective call (SELCAL) module, a Communication Single Side Band (COMM SSB) module, a Marker Beacon (MB) 243 module, a Marker Beacon (121.5/Beacon) 406, and a Beacon (beon) module.
In this embodiment, the equivalent circuit model corresponding to the system under test is determined according to the function of each module under test in the system under test, the association relationship between the modules under test, and the relationship between the module under test and other devices. Namely, the incidence relation between each module to be tested and the outside is expressed in a circuit form through equivalent transformation, so that the current system to be tested is quantized.
And step 120, determining a complex network model of the system to be tested according to the equivalent circuit model.
The complex network model is a quantitative model established based on a complex network, and the complex network refers to a network with partial or all properties of self-organization, self-similarity, attractors, small worlds and no scale.
In this embodiment, the equivalent circuit model is converted into a complex network model, and a plurality of nodes representing the module to be tested are quantitatively calculated based on the node concept in the complex network model, so that the detection of the importance degree of the module to be tested can be realized, and the test sequence is determined.
The method for determining the importance of the internal nodes of the test module based on the complex network model belongs to the prior art, and in the implementation, the method is applied to the practical application of determining the test sequence of the test module.
Specifically, in this embodiment, the importance factor of the node corresponding to each module to be tested in the complex network model may be determined, that is, the importance level of each module to be tested in the system to be tested is determined, where the importance level reflects the importance of the function of the module to be tested in the system to be tested and the importance of the association relationship between the module to be tested and other modules to be tested. By determining the importance factor of each module to be tested, all the modules to be tested can be sequenced, so that the test modules in the test sequence are arranged from strong to weak according to the importance, and a theoretical basis is provided for the test process.
The embodiment of the invention provides a method for generating a test sequence, which generates an equivalent circuit model equivalent to the structure of a system to be tested correspondingly according to the distribution of a plurality of modules to be tested in the system to be tested, converts the equivalent circuit model into a complex network model, generates the test sequence for testing the plurality of modules to be tested by determining the importance factors of each module to be tested in the complex network model and sequencing the importance factors, wherein the test sequence integrates the positions of the modules to be tested in the system to be tested, the coupling among the modules to be tested and the relationship between the modules to be tested and other devices in the system to be tested, and really takes the association relationship as a reference factor in the test process. The method solves the problem that the correlation among the modules cannot be dealt with to influence the test result when the existing test diagnosis method is used for carrying out the coordination integrated test on each module, and achieves the effects of improving the test precision and reducing the test time.
Example two
Fig. 2a is a flowchart of a method for generating a test sequence according to a second embodiment of the present invention, where this embodiment may be combined with various alternatives in one or more of the above embodiments, and in this embodiment, determining an equivalent circuit model of a system under test according to a plurality of modules under test in the system under test may include: establishing a relation topological graph of a system to be tested, wherein the relation topological graph at least comprises a plurality of modules to be tested; determining the weight value of each edge in the relational topological graph to form a weighted topological graph; and converting the weighted topological graph into an equivalent circuit model of the system to be tested.
Correspondingly, the method of the embodiment of the invention comprises the following steps:
The relational topological graph at least comprises a plurality of modules to be tested.
In this embodiment, the relational topology refers to a structure diagram formed by a plurality of modules to be tested and a communication medium. Generally, a relational topology is established according to the connection relationship between a module to be tested and other communication media in a system to be tested.
In an optional implementation manner of this embodiment, the system under test includes: the device comprises a control layer, a physical layer and a functional layer, wherein the physical layer comprises a plurality of information transmitting and receiving devices, the functional layer comprises a plurality of modules to be tested, the control layer is connected with the information transmitting and receiving devices, and the information transmitting and receiving devices are connected with the corresponding modules to be tested.
The information transceiver is a communication medium and is used for realizing data interaction between the module to be tested and the control layer of the system to be tested.
Specifically, establishing a relationship topological graph of the system to be tested includes:
respectively abstracting the control layer, the information transceiver and the module to be tested into nodes in a relational topological graph;
establishing a connection edge between corresponding nodes according to the relationship between the control layer and the information transceiver;
and establishing a connection edge between corresponding nodes according to the relation between the information transceiver and the module to be tested.
Exemplarily, taking a communication system in a flight device as an example, the information transceiver is a physical antenna, is located at a physical layer, and respectively includes: VOR physical antennas, Instrument Landing System (ILS) physical antennas, Communication very High Frequency (COMMVHF) physical antennas, Communication High Frequency (mhf) physical antennas, MB physical antennas, and Emergency Location Transmitter (ELT) physical antennas. The modules to be tested (VOR, LOC, G/S, COMM FM, COMM AM, SELCAL, COMM SSB, MB, 121.5/243BEACON and 406BEACON) are located at the functional layer, as shown in FIG. 2 b. The control layer, all modules to be tested and all physical antennas of the communication system are abstracted into nodes, a connecting edge exists between each module to be tested and the corresponding physical antenna, and a connecting edge exists between each physical antenna and the control layer.
Therefore, the optional embodiment provides specific steps for establishing the relation topological graph of the system to be tested based on the structural characteristics of the system to be tested, and ensures the accuracy of the obtained relation topological graph.
And step 220, determining the weight value of each edge in the relation topological graph to form a weighted topological graph.
In this embodiment, in order to determine the quantization relationship between the modules to be tested and the system to be tested, a weight value needs to be set for each edge in the relationship topological graph to form a weighted topological graph. The different weight principle is adopted as the weighting principle, that is, the larger the weight value is, the farther the relationship between the two is.
For example, in the communication system of the flight device, since the association between the control layer and the physical layer is weak and the coupling between the physical layer and the functional layer is strong, the weight value of each edge between the control layer and the physical layer is set to 10, and the weight value of each edge between the physical layer and the functional layer is set to 1, as shown in fig. 2 c.
And step 230, converting the weighted topological graph into an equivalent circuit model of the system to be tested.
In this embodiment, after the weighted topological graph is obtained, the weighted topological graph is converted into the equivalent circuit model of the system to be tested according to the conversion rule between the topological graph and the equivalent circuit model.
And 240, determining a complex network model of the system to be tested according to the equivalent circuit model.
And 250, determining the importance factor of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factor.
The technical scheme of the embodiment provides a specific step of determining an equivalent circuit model of a system to be tested according to a plurality of modules to be tested in the system to be tested, a relation topological graph corresponding to the system to be tested is determined, weighted values are given to all edges in the relation topological graph to form a weighted topological graph, the weighted topological graph is converted into the equivalent circuit model, the conversion process from the actual system to be tested to the equivalent circuit model is achieved, the obtained equivalent circuit model is guaranteed to actually reflect the functions and relation levels of the modules to be tested in the system to be tested, and an accurate model foundation is laid for subsequently determining a complex network model and calculating importance factors.
EXAMPLE III
Fig. 3a is a flowchart of a method for generating a test sequence according to a third embodiment of the present invention, where this embodiment may be combined with various optional solutions in one or more embodiments described above, in this embodiment, when there is a relationship between modules to be tested, after a connection edge between corresponding nodes is established according to the relationship between an information transceiver and the modules to be tested, the method may further include: establishing a switching edge between corresponding nodes according to the relation between the modules to be tested; converting the weighted topological graph into an equivalent circuit model of the system under test may include: converting the node corresponding to the control layer and the node corresponding to the information transceiver into a circuit node of an equivalent circuit model, and converting the node corresponding to the module to be tested into a circuit port of the equivalent circuit model; converting the connecting edge containing the weight value into a resistance branch of the equivalent circuit model, wherein the resistance value of the resistance branch is the corresponding weight value; and converting the switching edge into a voltage-controlled switch of the complex network model, wherein a control port of the voltage-controlled switch is connected with an adjacent node.
Correspondingly, the method of the embodiment of the invention comprises the following steps:
In this embodiment, the system under test includes: the system comprises a control layer, a physical layer and a functional layer, wherein the physical layer comprises a plurality of information receiving and transmitting devices and is used for realizing the physical connection between the control layer and the functional layer, and the functional layer comprises a plurality of modules to be tested and is used for realizing the specific functions of a system to be tested. Specifically, the control layer is connected with a plurality of information transceiver devices, and the information transceiver devices are connected with corresponding modules to be tested.
And step 320, establishing a connection edge between corresponding nodes according to the relationship between the control layer and the information transceiver.
And 340, when the relation exists between the modules to be tested, establishing the switching edges between the corresponding nodes according to the relation existing between the modules to be tested.
In this embodiment, when there is a relationship between modules to be tested (for example, in a communication system of a flight device, a frequency band shared by a VOR module and a LOC module, and a frequency band shared by a COMM AM module and a SELCAL module), a switching edge between the modules to be tested is correspondingly established.
An exemplary relationship topology of the communication system of the flight device is shown in fig. 3 b.
It should be noted that the switching edge is only disposed between the two associated modules to be tested, and does not affect other modules to be tested.
And step 350, determining the weight value of each edge in the relation topological graph to form a weighted topological graph.
For the communication system of the flight equipment, considering the relevance between the modules in the functional layer, the weight value of the switching edge is set to 5, and the obtained weighted topological graph is shown in fig. 3 c.
And step 360, converting the node corresponding to the control layer and the node corresponding to the information transceiver into a circuit node of the equivalent circuit model, and converting the node corresponding to the module to be tested into a circuit port of the equivalent circuit model.
And the resistance value of the resistance branch is a corresponding weight value.
And the control port of the voltage-controlled switch is connected with the adjacent node.
In the present embodiment, step 360-380 is a specific conversion rule between the topology and the equivalent circuit model. Firstly, converting a node corresponding to a control layer and a node corresponding to an information transceiver into a circuit node of an equivalent circuit model, and converting a node corresponding to a module to be tested into a circuit port of the equivalent circuit model, wherein the circuit node is a node having a current input/output flow direction in a circuit, and the circuit port is a node having no current flow direction in the circuit; secondly, will contain the resistance branch road of the connection limit conversion of weighted value to equivalent circuit model, wherein, the resistance value of resistance branch road is corresponding weighted value, that is to say in the equivalent circuit model that the communication system of flight equipment corresponds, the resistance value is respectively: 1 Ω, 5 Ω, and 10 Ω; and finally, converting the switching edge into a voltage-controlled switch of an equivalent circuit model, wherein a control port of the voltage-controlled switch is connected with an adjacent node, and the working principle of the voltage-controlled switch is as follows: when a potential difference exists between the two ports of the switch, the switch is turned on, and is turned off reversely.
An exemplary equivalent circuit model of the communication system of the flight device is shown in fig. 3 d.
And 390, determining a complex network model of the system to be tested according to the equivalent circuit model.
In an optional implementation manner of this embodiment, determining the complex network model of the system under test according to the equivalent circuit model includes:
calculating the relevance between nodes corresponding to any two modules to be tested in the equivalent circuit model, wherein the relevance is a corresponding current value when a preset voltage is applied between the nodes corresponding to any two modules to be tested;
and establishing an adjacency matrix corresponding to the complex network model according to the relevance.
In an equivalent circuit model of a communication system of flight equipment, when the relevance of two nodes is tested, a preset voltage U is applied to two ends of a corresponding circuit port0(setting U for convenience of calculation01V), the rest circuit ports are vacant, the node relevance is represented by the current I at the two ends of the circuit ports, and the relevance is stronger when the current is larger.
For example, taking the correlation between the VOR module and the LOC module as an example, a preset voltage U is applied to the two ends of the ports of the VOR and LOC circuits0The latter equivalent circuit is shown in fig. 3 e. The equivalent resistance is:
obtaining the relevance value of the VOR module and the LOC module as follows: 1/4.07 ≈ 0.245.
Based on this optional implementation, the obtained adjacency matrix corresponding to the complex network model is:
the corresponding relationship between the nodes and the module to be tested is shown in table 1.
TABLE 1
3100, determining importance factors of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factors.
The technical scheme of the embodiment provides a specific step after the connection edge between the corresponding nodes is established according to the relationship between the information transceiver and the module to be tested when the relationship exists between the modules to be tested, and a specific step of converting the weighted topological graph into the equivalent circuit model of the system to be tested, introduces the concept of switching the edge, and sets a specific conversion rule for converting the weighted topological graph into the equivalent circuit model, further ensures that the obtained equivalent model can reflect the functions and relationship grade of the module to be tested in the system to be tested, and lays an accurate model foundation for subsequently determining a complex network model and calculating an importance factor.
Example four
Fig. 4 is a flowchart of a method for generating a test sequence according to a fourth embodiment of the present invention, where this embodiment may be combined with each alternative in one or more of the foregoing embodiments, in this embodiment, determining an importance factor of each module to be tested in a complex network model, and generating a test sequence including a plurality of modules to be tested according to the importance factor may include: calculating the importance factors of each module to be tested in the current complex network model, determining the node with the highest importance factor as a target node, and adding the target node into a test sequence; deleting the target node from the complex network model to update the complex network model; and taking the updated complex network model as the current complex network model, repeatedly executing the operation of determining the target node and adding the target node into the test sequence until all the modules to be tested are added into the test sequence.
Correspondingly, the method of the embodiment of the invention comprises the following steps:
and step 410, abstracting the control layer, the information transceiver and the module to be tested into nodes in the relational topology graph respectively.
And step 420, establishing a connection edge between corresponding nodes according to the relationship between the control layer and the information transceiver.
And step 450, determining the weight value of each edge in the relation topological graph to form a weighted topological graph.
And 470, converting the connection edge containing the weight value into a resistance branch of the equivalent circuit model.
And the resistance value of the resistance branch is a corresponding weight value.
And the control port of the voltage-controlled switch is connected with the adjacent node.
And 490, calculating the relevance between the nodes corresponding to any two modules to be tested in the equivalent circuit model.
The relevance is a corresponding current value when a preset voltage is applied between nodes corresponding to any two modules to be tested.
In this embodiment, the process of calculating the importance factor of each module to be tested in the complex network model may be: determining an adjacency matrix; normalizing the adjacent matrix and calculating a mutual information matrix; and performing row summation on the mutual information matrix, and taking the obtained row summation value as an importance factor of the corresponding node.
Based on the determined adjacency matrix of the complex network model corresponding to the communication system of the flight device in the previous embodiment, the obtained mutual information matrix is:
further, the obtained quantization importance factors of the respective nodes are shown in table 2.
TABLE 2
| Node point | Quantifying importance | Node point | Quantifying importance |
| v1 | -3.0205 | v6 | 2.5545 |
| v2 | 2.5545 | v7 | 0.4715 |
| v3 | 0.4715 | v8 | -7.0005 |
| v4 | 0.4715 | v9 | 0.4715 |
| v5 | 2.5545 | v10 | 0.4715 |
It can be seen that, where node v2、v5And v6Is more important than other nodes, any one of the three nodes can be selected as a target node and added into the test sequence.
And 4130, taking the updated complex network model as the current complex network model, repeatedly executing the operation of determining the target node and adding the target node into the test sequence until all the modules to be tested are added into the test sequence.
In this embodiment, after the current target node is determined and added to the test sequence, the node is deleted, and an updated complex network model is obtained based on the equivalent circuit model. And re-determining the target node aiming at the updated complex network model, adding the new target node into the test sequence, and continuously updating the complex network model until all the nodes in the complex network model are added into the test sequence to generate the test sequence comprising all the modules to be tested.
The technical scheme of the embodiment provides a specific step of determining the importance factor of each module to be tested in the complex network model, generating a test sequence comprising a plurality of modules to be tested according to the importance factor, continuously determining the target node, adding the determined target node into the test sequence, and then updating the complex network model, so that the functions of updating the incidence relation among the modules to be tested based on the importance factor of the modules to be tested, generating the test sequence based on the incidence relation and function limitation are realized, and the obtained test sequence meets the requirement of coordination integration test.
In an optional implementation manner of this embodiment, when the test sequence is not unique, after generating the test sequence including the plurality of modules under test, the method further includes:
determining prior costs of a plurality of modules to be tested;
determining the test cost of each test sequence according to the prior cost and the test sequence of a plurality of modules to be tested in each test sequence;
and taking the test sequence with the lowest test cost as the test sequence for finally testing the modules to be tested.
Because the generation of the test sequence is a dynamic process, the importance factors of the nodes in the current complex network model need to be calculated for many times. When the corresponding equivalent circuit model is constructed simply and the obtained adjacent matrix has low complexity, the situation that the weight values of all edges of the complex network model tend to be equal occurs, at the moment, the mutual information matrix obtained according to the adjacent matrix becomes a zero matrix, the difference of importance does not exist between nodes any more, namely, the obtained test sequence is not unique at the moment.
In this alternative embodiment, to overcome the above problems, a preferred test sequence is obtained, introducing the concept of test cost.
First, the a priori costs of a plurality of modules under test are determined. Typically, the prior cost may be determined based on empirical values, or a set of random arrays satisfying a normal distribution may be generated as the assumed value of the prior cost. And then, determining the test cost of each test sequence according to the prior cost and the test sequence of the modules to be tested in each test sequence.
Specifically, determining the test cost of each test sequence may be determining the test cost of each node in the test sequence, and summing the test costs to determine the test cost of the test sequence.
Setting the test cost of the test node as C (i), specifically expressed as: c (i) ═ Cs(i)+Cv(i) Wherein, Cs(i)＝0.5*c(i)，
Cs(i) Representing the fixed cost of the test node, C (i) representing the a priori cost of the test node, Cv(i) Represents the dynamic cost of the test node, w (i, j) represents the value at position (i, j) in the corresponding adjacency matrix when the current test node is added to the test sequence,
v (i) is a node set, and K (i) is a prior node set of the current test node i.
According to the setting, the size of the dynamic cost is in negative correlation with the information content of the prior node, and the larger the mutual information content of the prior node to the test node is, the lower the dynamic cost of the test node is; 2. when the mutual information quantity of the test node and the prior node is zero, C (i) ═ Cs(i)+Cv(i) (ii) c (i); 3 when the mutual information quantity of the test node and the prior node is equal to the information quantity of the test node, Cv(i) 0, c (i) 0.5 ═ c (i). The existing information of the previous test can simplify the subsequent test and reduce the test cost of the subsequent test.
In this optional embodiment, after determining the test cost of each test sequence, all the test costs are compared to determine the test sequence with the lowest test cost, and the test sequence is used as the test sequence for finally testing the plurality of modules to be tested.
Illustratively, for the example of the communication system of the flight device in the present embodiment, the a priori cost of 10 nodes is designed, and the a priori cost is satisfied as μ ═ 100, σ2A normal distribution of 10 is randomly generated, i.e., c (103.426135.784127.69486.501130.349107.25499.369107.14797.95098.759).
According to particular steps in this alternative embodiment, the preferred test sequence is determined from the plurality of test sequences as [ v [ ]6 v2 v4 v9 v10 v7 v5 v3 v1 v8]。
This alternative embodiment provides. When the test sequence is not unique, the specific steps after the test sequence containing a plurality of modules to be tested is generated are realized, and the advantages and disadvantages of the plurality of test sequences are considered from the cost perspective by introducing the concept of test cost, so that the test accuracy is ensured, the test cost is reduced, and the universality of the test mode is improved.
EXAMPLE five
Fig. 5 is a schematic structural diagram of a test sequence generation apparatus according to a fourth embodiment of the present invention, and as shown in fig. 5, the apparatus includes: an equivalent circuit model determination module 510, a complex network model determination module 520, and a test sequence generation module 530, wherein:
an equivalent circuit model determining module 510, configured to determine an equivalent circuit model of a system to be tested according to multiple modules to be tested in the system to be tested;
a complex network model determining module 520, configured to determine a complex network model of the system to be tested according to the equivalent circuit model;
the test sequence generating module 530 is configured to determine importance factors of each module to be tested in the complex network model, and generate a test sequence including a plurality of modules to be tested according to the importance factors.
The embodiment of the invention provides a test sequence generation device, which generates an equivalent circuit model equivalent to the structure of a system to be tested correspondingly according to the distribution of a plurality of modules to be tested in the system to be tested, converts the equivalent circuit model into a complex network model, generates a test sequence for testing the plurality of modules to be tested by determining the importance factors of each module to be tested in the complex network model and sequencing the importance factors, integrates the positions of the modules to be tested in the system to be tested, the coupling among the modules to be tested and the relationship between the modules to be tested and other devices in the system to be tested, and really takes the association relationship as a reference factor in the test process. The method solves the problem that the correlation among the modules cannot be dealt with to influence the test result when the existing test diagnosis method is used for carrying out the coordination integrated test on each module, and achieves the effects of improving the test precision and reducing the test time.
On the basis of the foregoing embodiments, the equivalent circuit model determining module may include:
the system comprises a relation topological graph establishing unit, a judging unit and a judging unit, wherein the relation topological graph establishing unit is used for establishing a relation topological graph of a system to be tested, and the relation topological graph at least comprises a plurality of modules to be tested;
the weighted topological graph forming unit is used for determining the weight value of each edge in the relational topological graph to form a weighted topological graph;
and the equivalent circuit model conversion unit is used for converting the weighted topological graph into an equivalent circuit model of the system to be tested.
On the basis of the above embodiments, the system under test includes: the system comprises a control layer, a physical layer and a functional layer, wherein the physical layer comprises a plurality of information transceiving devices, the functional layer comprises a plurality of modules to be tested, the control layer is connected with the plurality of information transceiving devices, and the information transceiving devices are connected with the corresponding modules to be tested;
the relationship topological graph establishing unit may include:
the node abstraction subunit is used for abstracting the control layer, the information transceiver and the module to be tested into nodes in the relational topology graph respectively;
a first connection edge establishing subunit, configured to establish a connection edge between corresponding nodes according to a relationship between the control layer and the information transceiver;
and the second connection edge establishing subunit is used for establishing a connection edge between corresponding nodes according to the relationship between the information transceiver and the module to be tested.
On the basis of the foregoing embodiments, the relationship topology graph establishing unit may further include:
and the switching edge establishing subunit is used for establishing a switching edge between the corresponding nodes according to the relationship between the information transceiver and the module to be tested after establishing a connecting edge between the corresponding nodes according to the relationship between the information transceiver and the module to be tested when the relationship exists between the modules to be tested.
The equivalent circuit model conversion unit may be specifically configured to:
converting the node corresponding to the control layer and the node corresponding to the information transceiver into a circuit node of an equivalent circuit model, and converting the node corresponding to the module to be tested into a circuit port of the equivalent circuit model;
converting the connecting edge containing the weight value into a resistance branch of the equivalent circuit model, wherein the resistance value of the resistance branch is the corresponding weight value;
and converting the switching edge into a voltage-controlled switch of an equivalent circuit model, wherein a control port of the voltage-controlled switch is connected with an adjacent node.
On the basis of the foregoing embodiments, the complex network model determining module 520 may include:
the correlation calculation unit is used for calculating the correlation between nodes corresponding to any two modules to be tested in the equivalent circuit model, wherein the correlation is a current value corresponding to a preset voltage applied between the nodes corresponding to any two modules to be tested;
and the adjacency matrix establishing unit is used for establishing the adjacency matrix corresponding to the complex network model according to the relevance.
On the basis of the foregoing embodiments, the test sequence generating module 530 may include:
the target node determining unit is used for calculating importance factors of each module to be tested in the current complex network model, determining a node with the highest importance factor as a target node, and adding the target node into a test sequence;
the target node deleting unit is used for deleting the target node from the complex network model so as to update the complex network model;
and the repeated execution unit is used for repeatedly executing the operation of determining the target node and adding the target node into the test sequence by taking the updated complex network model as the current complex network model until all the modules to be tested are added into the test sequence.
On the basis of the foregoing embodiments, the apparatus may further include:
and the prior cost determination module is used for determining the prior cost of the modules to be tested after generating the test sequence containing the modules to be tested when the test sequence is not unique.
A test cost determining module for determining the test cost of each test sequence according to the prior cost and the test sequence of the modules to be tested in each test sequence after generating the test sequence containing the modules to be tested when the test sequence is not unique
And the final test sequence determining module is used for taking the test sequence with the lowest test cost as the test sequence for finally testing the modules to be tested after generating the test sequence containing the modules to be tested when the test sequence is not unique.
EXAMPLE six
Fig. 6 is a schematic structural diagram of an electronic device according to a fifth embodiment of the present invention, as shown in fig. 6, the electronic device includes a processor 60 and a memory 61; the number of processors 60 in the device may be one or more, and one processor 60 is taken as an example in fig. 6; the processor 60 and the memory 61 in the device may be connected by a bus or other means, as exemplified by the bus connection in fig. 6.
The memory 61 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to a test sequence generation method in the embodiment of the present invention (for example, the equivalent circuit model determination module 510, the complex network model determination module 520, and the test sequence generation module 530 in the test sequence generation apparatus). The processor 60 executes various functional applications of the device and data processing, i.e., implements the above-described test sequence generation method, by executing software programs, instructions, and modules stored in the memory 61.
The memory 61 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 61 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 61 may further include memory located remotely from the processor 60, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
EXAMPLE seven
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method for generating a test sequence, the method including:
determining an equivalent circuit model of a system to be tested according to a plurality of modules to be tested in the system to be tested;
determining a complex network model of the system to be tested according to the equivalent circuit model;
and determining the importance factor of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factors.
Of course, the storage medium provided by the embodiment of the present invention and containing the computer-executable instructions is not limited to the method operations described above, and may also perform related operations in the method for generating the test sequence provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the above test sequence generation apparatus, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for generating a test sequence, comprising:
determining an equivalent circuit model of a system to be tested according to a plurality of modules to be tested in the system to be tested;
determining a complex network model of the system to be tested according to the equivalent circuit model;
and determining the importance factor of each module to be tested in the complex network model, and generating a test sequence comprising a plurality of modules to be tested according to the importance factor.
2. The method of claim 1, wherein determining the equivalent circuit model of the system under test according to the plurality of modules under test in the system under test comprises:
establishing a relation topological graph of the system to be tested, wherein the relation topological graph at least comprises a plurality of modules to be tested;
determining the weight value of each edge in the relation topological graph to form a weighted topological graph;
and converting the weighted topological graph into an equivalent circuit model of the system to be tested.
3. The method of claim 2, wherein the system under test comprises: the system comprises a control layer, a physical layer and a functional layer, wherein the physical layer comprises a plurality of information transceiving devices, the functional layer comprises a plurality of modules to be tested, the control layer is connected with the plurality of information transceiving devices, and the information transceiving devices are connected with the corresponding modules to be tested;
the establishing of the relationship topological graph of the system to be tested comprises the following steps:
abstracting the control layer, the information transceiver and the module to be tested into nodes in the relational topological graph respectively;
establishing a connection edge between corresponding nodes according to the relationship between the control layer and the information transceiver;
and establishing a connection edge between corresponding nodes according to the relation between the information transceiver and the module to be tested.
4. The method according to claim 3, wherein when there is a relationship between the modules under test, after the establishing a connection edge between corresponding nodes according to the relationship between the information transceiver device and the modules under test, further comprises:
establishing a switching edge between corresponding nodes according to the relation between the modules to be tested;
the converting the weighted topological graph into the equivalent circuit model of the system to be tested includes:
converting the node corresponding to the control layer and the node corresponding to the information transceiver into a circuit node of the equivalent circuit model, and converting the node corresponding to the module to be tested into a circuit port of the equivalent circuit model;
converting the connecting edge containing the weight value into a resistance branch of the equivalent circuit model, wherein the resistance value of the resistance branch is the corresponding weight value;
and converting the switching edge into a voltage-controlled switch of the equivalent circuit model, wherein a control port of the voltage-controlled switch is connected with an adjacent node.
5. The method according to any one of claims 3-4, wherein said determining the complex network model of the system under test according to the equivalent circuit model comprises:
calculating the relevance between nodes corresponding to any two modules to be tested in the equivalent circuit model, wherein the relevance is a corresponding current value when a preset voltage is applied between the nodes corresponding to any two modules to be tested;
and establishing an adjacency matrix corresponding to the complex network model according to the relevance.
6. The method according to claim 1, wherein the determining an importance factor of each module under test in the complex network model, and generating a test sequence including a plurality of modules under test according to the importance factor comprises:
calculating the importance factors of each module to be tested in the current complex network model, determining the node with the highest importance factor as a target node, and adding the target node into the test sequence;
deleting the target node from the complex network model to update the complex network model;
and taking the updated complex network model as the current complex network model, repeatedly executing the operation of determining the target node and adding the target node into the test sequence until all the modules to be tested are added into the test sequence.
7. The method of claim 1, wherein after the generating a test sequence including a plurality of modules under test when the test sequence is not unique, further comprising:
determining a priori costs of a plurality of the modules to be tested;
determining the test cost of each test sequence according to the prior cost and the test sequence of the modules to be tested in each test sequence;
and taking the test sequence with the lowest test cost as the test sequence for finally testing the modules to be tested.
8. An apparatus for generating a test sequence, comprising:
the equivalent circuit model determining module is used for determining an equivalent circuit model of the system to be tested according to a plurality of modules to be tested in the system to be tested;
the complex network model determining module is used for determining a complex network model of the system to be tested according to the equivalent circuit model;
and the test sequence generation module is used for determining the importance factor of each module to be tested in the complex network model and generating a test sequence comprising a plurality of modules to be tested according to the importance factor.
9. An electronic device, characterized in that the device comprises:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a method of generating a test sequence as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of generating a test sequence according to any one of claims 1 to 7.
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