CN112015382B - Processor architecture analysis method, device, equipment and storage medium - Google Patents
Processor architecture analysis method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a processor architecture parsing method, a processor architecture parsing device, a processor architecture parsing equipment and a storage medium. The method comprises the following steps: importing architecture deployment information of a processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of the entity; analyzing the architecture deployment information, and extracting entity role information, entity category information and entity position information; the entity role information comprises role classification and role names, the entity category information comprises a category and preset attributes, and the entity position information comprises a position and a role name; determining mounting port information between entities according to entity category information; determining entity information according to the entity role information; and determining the architecture of the processor according to the entity information, the mounting port information and the entity position information. According to the technical scheme, the processor architecture is determined by analyzing the architecture deployment information, so that the description of a unified architecture among the research and development teams is facilitated, and the response speed of the teams to the architecture development is accelerated.
Description
Technical Field
Embodiments of the present invention relate to computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for analyzing a processor architecture.
Background
With the increasing complexity of the current Artificial Intelligence (AI) processor chip, the types and the number of the core processing units are increasing, and the combination forms of the application-oriented core processing units included in the AI processors in different application fields are also different.
For processor development, multiple teams of children are required to work together. However, different research and development teams are responsible for different research and development focuses differently, in the prior art, a self-defined description method is usually provided for the architecture in the teams, but the description of the architecture by the different teams influences the readability of the architecture description, reduces the reaction speed of the teams for the development of the new architecture, increases the complexity of cooperation among teams, and further reduces the research and development efficiency of the processor.
Disclosure of Invention
The embodiment of the invention provides a method, a device, equipment and a storage medium for analyzing a processor architecture, which are used for improving the readability of the description of the processor architecture and improving the development efficiency of the processor architecture.
In a first aspect, an embodiment of the present invention provides a method for parsing a processor framework, including:
importing architecture deployment information of a processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of an entity;
analyzing the architecture deployment information, and extracting entity role information, entity category information and entity position information; the entity role information comprises a role classification and a role name, the entity category information comprises a category and a preset attribute, and the entity position information comprises a position and a role name;
determining mounting port information among the entities according to the entity category information;
determining entity information according to the entity role information;
and determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
In a second aspect, an embodiment of the present invention further provides a processor architecture parsing apparatus, including:
the architecture deployment information importing module is used for importing architecture deployment information of the processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of an entity;
the information extraction module is used for analyzing the architecture deployment information and extracting entity role information, entity category information and entity position information; the entity role information comprises a role classification and a role name, the entity category information comprises a category and a preset attribute, and the entity position information comprises a position and a role name;
the mounting port information determining module is used for determining mounting port information among the entities according to the entity category information;
the entity information determining module is used for determining entity information according to the entity role information;
and the architecture determining module is used for determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
In a third aspect, an embodiment of the present invention further provides a computer device, where the computer device includes:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a processor architecture parsing method as provided by any embodiment of the invention.
In a fourth aspect, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a processor architecture parsing method as provided by any of the embodiments of the present invention.
The embodiment of the invention determines the processor architecture by analyzing the architecture deployment information, solves the problem that the description of different teams on the architecture influences the readability of the architecture description, realizes the description of a unified architecture, accelerates the reaction speed of the teams on the architecture development, avoids repeatedly reconstructing an automation tool aiming at the architecture updating and lays a team cooperation foundation from the architecture level.
Drawings
FIG. 1 is a flowchart of a method for parsing a processor architecture according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for parsing a processor architecture according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a processor architecture parsing apparatus according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer device in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a processor architecture parsing method according to an embodiment of the present invention, where the embodiment is applicable to modeling a processor architecture and describing the architecture, and the method may be executed by a processor architecture parsing apparatus, which may be generally integrated in a computer device, and the method specifically includes the following steps:
the architecture deployment information of the processor is information describing architecture deployment according to a preset rule. The architecture elements in the processor can be described by adopting forms or character string texts and the like, and the architecture deployment information comprises the category, preset attributes, positions, role classification and role names of the entity. The category is the boundary of design entities in the architecture; the interconnection between design entities in the same category does not need to be realized by a bridging entity or a cross-border executor, and the interconnection between design entities outside the category boundary needs to be realized by a bridging entity or a cross-border executor. In a system, a plurality of domains can exist, and the domains can be nested and contained. Where a design entity exists a boundary within the architecture, a category is needed to identify the boundary. The executor is used as an initiator and a receiver of the request; the actuators are entities which independently complete work, and the actuators may be mounted in a plurality of categories or only in one category. The receiver receives only the request as the destination of the request; the receiver can not initiate a request and can not finish work independently, and the receiver needs to be matched with an actuator to finish work. The receiver may be mounted in one or more domains. The bridge does not originate as a source, does not serve any request, serves as a boundary interconnection of different categories, and is at least carried in 2 categories. A bridge must be at least in 2 categories, at most without limitation, which is neither the start nor the end of a request (or data).
the entity role information comprises role classification and role names, the entity category information comprises a category and preset attributes, and the entity position information comprises a position and a role name. Role names are used as surrogates for entities to indicate which entity the object described is. Role classification is used to describe the belonging of an entity to an actuator, receiver or bridge. The category to which the entity belongs includes a current category name and a parent category name corresponding to the entity, and may further include the number of current categories existing in the parent category. The preset attribute may include an active and passive attribute of the entity, that is, whether the entity has an active request initiating capability or not, and whether the entity has a passive request receiving and servicing capability, and may further include an interface bit width and a read-write attribute of the interface, that is, whether the entity has a read operation initiating or receiving capability or whether the entity has a write operation initiating or receiving capability or not. The location is a name including a category in which the entity is located, and is used for specifying the location of the entity, and may further include the number of current entities in the category in which the entity is located.
the entity category information includes a current category corresponding to the entity, a parent category corresponding to the entity, and the number of the current categories in the parent category. The category of each entity and the category distribution thereof can be obtained by analyzing the current category and the category of the parent of each entity, the category of the parent is the category of the entity at the top level, and the analysis of the category distribution is finished when meeting the category of the top level, so that the condition of the entity mounted in the category can be obtained according to the category information of the entities, and the mounting port information among the entities is obtained.
wherein, whether the entity can initiate the request, can receive the request or only transmit the request can be determined according to the role classification of the entity. According to the entity role information, the function of each entity in the architecture can be determined, and the function description of the entity is used as the entity information of each entity.
And 150, determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
In the above steps, the condition of the entity mounted in the category is determined, the function of the entity is also determined, and the basic analysis resource for determining the processor architecture is obtained by combining the position of the entity. Through the combination of the basic analysis resources, the logic relation definition of the entities in the architecture can be determined, all the entities can be accurate to the mounting interface, and all the entities and the functions thereof, all the entity mounting ports and all the categories and category inclusion relations in the architecture can be obtained. Therefore, the work of each port can be analyzed, the readability of the output port description is good, and the operation is convenient among different teams.
According to the technical scheme, the processor architecture is determined by analyzing the architecture deployment information, the problem that the description of the architecture by different teams influences the readability of the architecture description is solved, the description of the unified architecture is realized, the response speed of the teams to the architecture development is increased, repeated reconstruction of an automation tool for architecture updating is avoided, and a team cooperation foundation is laid from the architecture level.
Example two
Fig. 2 is a flowchart of a processor architecture parsing method according to a second embodiment of the present invention, which is further refined based on the foregoing technical solution, and for the architecture deployment information, a two-dimensional table of architecture deployment information may be used, where the two-dimensional table of architecture deployment information includes a category attribute column, a location column, a role classification column, and a role name column, and the architecture deployment situation of each entity is recorded in the same row. Optionally, the two-dimensional table of architecture deployment information at least includes one of the following: the category attribute column comprises a parent category, the number of the current categories, active and passive attributes, interface bit width, read-write attributes and the number of interfaces; the position column comprises the category of the entity and the number of the entity; the role classification of the role classification column record is one of the following: an actuator, a receiver, or a bridge.
Architecture deployment information two-dimensional table the following table 1 is an example,
TABLE 1
For the header part, FC denotes the category name, WZ denotes the location name, JS denotes the character classification, and JSMC denotes the character name. For the architecture deployment information two-dimensional table, the table deployment principle is as follows:
1. the list head category row can be expanded in an infinite row, namely, the category number is not limited. But the category names must be unique. Table 1 includes 6 category columns.
2. The position column, the role classification column and the role name column in the header are fixed columns, and the columns cannot be expanded.
3. The table head row is defaulted to be the first row of the table, the table content row is a role entity definition row, and the table content row can be expanded without limit from top to bottom, the number of roles is unlimited, the role names can be repeated, but at the same time, the deployment categories must be different.
4. The parent category is the same as the current category name, and the current category is represented as a top-level category and is a parent category root node.
For the architecture deployment information two-dimensional table, the table contents are defined as follows:
1. category list
FC in parent class, current FC number @ MS, interface bit width RW and interface number
The table contents of the category column are defined as follows:
parent FC (last _ FC), representing the parent FC name, the current FC name being the current list header. The parent FC contains the current FC.
The current FC number (FC _ num) indicates the number of current FCs that exist within the parent FC.
MS (mstslv), which represents the active and passive attributes of a role, M represents that the current entity has the active request initiating capability of operation, and S represents that the current entity has the passive receiving and service request capability of operation, and the attribute identifier may be M, S, MS. The MS has both the capability of actively initiating requests for operations and the capability of passively receiving and servicing requests for operations on behalf of the current entity.
Interface bit width (ifbw), which represents the current interface bit width and is identified by the number of bits. For example, 256 represents an interface with a bit width of 256 bits. The bit width is defined according to the architecture requirement and is not limited.
And RW (rwType) which represents the read-write attribute of the interface, R represents that the current entity has the read operation initiating or receiving capability, and W represents that the current entity has the write operation initiating or receiving capability. This attribute identification may be R, W, RW. RW is a device that has both read operation initiating or receiving capability and write operation initiating or receiving capability on behalf of the current entity.
The number of interfaces indicates the current entity, how many interfaces are in the current FC, and the number of interfaces is defined according to the architecture requirement and is not limited.
2. Position column (WZ)
FC of entity
The contents of the location list table are defined as follows:
and the FC where the entity is located represents the name of the FC where the entity is located, and is used for clarifying the location of the entity.
And the entity number represents the number of the current entities in the FC where the entities are located.
3. Role column (JS)
Role names are defined as follows:
ZXQ, representing an actuator, that may be the source of an operation and must have the ability to initiate the operation, and the ability to receive the operation is optional. ZXQ may be mounted to a plurality of FCs or may be mounted to only one FC.
QJQ, representing a bridge, which must be loaded on more than 2 FC (inclusive) and serve operation forwarding between different FCs, QJQ itself cannot be the source of operation, and it can realize operation forwarding between FCs in simplex or duplex form through interface definition
JSQ, meaning that the receiver can only receive requests, is the destination of the request, and it cannot initiate requests, cannot perform work independently, and does work in coordination with the executors. The receiver can be mounted on one FC or a plurality of FCs
4. Column role name (JSMC)
The role name may appear multiple times in different rows, but the contents of the FC column portion identified by all rows in which the duplicate role name is located must be different. That is, an identical design entity may appear multiple times within the fabric, but all such entities within the same FC must be defined in the same row, with different row definitions for such entities of different FCs.
Based on the row and column composition of the two-dimensional table of the architecture deployment information and the definition of the content in the table, the processor architecture analysis method comprises the following steps:
And step 230, extracting an entity role list and an entity category list from the category role two-dimensional hash table.
And 240, recursively searching the category relation expression in the entity category list, and positioning the entity position and the category distribution thereof to obtain a mounting port list. The domain relational expressions in the domain column are disassembled to generate a mount definition, for example, last _ FC: FC _ Num @ MstSlv: if BitWid th: rwType: if Num, recursive search of the domain relational expressions, GZ _ list.apend (last _ FC + (last _ FC [ i ] + (0.. FC _ Num-1))), where GZ _ list represents a mount port list, and the top FC class category is self, so that the recursive parent category encounters the top domain end (last _ FC = = FC _ list [ j ]) & (FC _ list [ j ] = = FC _ list [ i ]), and the mount port list GZ _ list is obtained through parsing.
And step 250, analyzing the entity role list, and classifying according to the contained entity roles to obtain the entity list. The entity role list is analyzed to obtain the role names and the corresponding role classifications of all entities in the framework, and the entity list is formed. (JSMC + (0.. JS _ num-1) + (0.. ifNum) + MstSlv), where ST _ list represents the entity manifest.
Step 260, performing segment combination on the mounting port list, the entity list and the position and role two-dimensional hash table to obtain an architecture definition, and storing the architecture definition to a preset list to obtain an architecture of the processor; the preset list comprises an entity list, a mounting port list and a category list. The mounting port list, the entity list and the position role two-dimensional hash table obtained by analyzing the architecture deployment two-dimensional table jointly form a resource pool defined by the architecture, and the mounting port list, the entity list and the position role two-dimensional hash table in the resource pool are combined in a segmented mode to obtain the architecture of the processor. For example, according to GZ _ list, ST _ list, and H _ ArchDef [ WZ ] [ JSMC ], H _ ArchDef [ WZ ] [ JSMC ] @ GZ _ list [ i ] + ST _ list [ j ], the combined entries are, for example: FC05_04@ FC00_00__ FC01_00__ FC02_00__ FC03_02__ FC04_01__ FC05_04__ ZXQ04_00__ M.
According to the analysis method for deploying the two-dimensional table based on the architecture, only parent category identification constraint, current category quantity constraint and other parts for describing the characteristics of the ports are performed on the contents of H _ ArchDef [ FC ] [ JSMC ], any constraint is not performed, and the method can be expanded at will. The naming of all the basic elements of the description architecture can be freely named, and the basic principle of the naming can be met. The intra-architecture core processing components are classified based on the definition of the basic elements of the architecture. A two-dimensional table is arranged through the architecture, a core processing component is arranged in the system, and relevant parameters are well defined. And finally, generating the architecture description by an architecture generation method based on the architecture deployment two-dimensional table.
The architecture can be modeled by using the architecture deployment two-dimensional table, the modeling method can define the processor system architecture at different system levels, a top system can be one processor or a plurality of processors, and the system level is not limited. The output result can be provided in a production system, the standard architecture description is unified, flexible extension can be provided, and the flexible extension, the custom addition and the deployment can be carried out in a sub-production system. The framework definition is simple and efficient, readability is high, and scene automatic generation based on the framework definition has universality. And (3) auxiliary framework exploration, framework assembly, path complexity analysis and directional scene combination research are carried out, and high-efficiency automation is realized. The modeling method and the automatically generated architecture description belong to an open framework, and except the definition of core elements and the basic principle followed by the analysis method, the method can be expanded or mapped to locally define the description method of the sub-team according to the special functions of the sub-team in all aspects.
Because the modeling method has high speed of outputting the architecture definition, the modeling method can be used as an auxiliary tool for processor architecture exploration, and once the new generation architecture exploration is basically stable, the modeling method can be quickly deployed to each sub-team. Meanwhile, the local description method which is self-defined by the stable sub-team according to the basic architecture description is stable and does not need to independently develop scripts or tools according to each chip, and the response speed of the sub-team to the new architecture development can be accelerated from the viewpoint of improving the efficiency.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a processor architecture parsing apparatus according to a third embodiment of the present invention, where the processor architecture parsing apparatus includes:
the architecture deployment information importing module 310 is configured to import architecture deployment information of a processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of the entity;
the information extraction module 320 is configured to analyze the architecture deployment information and extract entity role information, entity category information, and entity location information; the entity role information comprises role classification and role names, the entity category information comprises a category and preset attributes, and the entity position information comprises a position and a role name;
a mounting port information determining module 330, configured to determine mounting port information between entities according to entity category information;
an entity information determining module 340, configured to determine entity information according to the entity role information;
and an architecture determining module 350, configured to determine an architecture of the processor according to the entity information, the mounting port information, and the entity location information.
According to the technical scheme, the processor architecture is determined by analyzing the architecture deployment information, the problem that the description of the architecture by different teams influences the readability of the architecture description is solved, the description of the unified architecture is realized, the response speed of the teams to the architecture development is increased, repeated reconstruction of an automation tool for architecture updating is avoided, and a team cooperation foundation is laid from the architecture level.
Optionally, the architecture deployment information is an architecture deployment information two-dimensional table, where the architecture deployment information two-dimensional table includes a category attribute column, a location column, a role classification column, and a role name column, and the architecture deployment condition of each entity is recorded in the same row.
Optionally, the information extraction module is specifically configured to:
analyzing the architecture deployment two-dimensional table to obtain a category role two-dimensional hash table and a position role two-dimensional hash table;
and extracting an entity role list and an entity category list from the category role two-dimensional hash table.
Optionally, the mount port information determining module is specifically configured to:
and recursively searching the category relation expression in the entity category list, positioning the entity position and the category distribution thereof, and obtaining the mounting port list.
Optionally, the entity information determining module is specifically configured to:
and analyzing the entity role list, and classifying according to the contained entity roles to obtain the entity list.
Optionally, the architecture determination module is specifically configured to:
the mounting port list, the entity list and the position role two-dimensional hash table are combined in a segmented mode to obtain an architecture definition, and the architecture definition is stored in a preset list to obtain the architecture of the processor; the preset list comprises an entity list, a mounting port list and a category list.
Optionally, the two-dimensional table of architecture deployment information at least includes one of the following:
the category attribute column comprises a parent category, the number of the current categories, active and passive attributes, interface bit width, read-write attributes and the number of interfaces;
the position column comprises the category of the entity and the number of the entity;
the role classification of the role classification column record is one of the following: an actuator, a receiver, or a bridge.
Optionally, the category is a boundary of a design entity in the framework; for the design entities in the same category, the interconnection is not required to be realized through a bridging entity or a cross executor, and for the design entities outside the category boundary, the interconnection is required to be realized through the bridging entity or the cross executor;
the executor is used as an initiator and a receiver of the request;
the receiver receives only the request as the destination of the request;
the bridge does not originate as a source, does not serve any request, serves as a boundary interconnection of different categories, and is at least carried in 2 categories.
The processor architecture analysis device provided by the embodiment of the invention can execute the processor architecture analysis method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Example four
Fig. 4 is a schematic structural diagram of a computer apparatus according to a fourth embodiment of the present invention, as shown in fig. 4, the computer apparatus includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processors 410 in the computer device may be one or more, and one processor 410 is taken as an example in fig. 4; the processor 410, the memory 420, the input device 430 and the output device 440 in the computer apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 4.
The memory 420 serves as a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the processor architecture parsing method in the embodiment of the present invention (for example, the architecture deployment information importing module 310, the information extracting module 320, the mounting port information determining module 330, the entity information determining module 340, and the architecture determining module 350 in the processor architecture parsing apparatus). The processor 410 executes various functional applications and data processing of the computer device by executing software programs, instructions and modules stored in the memory 420, that is, implements the above-described processor architecture parsing method.
The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 420 may further include memory located remotely from processor 410, which may be connected to a computer device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 430 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus. The output device 440 may include a display device such as a display screen.
EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a processor architecture parsing method, where the method includes:
importing architecture deployment information of a processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of an entity;
analyzing the architecture deployment information, and extracting entity role information, entity category information and entity position information; the entity role information comprises a role classification and a role name, the entity category information comprises a category and a preset attribute, and the entity position information comprises a position and a role name;
determining mounting port information among the entities according to the entity category information;
determining entity information according to the entity role information;
and determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the processor architecture parsing method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the processor architecture parsing apparatus, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A method for processor architecture parsing, comprising:
importing architecture deployment information of a processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of an entity; the role classification comprises an executor, a receiver, or a bridge;
analyzing the architecture deployment information, and extracting entity role information, entity category information and entity position information; the entity role information comprises a role classification and a role name, the entity category information comprises a category and a preset attribute, and the entity position information comprises a position and a role name;
determining mounting port information among the entities according to the entity category information;
determining entity information according to the entity role information;
and determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
2. The method according to claim 1, wherein the architecture deployment information is an architecture deployment information two-dimensional table, wherein the architecture deployment information two-dimensional table includes a category attribute column, a location column, a role classification column, and a role name column, and the architecture deployment status of each entity is recorded in the same row.
3. The method of claim 2, wherein the parsing the architecture deployment information and extracting entity role information, entity category information, and entity location information comprises:
analyzing the architecture deployment two-dimensional table to obtain a category role two-dimensional hash table and a position role two-dimensional hash table;
and extracting an entity role list and an entity category list from the category role two-dimensional hash table.
4. The method of claim 3, wherein the determining the port information for mounting between the entities according to the entity category information comprises:
and recursively searching the category relation expression in the entity category list, positioning the entity position and the category distribution thereof, and obtaining a mounting port list.
5. The method of claim 4, wherein the determining entity information according to the entity role information comprises:
and analyzing the entity role list, and obtaining the entity list according to the contained entity role classification.
6. The method of claim 5, wherein determining the architecture of the processor according to the entity information, the mount port information, and the entity location information comprises:
the mounting port list, the entity list and the position role two-dimensional hash table are combined in a segmented mode to obtain an architecture definition, and the architecture definition is stored in a preset list to obtain the architecture of the processor; the preset list comprises an entity list, a mounting port list and a category list.
7. The method of claim 2, wherein the two-dimensional table of architecture deployment information comprises at least one of:
the category attribute column comprises a parent category, the number of the current categories, an active attribute, a passive attribute, an interface bit width, a read-write attribute and the number of interfaces;
the position column comprises a category of the entity and the number of the entity;
the role classification column records the role classification.
8. The method of claim 7, wherein the category is a boundary of a design entity within the architecture; for the design entities in the same category, the interconnection is not required to be realized through a bridging entity or a cross executor, and for the design entities outside the category boundary, the interconnection is required to be realized through the bridging entity or the cross executor;
the executor is used as an initiator and a receiver of the request;
the receiver receives only the request as the destination of the request;
the bridge does not originate as a source, does not serve any request, serves as a boundary interconnection of different categories, and is at least carried in 2 categories.
9. A processor architecture parsing apparatus, comprising:
the architecture deployment information importing module is used for importing architecture deployment information of the processor; the architecture deployment information comprises the category, preset attribute, position, role classification and role name of an entity; the role classification comprises an executor, a receiver, or a bridge;
the information extraction module is used for analyzing the architecture deployment information and extracting entity role information, entity category information and entity position information; the entity role information comprises a role classification and a role name, the entity category information comprises a category and a preset attribute, and the entity position information comprises a position and a role name;
the mounting port information determining module is used for determining mounting port information among the entities according to the entity category information;
the entity information determining module is used for determining entity information according to the entity role information;
and the architecture determining module is used for determining the architecture of the processor according to the entity information, the mounting port information and the entity position information.
10. A computer device, characterized in that the computer device comprises:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the processor architecture parsing method of any of claims 1-8.
11. A storage medium containing computer-executable instructions for performing the processor architecture parsing method of any one of claims 1-8 when executed by a computer processor.
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