CN112004262B - Radio Frequency Amplifying Device and Uplink and Downlink Time Slot Synchronization Method - Google Patents

Abstract

The invention provides a radio frequency amplification device and a method for synchronizing uplink and downlink time slots. The device includes: a radio frequency unit, which is used to output high-frequency signals and control signals for uplink and downlink transceiver switches; a power divider, an input terminal of the power divider Connect with the output end of described radio frequency unit; Amplifying unit, the output end of power splitter is connected with the input end of amplifying unit, and amplifying unit comprises: uplink and downlink send and receive switch; The high-frequency signal of radio frequency unit output passes through described power divider transmission To the first input end of the uplink and downlink transceiver switch, the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink transceiver switch through the power divider; the control signal is used to control the radio frequency amplification device Uplink and downlink time slots are synchronized. In the embodiment of the present invention, the radio frequency unit outputs the control signal of the uplink and downlink transceiver switches to the outside, and the control signal is transmitted to the amplifying unit through the feeder and the power divider, so as to realize the synchronization of the uplink and downlink time slots.

Description

Radio Frequency Amplifying Device and Uplink and Downlink Time Slot Synchronization Method

technical field

The invention relates to the field of communication technology, in particular to a radio frequency amplification device and a method for synchronizing uplink and downlink time slots.

Background technique

A radio frequency amplification device (such as a repeater) supporting the TDD (Time Division Duplexing) system needs an uplink and downlink synchronization signal to control the transceiver switch, and two schemes are mainly used in the prior art. Solution 1: Demodulate the uplink and downlink time slots through a modem, and then control the transceiver switch. Solution 2: Use a radio frequency power detector to detect the uplink and downlink switching moments from the radio frequency signal envelope signal, and then control the transceiver switch. Option 1 is expensive to implement and consumes a lot of power; Option 2 is not suitable for 5G standard signals, which have no obvious characteristic signals at the time of uplink and downlink switching. If Option 2 is adopted, its detection accuracy is very low. Therefore, there is no low-cost uplink and downlink time slot synchronization scheme suitable for 5G standard signals in the prior art.

Contents of the invention

The purpose of the present invention is to provide a radio frequency amplification device and a method for synchronizing uplink and downlink time slots, so as to solve the problem in the prior art that there is no synchronization of uplink and downlink time slots suitable for 5G standard signals.

In order to solve the above problems, an embodiment of the present invention provides a radio frequency amplification device, including:

A radio frequency unit, the radio frequency unit is used to output high-frequency signals and control signals for uplink and downlink transceiver switches;

A power splitter, the input end of the power splitter is connected to the output end of the radio frequency unit;

An amplifying unit, the output end of the power divider is connected to the input end of the amplifying unit, and the amplifying unit includes: an uplink and downlink transceiver switch;

Wherein, the high-frequency signal output by the radio frequency unit is transmitted to the first input terminal of the uplink and downlink transceiver switch through the power divider, and the control signal output by the radio frequency unit is transmitted to the uplink and downlink through the power divider. The second input terminal of the row transceiver switch; the control signal is used to control the synchronization of the uplink and downlink time slots of the radio frequency amplification device.

Wherein, the amplifying unit also includes:

Logic circuit, the control signal output by the radio frequency unit is first transmitted to the logic circuit through the power divider, and converted by the logic circuit to obtain a digital control signal, and the digital control signal is transmitted to the uplink and downlink transceiver switch the second input terminal.

Wherein, the amplifying unit further includes: a delay adjustment circuit;

The control signal output by the radio frequency unit is first transmitted to the logic circuit through the power divider, and converted by the logic circuit to obtain a digital control signal, and the digital control signal is then passed through the time delay of the time delay adjustment circuit adjusted and transmitted to the second input end of the uplink and downlink transceiver switches;

Wherein, the time delay for the high-frequency signal to be transmitted to the first input end of the uplink and downlink transceiver switch is the same as the time delay for the control signal to be transmitted to the second input end of the uplink and downlink transceiver switch.

Wherein, the amplifying unit also includes:

Uplink signal amplifier and downlink signal amplifier;

When the control signal is used to control the uplink and downlink transceiver switch to switch to downlink signal transmission, the high frequency signal output by the radio frequency unit is output to the downlink signal amplifier through the output terminal of the uplink and downlink transceiver switch;

When the control signal is used to control the uplink and downlink transceiver switch to switch to uplink signal transmission, the uplink signal of the previous stage is transmitted to the third input terminal of the uplink and downlink transceiver switch after passing through the uplink signal amplifier.

Wherein, the radio frequency unit includes:

a radio frequency circuit, a control signal generating circuit, a first capacitor and a first inductor;

Wherein, the high-frequency signal output by the radio frequency circuit is transmitted to the output terminal of the radio frequency unit through the first capacitor; the control signal generated by the control signal generating circuit is transmitted to the output terminal of the radio frequency unit through the first inductor output.

Wherein, the amplifying unit also includes:

a second capacitor and a second inductance;

Wherein, the high-frequency signal output by the radio frequency unit is transmitted to the second capacitor after passing through the power divider, and then transmitted to the first input end of the uplink and downlink transceiver switch through the second capacitor;

The control signal output by the radio frequency unit is transmitted to the second inductor after passing through the power divider, and then transmitted to the second input end of the uplink and downlink transceiver switch through the second inductor.

An embodiment of the present invention also provides a method for synchronizing uplink and downlink time slots, which is applied to the radio frequency amplification device as described above, including:

The control signal of the uplink and downlink transceiver switch output by the radio frequency unit of the radio frequency amplifier device is transmitted to the uplink and downlink transceiver switch of the radio frequency amplifier device through a feeder line and a power divider;

Wherein, the control signal is used to control the synchronization of uplink and downlink time slots of the radio frequency amplifying device.

Wherein, the method also includes:

The delay adjustment circuit of the radio frequency amplifier device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplifier device, so that the high frequency signal output by the radio frequency unit is transmitted to the first input of the uplink and downlink transceiver switch The time delay at the end is the same as the time delay at which the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink transceiver switch.

An embodiment of the present invention also provides a radio frequency amplification device, including a memory, a processor, and a computer program stored on the memory and operable on the processor. When the processor executes the program, the above-mentioned Uplink and downlink time slot synchronization method.

An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps in the method for synchronizing uplink and downlink time slots as described above are implemented.

The technical solution of the present invention has at least the following beneficial effects:

In the radio frequency amplification device and the uplink and downlink time slot synchronization method of the embodiment of the present invention, the radio frequency unit outputs the control signal of the uplink and downlink transceiver switches to the outside, and the control signal is transmitted to the amplifying unit through the feeder line and the power divider, thereby realizing uplink and downlink Row time slot synchronization.

Description of drawings

FIG. 1 shows a schematic structural diagram of a radio frequency amplification device provided by an embodiment of the present invention;

FIG. 2 shows a schematic diagram of the frequency selection characteristics of the power divider of the radio frequency amplification device provided by the embodiment of the present invention;

3 shows a schematic diagram of the control signals of the uplink and downlink transceiver switches of the radio frequency amplification device provided by the embodiment of the present invention;

Fig. 4 shows a schematic diagram of a cost reduction solution of a distributed pico base station provided by an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

In the embodiment of the present invention, the 5G standard signal is taken as an example, but it is not limited to this signal, and the technical solution provided by the embodiment of the present invention can be applied to other signals with the same problem.

As shown in Figure 1, an embodiment of the present invention provides a radio frequency amplification device, including:

A radio frequency unit 1, the radio frequency unit 1 is used to output high-frequency signals and control signals for uplink and downlink transceiver switches;

A power divider 2, the input end of the power divider 2 is connected to the output end of the radio frequency unit 1;

An amplifying unit 3, the output end of the power divider 2 is connected to the input end of the amplifying unit 3, and the amplifying unit 3 includes: an uplink and downlink transceiver switch 31;

Wherein, the high-frequency signal output by the radio frequency unit 1 is transmitted to the first input terminal B1 of the uplink and downlink transceiver switch 31 through the power divider 2, and the control signal output by the radio frequency unit 1 is transmitted through the power divider 2 is transmitted to the second input terminal B2 of the uplink and downlink transceiver switch 31; the control signal is used to control the uplink and downlink time slot synchronization of the radio frequency amplification device.

In the embodiment of the present invention, the amplifying unit works in the time division duplex TDD mode, and its uplink and downlink transceiver switch 31 needs a control signal, which is output by the radio frequency unit 1, and is transmitted by wire (the feeder of the radio frequency unit and the passive device power division device) to the uplink and downlink transceiver switch 31.

Optionally, the power divider 2 is a power divider with frequency selectivity; for example, as shown in Figure 2, the frequency selection characteristics of the power divider are: the 0.7-2.7GHz frequency band is used to support the high frequency signals, and the frequency band below 1MHz is used to transmit control signals.

As an optional embodiment, the amplifying unit 3 further includes:

Logic circuit 32, the control signal output by the radio frequency unit 1 is first transmitted to the logic circuit 32 through the power divider, and converted by the logic circuit 32 to obtain a digital control signal, and the digital control signal is transmitted to the The second input terminal B2 of the uplink and downlink transceiver switch 31 .

In the embodiment of the present invention, since the control signal must undergo some attenuation during transmission from the radio frequency unit to the amplification unit, the control signal needs to be restored to digital control signals of “0” and “1” by the logic circuit 32 in FIG. 1 ,As shown in Figure 3. Optionally, the logic circuit 32 may be composed of two inverters.

As another optional embodiment, the amplifying unit 3 further includes: a delay adjustment circuit 33;

The control signal output by the radio frequency unit 1 is first transmitted to the logic circuit 32 through the power divider, converted by the logic circuit 32 to obtain a digital control signal, and then the digital control signal passes through the delay adjustment circuit 33 after the time delay is adjusted and transmitted to the second input terminal B2 of the uplink and downlink transceiver switch 31;

Wherein, the time delay of the high-frequency signal being transmitted to the first input terminal B1 of the uplink and downlink transceiver switch 31 is the same as the time delay of the control signal being transmitted to the second input terminal B2 of the uplink and downlink transceiver switch 31; That is, the time delay of the signal from point A to point B1 is the same as the time delay of the signal from point A to point B2.

In the embodiment of the present invention, since the uplink and downlink signals and control signals need to be aligned in the time domain, it is necessary to ensure that the time delay of the signal from point A to point B1 is consistent with the time delay of the signal from point A to point B2. For this problem, in the embodiment of the present invention, a delay adjustment circuit 33 is added after the logic circuit 32 to realize the time synchronization between the uplink and downlink signals and the control signals. The specific structure of the time delay adjustment circuit 33 can be realized by adopting mature technical solutions in the industry, and is not specifically limited here. In order to minimize the random interference introduced by the signal transmission process, the delay value inside the delay adjustment circuit may be an average value within a period of time.

As yet another optional embodiment, the amplifying unit 3 further includes:

Uplink signal amplifier 34 and downlink signal amplifier 35;

In the case where the control signal is used to control the uplink and downlink transceiver switches to switch to downlink signal transmission (for example, control signal=1), the high frequency signal output by the radio frequency unit 1 passes through the output of the uplink and downlink transceiver switches output to the downlink signal amplifier 35;

In the case where the control signal is used to control the uplink and downlink transceiver switch to switch to uplink signal transmission (for example, control signal=0), the previous stage uplink signal is transmitted to the uplink and downlink transceiver after passing through the uplink signal amplifier 34 The third input terminal of the switch.

In short, when the control signal=1, the uplink and downlink transceiver switch switches to a downlink signal, and the high frequency signal is sent to the subsequent stage circuit through the downlink signal amplifier 35; when the control signal=0, the uplink and downlink transceiver switch switches to an uplink signal, The previous uplink signal is sent to the uplink and downlink transceiver switches after passing through the uplink signal amplifier 34 .

Optionally, in the above embodiments of the present invention, the radio frequency unit 1 includes:

a radio frequency circuit 11, a control signal generating circuit 12, a first capacitor C1 and a first inductor L1;

Wherein, the high-frequency signal output by the radio frequency circuit 11 is transmitted to the output terminal of the radio frequency unit 1 through the first capacitor C1; the control signal generated by the control signal generating circuit 12 is transmitted to the output terminal of the radio frequency unit 1 through the first inductor L1. The output end of the radio frequency unit 1.

In the embodiment of the present invention, the control signal is a low frequency signal. The high-frequency signal (such as GHz) output by the radio frequency circuit is transmitted to the output terminal through the first capacitor C1, and the control signal is a low-frequency signal (such as KHz), which is transmitted to the output terminal through the first inductor L1.

Optionally, in the above embodiments of the present invention, the amplifying unit 3 further includes:

a second capacitor C2 and a second inductor L2;

Wherein, the high-frequency signal output by the radio frequency unit 1 is transmitted to the second capacitor C2 after passing through the power divider 2, and then transmitted to the first input terminal of the uplink and downlink transceiver switch 31 through the second capacitor C2 B1;

The control signal output by the radio frequency unit 1 is transmitted to the second inductor L2 after passing through the power divider 2 , and then transmitted to the second input terminal B2 of the uplink and downlink transceiver switch 31 through the second inductor L2 .

In the embodiment of the present invention, the output signal of the radio frequency unit 1 is transmitted to the amplification unit 3 after passing through the power divider 2, wherein the high-frequency signal is transmitted to the uplink and downlink transceiver switch 31 through the second capacitor C2, and the low-frequency signal is transmitted to the uplink and downlink through the second inductor L2 Transceiver switch 31.

Optionally, the radio frequency amplification device provided by the embodiment of the present invention is applicable to but not limited to distributed pico base stations. As shown in FIG. 4 , the distributed pico base stations include: a baseband unit, a switching unit, and a radio frequency unit. In order to reduce the total cost of the distributed pico base station network, the radio frequency unit is connected to multiple amplification units through a power divider to expand its coverage.

In summary, in the embodiment of the present invention, the radio frequency unit outputs the control signal of the uplink and downlink transceiver switches to the outside, and the control signal is transmitted to the amplifying unit through the feeder and the power divider, so as to realize the synchronization of the uplink and downlink time slots; further increase the delay adjustment The circuit realizes time synchronization of uplink and downlink signals and control signals.

An embodiment of the present invention also provides a method for synchronizing uplink and downlink time slots, which is applied to the radio frequency amplification device as described above, including:

The control signal of the uplink and downlink transceiver switch output by the radio frequency unit of the radio frequency amplifier device is transmitted to the uplink and downlink transceiver switch of the radio frequency amplifier device through a feeder line and a power divider;

Wherein, the control signal is used to control the synchronization of uplink and downlink time slots of the radio frequency amplifying device.

Optionally, the method also includes:

The delay adjustment circuit of the radio frequency amplifier device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplifier device, so that the high frequency signal output by the radio frequency unit is transmitted to the first input of the uplink and downlink transceiver switch The time delay at the end is the same as the time delay at which the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink transceiver switch.

In the embodiment of the present invention, the radio frequency unit outputs the control signal of the uplink and downlink transceiver switches to the outside, and the control signal is transmitted to the amplifying unit through the feeder and the power divider, thereby realizing synchronization of the uplink and downlink time slots; further adding a delay adjustment circuit to realize uplink and downlink The row signal is time-synchronized with the control signal.

An embodiment of the present invention also provides a base station, including a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the program, the above-mentioned up and down Each process in the embodiment of the time slot synchronization method can achieve the same technical effect, and will not be repeated here to avoid repetition.

The embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, each process in the above-mentioned embodiment of the uplink and downlink time slot synchronization method is realized, and the same To avoid repetition, the technical effects will not be repeated here. Wherein, the computer-readable storage medium is, for example, a read-only memory (Read-Only Memory, ROM for short), a random access memory (Random Access Memory, RAM for short), a magnetic disk or an optical disk, and the like.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems or computer program products. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a Means for realizing the functions specified in one or more procedures and/or one or more blocks of the flowchart.

These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable storage medium produce a paper product comprising instruction means, The instruction means implements the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device Steps are provided for implementing the functions specified in the flow chart or flow charts and/or block diagram block or blocks.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, these improvements and modifications It should also be regarded as the protection scope of the present invention.

Claims (8)

1. A radio frequency amplifier, characterized in that, comprising: A radio frequency unit, the radio frequency unit is used to output high-frequency signals and control signals for uplink and downlink transceiver switches; A power splitter, the input end of the power splitter is connected to the output end of the radio frequency unit; An amplifying unit, the output end of the power divider is connected to the input end of the amplifying unit, and the amplifying unit includes: an uplink and downlink transceiver switch; Wherein, the high-frequency signal output by the radio frequency unit is transmitted to the first input terminal of the uplink and downlink transceiver switch through the power divider, and the control signal output by the radio frequency unit is transmitted to the uplink and downlink through the power divider. The second input terminal of the row transceiver switch; the control signal is used to control the synchronization of the uplink and downlink time slots of the radio frequency amplification device; The amplifying unit also includes: Logic circuit, the control signal output by the radio frequency unit is first transmitted to the logic circuit through the power divider, and converted by the logic circuit to obtain a digital control signal, and the digital control signal is transmitted to the uplink and downlink transceiver switch the second input terminal; The amplifying unit also includes: a delay adjustment circuit; The control signal output by the radio frequency unit is first transmitted to the logic circuit through the power divider, and converted by the logic circuit to obtain a digital control signal, and the digital control signal is then passed through the time delay of the time delay adjustment circuit adjusted and transmitted to the second input end of the uplink and downlink transceiver switches; Wherein, the time delay for the high-frequency signal to be transmitted to the first input end of the uplink and downlink transceiver switch is the same as the time delay for the control signal to be transmitted to the second input end of the uplink and downlink transceiver switch. 2. The radio frequency amplifying device according to claim 1, wherein the amplifying unit further comprises: Uplink signal amplifier and downlink signal amplifier; When the control signal is used to control the uplink and downlink transceiver switch to switch to downlink signal transmission, the high frequency signal output by the radio frequency unit is output to the downlink signal amplifier through the output terminal of the uplink and downlink transceiver switch; When the control signal is used to control the uplink and downlink transceiver switch to switch to uplink signal transmission, the uplink signal of the previous stage is transmitted to the third input terminal of the uplink and downlink transceiver switch after passing through the uplink signal amplifier. 3. The radio frequency amplifying device according to claim 1, wherein the radio frequency unit comprises: a radio frequency circuit, a control signal generating circuit, a first capacitor and a first inductor; Wherein, the high-frequency signal output by the radio frequency circuit is transmitted to the output terminal of the radio frequency unit through the first capacitor; the control signal generated by the control signal generating circuit is transmitted to the output terminal of the radio frequency unit through the first inductor output. 4. The radio frequency amplifying device according to claim 1, wherein the amplifying unit further comprises: a second capacitor and a second inductance; Wherein, the high-frequency signal output by the radio frequency unit is transmitted to the second capacitor after passing through the power divider, and then transmitted to the first input end of the uplink and downlink transceiver switch through the second capacitor; The control signal output by the radio frequency unit is transmitted to the second inductor after passing through the power divider, and then transmitted to the second input end of the uplink and downlink transceiver switch through the second inductor. 5. A method for synchronizing uplink and downlink time slots, applied to the radio frequency amplification device according to any one of claims 1-4, characterized in that, comprising: The control signal of the uplink and downlink transceiver switch output by the radio frequency unit of the radio frequency amplifier device is transmitted to the uplink and downlink transceiver switch of the radio frequency amplifier device through a feeder line and a power divider; Wherein, the control signal is used to control the synchronization of uplink and downlink time slots of the radio frequency amplifying device. 6. The method according to claim 5, further comprising: The delay adjustment circuit of the radio frequency amplifier device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplifier device, so that the high frequency signal output by the radio frequency unit is transmitted to the first input of the uplink and downlink transceiver switch The time delay at the end is the same as the time delay at which the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink transceiver switch. 7. A radio frequency amplifying device, comprising a memory, a processor and a computer program stored on the memory and operable on the processor; it is characterized in that, when the processor executes the program, it realizes the The uplink and downlink time slot synchronization method described in 5 or 6. 8. A computer-readable storage medium, on which a computer program is stored, wherein when the program is executed by a processor, the steps in the method for synchronizing uplink and downlink time slots according to claim 5 or 6 are implemented.

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