CN112004262B - Radio frequency amplifying device and uplink and downlink time slot synchronization method - Google Patents
Radio frequency amplifying device and uplink and downlink time slot synchronization method Download PDFInfo
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- CN112004262B CN112004262B CN201910446607.5A CN201910446607A CN112004262B CN 112004262 B CN112004262 B CN 112004262B CN 201910446607 A CN201910446607 A CN 201910446607A CN 112004262 B CN112004262 B CN 112004262B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention provides a radio frequency amplifying device and an uplink and downlink time slot synchronizing method, wherein the device comprises the following steps: a radio frequency unit is provided which, the radio frequency unit is used for outputting a high-frequency signal and a control signal of the uplink and downlink receiving and transmitting switch; the power divider is used for dividing the power into a plurality of power dividers, the input end of the power divider is connected with the output end of the radio frequency unit; an amplifying unit, which is used for amplifying the signals, the output end of the power divider is connected with the input end of the amplifying unit, the amplifying unit includes: an uplink/downlink receiving/transmitting switch; the high-frequency signal output by the radio frequency unit is transmitted to the first input end of the uplink and downlink receiving and transmitting switch through the power divider, and the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink receiving and transmitting switch through the power divider; the control signal is used for controlling the uplink and downlink time slot synchronization of the radio frequency amplifying device. In the embodiment of the invention, the control signals of the uplink and downlink receiving and transmitting switches are output to the outside by the radio frequency unit, and the control signals are transmitted to the amplifying unit through the feeder line and the power divider, so that uplink and downlink time slot synchronization is realized.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a radio frequency amplifying device and an uplink and downlink time slot synchronization method.
Background
The radio frequency amplifying device (such as a repeater) supporting the TDD (Time Division Duplexing, time division duplex) system needs an uplink and downlink synchronizing signal to control the transceiver switch, and two schemes are mainly adopted in the prior art. Scheme 1: the uplink time slot and the downlink time slot are demodulated by a modem, so as to control the receiving and transmitting switch. Scheme 2: and detecting uplink and downlink switching moments from the envelope signal of the radio frequency signal by adopting a radio frequency power detector, so as to control a receiving and transmitting switch. The scheme 1 has higher implementation cost and higher power consumption; scheme 2 is not suitable for 5G system signals, the 5G system signals have no obvious characteristic signals at the time of uplink and downlink switching, and if scheme 2 is adopted, the detection accuracy is very low. Therefore, there is no low-cost uplink and downlink time slot synchronization scheme suitable for 5G system signals in the prior art.
Disclosure of Invention
The invention aims to provide a radio frequency amplifying device and an uplink and downlink time slot synchronization method, which are used for solving the problem that uplink and downlink time slot synchronization applicable to 5G standard signals does not exist in the prior art.
In order to solve the above-mentioned problems, an embodiment of the present invention provides a radio frequency amplifying device, including:
the radio frequency unit is used for outputting high-frequency signals and control signals of the uplink and downlink receiving and transmitting switches;
the input end of the power divider is connected with the output end of the radio frequency unit;
the output end of the power divider is connected with the input end of the amplifying unit, and the amplifying unit comprises: an uplink/downlink receiving/transmitting switch;
the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink receiving and transmitting switch through the power divider; the control signal is used for controlling the uplink and downlink time slot synchronization of the radio frequency amplifying device.
Wherein the amplifying unit further includes:
and the control signal output by the radio frequency unit is firstly transmitted to the logic circuit through the power divider, the digital control signal is obtained through conversion of the logic circuit, and the digital control signal is transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
Wherein the amplifying unit further includes: a delay adjustment circuit;
the control signal output by the radio frequency unit is firstly transmitted to the logic circuit through the power divider, the digital control signal is obtained through conversion of the logic circuit, and the digital control signal is transmitted to the second input end of the uplink and downlink receiving and transmitting switch after the delay adjustment of the delay adjustment circuit;
the time delay of the high-frequency signal transmitted to the first input end of the uplink and downlink receiving and transmitting switch is the same as the time delay of the control signal transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
Wherein the amplifying unit further includes:
an upstream signal amplifier and a downstream signal amplifier;
under the condition that the control signal is used for controlling the uplink and downlink receiving and transmitting switch to downlink signal transmission, the high-frequency signal output by the radio frequency unit is output to the downlink signal amplifier through the output end of the uplink and downlink receiving and transmitting switch;
and under the condition that the control signal is used for controlling the uplink and downlink receiving and transmitting switch to uplink signal transmission, the previous stage uplink signal is transmitted to the third input end of the uplink and downlink receiving and transmitting switch after passing through the uplink signal amplifier.
Wherein, the radio frequency unit includes:
the radio frequency circuit, the control signal generating circuit, the first capacitor and the first inductor;
the high-frequency signal output by the radio frequency circuit is transmitted to the output end of the radio frequency unit through the first capacitor; and the control signal generated by the control signal generating circuit is transmitted to the output end of the radio frequency unit through the first inductor.
Wherein the amplifying unit further includes:
a second capacitor and a second inductor;
the high-frequency signal output by the radio frequency unit is transmitted to the second capacitor after passing through the power divider, and is transmitted to the first input end of the uplink and downlink receiving and transmitting switch through the second capacitor;
and a control signal output by the radio frequency unit is transmitted to the second inductor after passing through the power divider, and is transmitted to the second input end of the uplink and downlink receiving and transmitting switch through the second inductor.
The embodiment of the invention also provides an uplink and downlink time slot synchronization method which is applied to the radio frequency amplifying device and comprises the following steps:
the control signals of the uplink and downlink receiving and transmitting switches output by the radio frequency unit of the radio frequency amplifying device are transmitted to the uplink and downlink receiving and transmitting switches of the radio frequency amplifying device through a feeder line and a power divider;
the control signal is used for controlling uplink and downlink time slot synchronization of the radio frequency amplifying device.
Wherein the method further comprises:
the delay adjustment circuit of the radio frequency amplification device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplification device, so that the delay of the high-frequency signal output by the radio frequency unit transmitted to the first input end of the uplink and downlink receiving and transmitting switch is the same as the delay of the control signal output by the radio frequency unit transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
The embodiment of the invention also provides a radio frequency amplifying device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes the uplink and downlink time slot synchronization method when executing the program.
The embodiment of the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the uplink and downlink slot synchronization method described above.
The technical scheme of the invention has at least the following beneficial effects:
in the radio frequency amplifying device and the uplink and downlink time slot synchronization method of the embodiment of the invention, the control signal of the uplink and downlink receiving and transmitting switch is output to the outside by the radio frequency unit, and the control signal is transmitted to the amplifying unit through the feeder line and the power divider, thereby realizing uplink and downlink time slot synchronization.
Drawings
Fig. 1 shows a schematic structural diagram of a radio frequency amplifying device according to an embodiment of the present invention;
fig. 2 shows a schematic diagram of frequency selection characteristics of a power divider of a radio frequency amplifying device according to an embodiment of the present invention;
fig. 3 is a schematic diagram showing control signals of an uplink and downlink transceiving switch of a radio frequency amplifying device according to an embodiment of the present invention;
fig. 4 shows a schematic diagram of a cost-reduction scheme of a distributed pico-cell according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
In the embodiment of the invention, a 5G system signal is taken as an example, but the invention is not limited to the signal, and the technical scheme provided by the embodiment of the invention can be applied to other signals with the same problems.
As shown in fig. 1, an embodiment of the present invention provides a radio frequency amplifying device, including:
the radio frequency unit 1 is used for outputting a high-frequency signal and a control signal of an uplink and downlink receiving and transmitting switch;
the input end of the power divider 2 is connected with the output end of the radio frequency unit 1;
an amplifying unit 3, an output end of the power divider 2 is connected with an input end of the amplifying unit 3, and the amplifying unit 3 includes: an up-down transmitting/receiving switch 31;
the high-frequency signal output by the radio frequency unit 1 is transmitted to the first input end B1 of the uplink and downlink transceiving switch 31 through the power divider 2, and the control signal output by the radio frequency unit 1 is transmitted to the second input end B2 of the uplink and downlink transceiving switch 31 through the power divider 2; the control signal is used for controlling the uplink and downlink time slot synchronization of the radio frequency amplifying device.
In the embodiment of the present invention, the amplifying unit works in a time division duplex TDD mode, and the uplink and downlink transmit-receive switch 31 needs a control signal, and the control signal is output by the radio frequency unit 1 and is transmitted to the uplink and downlink transmit-receive switch 31 through wired transmission (feeder line of the radio frequency unit and passive device power divider).
Optionally, the power divider 2 is a power divider with frequency selectivity; for example, as shown in fig. 2, the frequency selective characteristics of the power divider are: the frequency band of 0.7-2.7GHz is used for supporting the high-frequency signals output by the radio frequency circuit, and the frequency band below 1MHz is used for transmitting control signals.
As an alternative embodiment, the amplifying unit 3 further comprises:
the control signal output by the radio frequency unit 1 is transmitted to the logic circuit 32 through the power divider, and is converted by the logic circuit 32 to obtain a digital control signal, and the digital control signal is transmitted to the second input terminal B2 of the uplink/downlink transceiver switch 31.
In the embodiment of the present invention, since the control signal must be attenuated during the transmission from the rf unit to the amplifying unit, the control signal needs to be recovered to the digital control signals of "0" and "1" through the logic circuit 32 in fig. 1, as shown in fig. 3. Alternatively, the logic circuit 32 may be composed of two inverters.
As another alternative embodiment, the amplifying unit 3 further includes: a delay adjustment circuit 33;
the control signal output by the radio frequency unit 1 is firstly transmitted to the logic circuit 32 through the power divider, the digital control signal is obtained through the conversion of the logic circuit 32, and the digital control signal is transmitted to the second input end B2 of the uplink and downlink transceiving switch 31 after the delay adjustment of the delay adjustment circuit 33;
the time delay of the high-frequency signal transmitted to the first input terminal B1 of the uplink/downlink transceiving switch 31 is the same as the time delay of the control signal transmitted to the second input terminal B2 of the uplink/downlink transceiving switch 31; i.e. the time delay of the signal from point a to point B1 is the same as the time delay of the signal from point a to point B2.
In the embodiment of the present invention, since the uplink and downlink signals and the control signal need to be aligned in the time domain, the time delay from the point a to the point B1 and the time delay from the point a to the point B2 of the signal are ensured to be consistent, and in order to solve the problem, a time delay adjusting circuit 33 is added behind the logic circuit 32 in the embodiment of the present invention, so as to realize time synchronization of the uplink and downlink signals and the control signal. The specific structure of the delay adjustment circuit 33 can be implemented by using a well-known technical scheme, which is not limited herein. In order to minimize random interference introduced during signal transmission, the delay value within the delay adjustment circuit may be an average value over a period of time.
As a further alternative embodiment, the amplifying unit 3 further comprises:
an upstream signal amplifier 34 and a downstream signal amplifier 35;
in the case where the control signal is used to control the uplink/downlink transceiving switch to downlink signal transmission (for example, control signal=1), the high-frequency signal output by the radio frequency unit 1 is output to the downlink signal amplifier 35 through the output terminal of the uplink/downlink transceiving switch;
when the control signal is used to control the switch to uplink signal transmission (e.g., control signal=0), the upstream signal of the previous stage is transmitted to the third input terminal of the uplink/downlink transceiver switch after passing through the uplink signal amplifier 34.
In short, when the control signal=1, the up-down transceiving switch is switched to the down-signal, and the high-frequency signal is sent to the post-stage circuit through the down-signal amplifier 35; when the control signal=0, the uplink/downlink transmission/reception switch is switched to the uplink signal, and the uplink signal of the preceding stage is sent to the uplink/downlink transmission/reception switch through the uplink signal amplifier 34.
Optionally, in the foregoing embodiment of the present invention, the radio frequency unit 1 includes:
a radio frequency circuit 11, a control signal generating circuit 12, a first capacitor C1, and a first inductor L1;
the high-frequency signal output by the radio frequency circuit 11 is transmitted to the output end of the radio frequency unit 1 through the first capacitor C1; the control signal generated by the control signal generating circuit 12 is transmitted to the output terminal of the radio frequency unit 1 through the first inductor L1.
In the embodiment of the invention, the control signal is a low-frequency signal. The high-frequency signal (for example, GHz) output by the radio-frequency circuit is transmitted to the output end through the first capacitor C1, the control signal is a low-frequency signal (for example, KHz), and the control signal is transmitted to the output end through the first inductor L1.
Optionally, in the above embodiment of the present invention, the amplifying unit 3 further includes:
a second capacitor C2 and a second inductance L2;
the high-frequency signal output by the radio frequency unit 1 is transmitted to the second capacitor C2 after passing through the power divider 2, and is transmitted to the first input terminal B1 of the uplink/downlink transceiver switch 31 after passing through the second capacitor C2;
the control signal output by the radio frequency unit 1 is transmitted to the second inductor L2 after passing through the power divider 2, and is transmitted to the second input terminal B2 of the uplink/downlink transceiving switch 31 after passing through the second inductor L2.
In the embodiment of the present invention, the output signal of the radio frequency unit 1 is transmitted to the amplifying unit 3 after passing through the power divider 2, wherein the high-frequency signal is transmitted to the up-down transceiving switch 31 through the second capacitor C2, and the low-frequency signal is transmitted to the up-down transceiving switch 31 through the second inductor L2.
Optionally, the radio frequency amplifying device provided by the embodiment of the present invention is applicable to, but not limited to, a distributed pico-base station, as shown in fig. 4, where the distributed pico-base station includes: baseband unit, switching unit and radio frequency unit. In order to reduce the total cost of the distributed pico-cell network, the radio frequency unit is externally connected with a plurality of amplifying units through the power divider so as to enlarge the coverage range of the radio frequency unit.
In summary, in the embodiment of the invention, the radio frequency unit outputs the control signal of the uplink and downlink transceiving switch to the outside, and the control signal is transmitted to the amplifying unit through the feeder line and the power divider, so that uplink and downlink time slot synchronization is realized; the time delay adjusting circuit is further added to realize time synchronization of the uplink and downlink signals and the control signals.
The embodiment of the invention also provides an uplink and downlink time slot synchronization method which is applied to the radio frequency amplifying device and comprises the following steps:
the control signals of the uplink and downlink receiving and transmitting switches output by the radio frequency unit of the radio frequency amplifying device are transmitted to the uplink and downlink receiving and transmitting switches of the radio frequency amplifying device through a feeder line and a power divider;
the control signal is used for controlling uplink and downlink time slot synchronization of the radio frequency amplifying device.
Optionally, the method further comprises:
the delay adjustment circuit of the radio frequency amplification device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplification device, so that the delay of the high-frequency signal output by the radio frequency unit transmitted to the first input end of the uplink and downlink receiving and transmitting switch is the same as the delay of the control signal output by the radio frequency unit transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
In the embodiment of the invention, the radio frequency unit outputs the control signals of the uplink and downlink receiving and transmitting switches to the amplifying unit through the feeder line and the power divider, thereby realizing uplink and downlink time slot synchronization; the time delay adjusting circuit is further added to realize time synchronization of the uplink and downlink signals and the control signals.
The embodiment of the invention also provides a base station, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes each process in the embodiment of the uplink and downlink time slot synchronization method as described above when executing the program, and can achieve the same technical effect, and in order to avoid repetition, the description is omitted.
The embodiment of the present invention also provides a computer readable storage medium, on which a computer program is stored, where the program when executed by a processor implements each process in the embodiment of the uplink and downlink time slot synchronization method as described above, and the same technical effects can be achieved, and for avoiding repetition, a detailed description is omitted herein. Wherein the computer readable storage medium is selected from Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, magnetic disk storage and optical storage, etc.) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block or blocks.
These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (8)
1. A radio frequency amplifying device, comprising:
the radio frequency unit is used for outputting high-frequency signals and control signals of the uplink and downlink receiving and transmitting switches;
the input end of the power divider is connected with the output end of the radio frequency unit;
the output end of the power divider is connected with the input end of the amplifying unit, and the amplifying unit comprises: an uplink/downlink receiving/transmitting switch;
the control signal output by the radio frequency unit is transmitted to the second input end of the uplink and downlink receiving and transmitting switch through the power divider; the control signal is used for controlling the uplink and downlink time slot synchronization of the radio frequency amplifying device;
the amplifying unit further includes:
the control signal output by the radio frequency unit is firstly transmitted to the logic circuit through the power divider, the digital control signal is obtained through conversion of the logic circuit, and the digital control signal is transmitted to the second input end of the uplink and downlink receiving and transmitting switch;
the amplifying unit further includes: a delay adjustment circuit;
the control signal output by the radio frequency unit is firstly transmitted to the logic circuit through the power divider, the digital control signal is obtained through conversion of the logic circuit, and the digital control signal is transmitted to the second input end of the uplink and downlink receiving and transmitting switch after the delay adjustment of the delay adjustment circuit;
the time delay of the high-frequency signal transmitted to the first input end of the uplink and downlink receiving and transmitting switch is the same as the time delay of the control signal transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
2. The radio frequency amplifying device according to claim 1, wherein the amplifying unit further comprises:
an upstream signal amplifier and a downstream signal amplifier;
under the condition that the control signal is used for controlling the uplink and downlink receiving and transmitting switch to downlink signal transmission, the high-frequency signal output by the radio frequency unit is output to the downlink signal amplifier through the output end of the uplink and downlink receiving and transmitting switch;
and under the condition that the control signal is used for controlling the uplink and downlink receiving and transmitting switch to uplink signal transmission, the previous stage uplink signal is transmitted to the third input end of the uplink and downlink receiving and transmitting switch after passing through the uplink signal amplifier.
3. The radio frequency amplification device of claim 1, wherein the radio frequency unit comprises:
the radio frequency circuit, the control signal generating circuit, the first capacitor and the first inductor;
the high-frequency signal output by the radio frequency circuit is transmitted to the output end of the radio frequency unit through the first capacitor; and the control signal generated by the control signal generating circuit is transmitted to the output end of the radio frequency unit through the first inductor.
4. The radio frequency amplifying device according to claim 1, wherein the amplifying unit further comprises:
a second capacitor and a second inductor;
the high-frequency signal output by the radio frequency unit is transmitted to the second capacitor after passing through the power divider, and is transmitted to the first input end of the uplink and downlink receiving and transmitting switch through the second capacitor;
and a control signal output by the radio frequency unit is transmitted to the second inductor after passing through the power divider, and is transmitted to the second input end of the uplink and downlink receiving and transmitting switch through the second inductor.
5. A method for synchronizing uplink and downlink time slots, applied to a radio frequency amplifying device as in any one of claims 1-4, comprising:
the control signals of the uplink and downlink receiving and transmitting switches output by the radio frequency unit of the radio frequency amplifying device are transmitted to the uplink and downlink receiving and transmitting switches of the radio frequency amplifying device through a feeder line and a power divider;
the control signal is used for controlling uplink and downlink time slot synchronization of the radio frequency amplifying device.
6. The method of claim 5, wherein the method further comprises:
the delay adjustment circuit of the radio frequency amplification device performs delay adjustment on the control signal output by the radio frequency unit of the radio frequency amplification device, so that the delay of the high-frequency signal output by the radio frequency unit transmitted to the first input end of the uplink and downlink receiving and transmitting switch is the same as the delay of the control signal output by the radio frequency unit transmitted to the second input end of the uplink and downlink receiving and transmitting switch.
7. A radio frequency amplifying device comprising a memory, a processor and a computer program stored on the memory and executable on the processor; the method for synchronizing uplink and downlink time slots according to claim 5 or 6 is realized when the processor executes the program.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the uplink and downlink time slot synchronization method according to claim 5 or 6.
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| CN1707987A (en) * | 2004-06-10 | 2005-12-14 | 中兴通讯股份有限公司 | Bidirectional amplifier in time division duplex communication system and amplifying method thereof |
| CN1913392A (en) * | 2005-08-11 | 2007-02-14 | 大唐移动通信设备有限公司 | Relay amplification device with transmit-receive function and transmit-receive control method |
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| CN101056463A (en) * | 2007-05-31 | 2007-10-17 | 武汉虹信通信技术有限责任公司 | A method for uplink and downlink time division switching management in the TD-SCDMA RF receiving and transmission module |
| GB201308442D0 (en) * | 2013-05-10 | 2013-06-19 | Bae Systems Plc | Duplexer |
| WO2015124090A1 (en) * | 2014-02-19 | 2015-08-27 | 华为终端有限公司 | Radio-frequency circuit and terminal device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1707987A (en) * | 2004-06-10 | 2005-12-14 | 中兴通讯股份有限公司 | Bidirectional amplifier in time division duplex communication system and amplifying method thereof |
| CN1913392A (en) * | 2005-08-11 | 2007-02-14 | 大唐移动通信设备有限公司 | Relay amplification device with transmit-receive function and transmit-receive control method |
| CN101018086A (en) * | 2006-02-10 | 2007-08-15 | 大唐移动通信设备有限公司 | Synchronization receiving and transmitting control method and system of relay amplifier in the TD-SCDMA system |
| CN101056463A (en) * | 2007-05-31 | 2007-10-17 | 武汉虹信通信技术有限责任公司 | A method for uplink and downlink time division switching management in the TD-SCDMA RF receiving and transmission module |
| GB201308442D0 (en) * | 2013-05-10 | 2013-06-19 | Bae Systems Plc | Duplexer |
| WO2015124090A1 (en) * | 2014-02-19 | 2015-08-27 | 华为终端有限公司 | Radio-frequency circuit and terminal device |
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| CN112004262A (en) | 2020-11-27 |
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