CN112003613B - Dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator - Google Patents
Dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator Download PDFInfo
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- CN112003613B CN112003613B CN202010909113.9A CN202010909113A CN112003613B CN 112003613 B CN112003613 B CN 112003613B CN 202010909113 A CN202010909113 A CN 202010909113A CN 112003613 B CN112003613 B CN 112003613B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention discloses a dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator, which comprises two single-core voltage-controlled oscillators with the same structure; the method is characterized in that: the two single-core transconductance linearization voltage-controlled oscillators are connected in parallel; each single-core voltage-controlled oscillator comprises two differential resonance tubes, a plurality of switch capacitance circuits capable of being adjusted in a numerical control mode and a continuous tuning circuit, and the first single-core voltage-controlled oscillator comprises a first differential resonance tube and a second differential resonance tube; the second single-core voltage-controlled oscillator comprises a third differential resonance tube and a fourth differential resonance tube; the grid electrode of any differential resonance tube of the single-core voltage-controlled oscillator is connected to the drain electrode of the other differential resonance tube through a capacitor, and meanwhile, the grid electrodes of the second differential resonance tube and the fourth differential resonance tube are connected to the grid electrodes of the first differential resonance tube and the third differential resonance tube through a first differential inductor and are grounded in a common mode through the first differential inductor; the invention can be applied to a high-performance phase-locked loop system.
Description
Technical Field
The invention relates to a voltage-controlled oscillator, in particular to a dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator.
Background
The phase-locked loop can be used for providing local oscillation signals for a radio frequency receiving and transmitting system or providing clock signals for a data converter and a digital circuit, and the signal quality of the local oscillation signals or the clock signals has direct influence on key indexes in the radio frequency system and the high-speed high-precision data converter. When the phase-locked loop is operated in a narrow loop bandwidth mode, the far-end phase noise characteristic of the LC-type voltage-controlled oscillator directly determines the closed loop noise characteristic. With the rapid development of information technology, higher performance requirements are put forward on phase-locked loops, and in particular, higher phase noise performance requirements are put forward on voltage-controlled oscillators in phase-locked loops.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator.
The technical scheme of the invention is as follows: a dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator comprises two single-core voltage-controlled oscillators with the same structure; the method is characterized in that: the two single-core transconductance linearization voltage-controlled oscillators are connected in parallel;
each single-core voltage-controlled oscillator comprises two differential resonance tubes, a plurality of switch capacitance circuits capable of being adjusted in a numerical control mode and a continuous tuning circuit, and the first single-core voltage-controlled oscillator comprises a first differential resonance tube and a second differential resonance tube; the second single-core voltage-controlled oscillator comprises a third differential resonance tube and a fourth differential resonance tube;
the grid electrode of any differential resonance tube of the single-core voltage-controlled oscillator is connected to the drain electrode of the other differential resonance tube through a capacitor, and meanwhile, the grid electrodes of the second differential resonance tube and the fourth differential resonance tube are connected to the grid electrodes of the first differential resonance tube and the third differential resonance tube through a first differential inductor and are grounded in a common mode through the first differential inductor; the drain electrode of the fourth differential resonance tube and the drain electrode of the second differential resonance tube are connected with the drain electrode of the first differential resonance tube and the drain electrode of the third differential resonance tube through a second differential inductor;
the two ends of the first differential inductor are connected with a plurality of third switch capacitance circuits and a third continuous tuning circuit which can be adjusted in a numerical control mode in parallel.
According to the preferred scheme of the dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator, a plurality of first switch capacitance circuits and first continuous tuning circuits which can be adjusted in a numerical control mode are connected in parallel between the grid electrodes of the first differential resonance tube and the second differential resonance tube; and a plurality of second switch capacitance circuits and second continuous tuning circuits which can be adjusted in a numerical control way are connected in parallel between the grid electrodes of the third differential resonance tube and the fourth differential resonance tube.
The invention connects the VCO resonant cavities of the two single-core voltage-controlled oscillators with the same structure in parallel, thereby realizing the optimization of the overall phase noise of the oscillator. In the parallel connection process, a common inductance design thought is adopted, and the whole circuit architecture only needs two differential inductances, namely, when the grid electrodes of the resonant tubes are connected in parallel, one differential inductance is shared; when the drain electrodes of the resonant tubes are connected in parallel, the other differential inductor is shared, so that the layout area is effectively reduced. The PMOS resonance tube transconductance of the single-core voltage-controlled oscillator is linearized, and the near-end phase noise of the device is optimized.
According to the preferred scheme of the dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator, the first MOS tube controls the on and off of the first differential resonance tube and the second differential resonance tube, and the second MOS tube controls the on and off of the third differential resonance tube and the fourth differential resonance tube.
According to the preferred scheme of the dual-core parallel transconductance linearization low-phase noise-controlled oscillator, the first MOS tube and the second MOS tube are PMOS tubes; the grid electrodes of the first MOS tube and the second MOS tube are connected, and the interconnection node is used for simultaneously controlling the switch of the two single-core voltage-controlled oscillators.
The dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator has the beneficial effects that: the invention realizes the optimization of the near-end phase noise of the device; the dual-core parallel connection mode provided by the invention realizes the optimization of the overall phase noise of the VCO; the invention provides a common inductance connection mode, which effectively reduces the occupied chip area in the back-end layout; the dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator provided by the invention has very excellent phase noise performance and can be applied to a high-performance phase-locked loop system.
Drawings
Fig. 1 is a schematic block diagram of a dual-core parallel transconductance linearization low-phase noise-controlled oscillator according to the present invention.
Fig. 2 is a diagram of a switched capacitor implementation.
Fig. 3 is a diagram of a continuous tuning circuit implementation.
Fig. 4 is a diagram of the effect of phase noise simulation of a dual-core parallel transconductance linearized low-phase noise controlled oscillator at an oscillation frequency of 3 GHz.
Detailed Description
Referring to fig. 1 to 3, a dual-core parallel transconductance linearization low-phase noise voltage controlled oscillator includes two single-core voltage controlled oscillators with identical structures; the two single-core transconductance linearization voltage-controlled oscillators are connected in parallel;
each single-core voltage-controlled oscillator comprises two differential resonance tubes, a plurality of switch capacitance circuits capable of being adjusted in a numerical control mode and a continuous tuning circuit, and the first single-core voltage-controlled oscillator comprises a first differential resonance tube and a second differential resonance tube; the second single-core voltage-controlled oscillator comprises a third differential resonance tube and a fourth differential resonance tube;
the grid electrode of any differential resonance tube of the single-core voltage-controlled oscillator is connected to the drain electrode of the other differential resonance tube through a capacitor, and meanwhile, the grid electrodes of the second differential resonance tube PM4 and the fourth differential resonance tube PM6 are connected to the grid electrodes of the first differential resonance tube PM3 and the third differential resonance tube PM5 through a first differential inductance L1 and are grounded in a common mode through the first differential inductance L1; the common inductance of the resonance ends is realized. The drain electrode of the fourth differential resonance tube PM6 and the drain electrode of the second differential resonance tube PM4 are connected with the drain electrode of the first differential resonance tube PM3 and the drain electrode of the third differential resonance tube PM5 through a second differential inductor L2; the common inductance of the output ends is realized. The center tap of the second differential inductor L2 is grounded.
The two ends of the first differential inductor L1 are connected in parallel with a plurality of third switching capacitor circuits and third continuous tuning circuits which can be adjusted in a numerical control mode.
A plurality of first switch capacitance circuits and first continuous tuning circuits which can be adjusted in a numerical control way are connected in parallel between the grid electrodes of the first differential resonance tube and the second differential resonance tube; and a plurality of second switch capacitance circuits and second continuous tuning circuits which can be adjusted in a numerical control way are connected in parallel between the grid electrodes of the third differential resonance tube and the fourth differential resonance tube.
The first MOS tube PM1 controls the on and off of the first differential resonance tube and the second differential resonance tube, and the second MOS tube PM2 controls the on and off of the third differential resonance tube and the fourth differential resonance tube. In a specific embodiment, the grid electrode of the PM1 pipe is connected with the grid electrode of the PM2 pipe, the control port is named as PD, and the PD can realize simultaneous switch control on two single-core voltage-controlled oscillators; in addition, the PM3 pipe grid electrode and the PM4 pipe grid electrode are respectively connected with the PM5 pipe grid electrode and the PM6 pipe grid electrode in parallel, and the PM3 pipe drain electrode and the PM4 pipe drain electrode are respectively connected with the PM5 pipe drain electrode and the PM6 pipe drain electrode in parallel. The PM1 pipe and the PM2 pipe respectively supply power to the two single-core voltage-controlled oscillators, and the source electrode of the PM1 pipe and the source electrode of the PM2 pipe are connected with a power supply VCC
The first MOS tube and the second MOS tube are PMOS tubes; the grid electrodes of the first MOS tube and the second MOS tube are connected, and the interconnection node pairs the two voltage-controlled oscillators. The source electrode of the PM1 pipe and the source electrode of the PM2 pipe are connected with a power supply VCC, the grid electrode of the PM1 pipe is connected with the grid electrode of the PM2 pipe, the connection line is named PD, and the drain electrode of the PM1 pipe is connected with the source electrodes of the PM3 pipe and the PM4 pipe and used for supplying power to the PM3 pipe and the PM4 pipe of the resonance pipe; the drain electrode of the PM2 pipe is connected with the source electrodes of the PM5 pipe and the PM6 pipe and is used for supplying power to the PM5 pipe and the PM6 pipe of the resonance pipe.
The voltage-controlled oscillator provided by the invention has two connection methods which apply the common inductance, and the chip area occupied by the circuit in the back-end layout is effectively reduced by adopting the connection method. The method comprises the following steps: the grid electrode of the first differential resonance tube PM3 is connected with the grid electrode of the third differential resonance tube PM5, the connecting wire is TANKB, the grid electrode of the second differential resonance tube PM4 is connected with the grid electrode of the fourth differential resonance tube PM6, the connecting wire is TANKB, the connecting wire TANKA and the connecting wire TANKB are respectively connected with two ends of the differential inductor L1, and the common inductance of resonance ends is realized; the drain electrode of the first differential resonance tube PM3 is connected with the drain electrode of the third differential resonance tube PM5, the connecting wire is OUTP, the drain electrode of the second differential resonance tube PM4 is connected with the drain electrode of the fourth differential resonance tube PM6, the connecting wire is OUTN, and the connecting wire OUTP and the connecting wire OUTN are respectively connected with two ends of the differential inductor L2, so that the common inductor of the output end is realized.
In a specific embodiment, a gate of one resonant tube PM3 in the first single-core voltage-controlled oscillator is connected to one end of the capacitor C2, one end of the first continuous tuning circuit, one end of the four switch capacitors, and one end of the differential inductor L1; the grid electrode of the other resonance tube PM4 is connected with one end of a capacitor C1, the other end of the first continuous tuning circuit, the other ends of the four switch capacitors and the other end of a differential inductor L1; the other end of the capacitor C2 is connected with the drain electrode of the PM4 and one end of the inductor L2; the other end of the capacitor C1 is connected to the drain of the PM3 and the other end of the inductor L2. The PM3 pipe grid electrode and the PM4 pipe grid electrode are respectively connected with the PM5 pipe grid electrode and the PM6 pipe grid electrode in parallel, and the other part is a PM3 pipe drain electrode and a PM4 pipe drain electrode which are respectively connected with the PM5 pipe drain electrode and the PM6 pipe drain electrode in parallel; considering that the layout area is fully utilized, two ends of the grid parallel differential are connected with a continuous tuning circuit and four switch capacitance circuits in a bridging mode.
The grid electrode of the PM3 pipe is connected with one end of a capacitor C2, the connection line is named TANKB, the other end of the capacitor C2 is connected with the drain electrode of the PM4 pipe, and the connection line is named OUTN; the grid electrode of the PM4 pipe is connected with one end of a capacitor C1, the connection line is named TANKA, the other end of the capacitor C1 is connected with the drain electrode of PM3, and the connection line is named OUTP; the grid electrode of the PM5 pipe is connected with one end of a capacitor C4, the connection line is named TANKB, the other end of the capacitor C4 is connected with the drain electrode of the PM6 pipe, and the connection line is named OUTN; the grid electrode of the PM6 tube is connected with one end of a capacitor C3, the connection line is named TANKA, the other end of the capacitor C3 is connected with the drain electrode of the PM5, and the connection line is named OUTP.
A first continuous tuning circuit and four switch capacitors are connected between two connecting lines of TANKA and TANKB of the first single-core voltage-controlled oscillator in a bridging way, wherein the first continuous tuning circuit is composed of capacitors C5 and C6, varactors CV1 and CV2 and resistors R1 and R2 and is used for realizing continuous tuning of frequency; the four switch capacitors are respectively controlled by control signals CS <1>, CS <2>, CS <3> and CS <4>, the capacitance size controlled by CS <1> is C, the capacitance size controlled by CS <2> is C, the capacitance size controlled by CS <3> is 3 x C, and the capacitance size controlled by CS <4> is 5*C.
A second continuous tuning circuit and four switch capacitors are connected between two connecting lines of TANKA and TANKB of the second single-core voltage-controlled oscillator in a bridging way, wherein the second continuous tuning circuit is composed of capacitors C9 and C10, varactors CV5 and CV6 and resistors R5 and R6 and is used for realizing continuous tuning of frequency; the four switch capacitors are respectively controlled by control signals CS <1>, CS <2>, CS <3> and CS <4>, the capacitance size controlled by CS <1> is C, the capacitance size controlled by CS <2> is C, the capacitance size controlled by CS <3> is 3 x C, and the capacitance size controlled by CS <4> is 5*C.
In consideration of effective utilization of chip area, a third continuous tuning circuit and four switch capacitors are connected between TANKA and TANKB of the two single-core voltage-controlled oscillators, wherein the third continuous tuning circuit is composed of capacitors C7 and C8, varactors CV3 and CV4 and resistors R3 and R4 and is used for realizing continuous tuning of frequency; the four switch capacitors are controlled by control signals CS <0>, CS <2>, CS <3>, CS <4>, the capacitance controlled by CS <0> is C, the capacitance controlled by CS <2> is 2 x C, the capacitance controlled by CS <3> is 2 x C, and the capacitance controlled by CS <4> is 6*C.
In summary, the total capacitance controlled by CS <0> is C, the total capacitance controlled by CS <1> is 2×C, the total capacitance controlled by CS <2> is 4×C, the total capacitance controlled by CS <3> is 8×C, and the total capacitance controlled by CS <4> is 16×C.
The connecting wires TANK and TANKB are respectively connected with two ends of the differential inductor L1 to form a resonant cavity; the connecting wires OUTP and OUTN are respectively connected with two ends of the differential inductor L2 to form a load and output.
Referring to fig. 2, for the switched capacitor detailed implementation circuit, the PM11 pipe, the PM12 pipe, the NM1 pipe, and the NM2 pipe are combined with the input terminal control signal CS to implement selection of the capacitor or not. The source electrode of the PM11 pipe is connected with the source electrode of the PM12 pipe by a power supply VCC, the grid electrode of the PM11 pipe is connected with the grid electrode of the NM1 pipe by a CS, the drain electrode of the PM11 pipe is connected with the drain electrode of the NM1 pipe, and the source electrode of the NM1 pipe is connected with the ground at one end of the grid electrode of the PM12 pipe and the NM2 pipe and one end of a resistor R11. The drain electrode of the PM12 tube is connected with one end of the drain electrode of the NM2 tube, the resistor R2_1 and the resistor R2_2, and the source electrode of the NM2 tube is connected with the ground. The other end of the resistor R11 is connected with the grid electrode of the NM0 tube, the R2_1 is connected with the drain electrode of the NM0 tube and one end of the capacitor C0_1, and the R2_2 is connected with the source electrode of the NM0 tube and one end of the capacitor C0_2. The other terminal of the capacitor c0_1 is the connection line TANKA, and the other terminal of the capacitor c0_2 is the connection line TANKB.
Referring to fig. 3, a continuous tuning circuit is provided for implementing continuous frequency tuning of the VCO. The first, second and third continuous tuning circuits according to the present invention have the same structure, and the internal connection relationship will be specifically described with reference to the first continuous tuning circuit. One end of each of the varactors CV1 and CV2 is connected, the connecting wire is called VTUNE, the other end of each of the varactors CV1 is connected with one end of the capacitor C5 and one end of the resistor R1, the other end of each of the varactors CV2 is connected with one end of the capacitor C6 and one end of the resistor R2, the other ends of the resistor R1 and the resistor R2 are grounded, the other end of the capacitor C5 is a connecting wire TANKA, and the other end of the capacitor C6 is a connecting wire TANKB.
Fig. 4 is a diagram showing the effect of phase noise simulation of the oscillating frequency of 3GHz obtained by the voltage controlled oscillator circuit of the present invention, and it can be seen that the phase noise better than-120 dBc/Hz is realized at the frequency offset of 100kHz, and the present invention has very low phase noise characteristics.
The implementation results above show that: the dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator circuit has excellent phase noise performance. Can be applied to a high-performance radio frequency phase-locked loop system.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (4)
1. A dual-core parallel transconductance linearization low-phase noise voltage-controlled oscillator comprises two single-core voltage-controlled oscillators with the same structure; the method is characterized in that: the two single-core voltage-controlled oscillators are connected in parallel;
each single-core voltage-controlled oscillator comprises two differential resonance tubes, a plurality of switch capacitance circuits capable of being adjusted in a numerical control mode and a continuous tuning circuit, and the first single-core voltage-controlled oscillator comprises a first differential resonance tube (PM 3) and a second differential resonance tube (PM 4); the second single-core voltage-controlled oscillator comprises a third and a fourth differential resonance tubes (PM 5 and PM 6);
the grid electrode of any differential resonance tube of the single-core voltage-controlled oscillator is connected to the drain electrode of the other differential resonance tube through a capacitor, meanwhile, the grid electrodes of the second differential resonance tube (PM 4) and the fourth differential resonance tube (PM 6) are connected to the grid electrodes of the first differential resonance tube (PM 3) and the third differential resonance tube (PM 5) through a first differential inductance (L1), and are grounded in a common mode through the first differential inductance (L1); the drain electrode of the fourth differential resonance tube (PM 6) and the drain electrode of the second differential resonance tube (PM 4) are connected with the drain electrode of the first differential resonance tube and the drain electrode of the third differential resonance tube through a second differential inductor (L2);
and two ends of the first differential inductor (L1) are connected with a plurality of third switch capacitor circuits and third continuous tuning circuits which can be adjusted in a numerical control mode in parallel.
2. The dual-core parallel transconductance linearized low-phase noise-controlled oscillator of claim 1, wherein: a first continuous tuning circuit and a plurality of first switch capacitance circuits which can be adjusted in a numerical control way are connected in parallel between the grid electrodes of the first differential resonance tube and the second differential resonance tube; and a plurality of second switch capacitance circuits which can be adjusted in a numerical control way and a second continuous tuning circuit are connected in parallel between the grid electrodes of the third differential resonance tube and the fourth differential resonance tube.
3. The dual-core parallel transconductance linearized low-phase noise-controlled oscillator of claim 1 or 2, characterized in that: the first MOS tube (PM 1) controls the on and off of the first differential resonance tube and the second differential resonance tube, and the second MOS tube (PM 2) controls the on and off of the third differential resonance tube and the fourth differential resonance tube.
4. A dual-core parallel transconductance linearized low-phase noise-controlled oscillator as claimed in claim 3, characterized in that: the first MOS tube and the second MOS tube are PMOS tubes; the grid electrodes of the first MOS tube and the second MOS tube are connected, and the interconnection node is used for simultaneously controlling the switch of the two single-core voltage-controlled oscillators.
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| CN114978042B (en) * | 2022-05-10 | 2023-03-24 | 上海韬润半导体有限公司 | Switched capacitor circuit, voltage controlled oscillator and method of forming a switched capacitor circuit |
| CN117097263B (en) * | 2023-09-01 | 2024-04-26 | 香港中文大学（深圳） | Dual-mode single-core oscillator |
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| WO2013083735A2 (en) * | 2011-12-06 | 2013-06-13 | St-Ericsson Sa | Oscillator having dual topology |
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