CN112002644A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN112002644A
CN112002644A CN202010884251.6A CN202010884251A CN112002644A CN 112002644 A CN112002644 A CN 112002644A CN 202010884251 A CN202010884251 A CN 202010884251A CN 112002644 A CN112002644 A CN 112002644A
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CN
China
Prior art keywords
side wall
semiconductor device
layer
semiconductor substrate
manufacturing
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CN202010884251.6A
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Chinese (zh)
Inventor
梁启超
蔡彬
章晶
黄冠群
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN202010884251.6A priority Critical patent/CN112002644A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method is applied to the technical field of semiconductors. In the preparation method of the semiconductor device provided by the invention, the first side wall with high dielectric constant and the dielectric layer between the grid structure and the conductive contact plug are converted into the second side wall with low dielectric constant and no air, so that the parasitic capacitance between the grid structure and the conductive contact plug on the semiconductor substrate is reduced on the basis of realizing the original structural action, and meanwhile, the second side wall is still arranged on the grid side wall, so that the problem that the grid side wall cannot be protected when the air side wall is used can be avoided, the stability of the grid structure is ensured, and the operation speed and the response time of the semiconductor device are further improved.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
As the integration of semiconductor devices continues to increase and the critical dimensions associated with these devices continue to decrease, it has become a focus of attention on how to reduce the power consumption and increase the operating speed of CMOS devices. Based on this, researchers find that reducing the parasitic capacitance of the device is an effective method for increasing the operation speed of the device, in addition to reducing the energy consumption of the CMOS device by adopting measures such as copper interconnection instead of aluminum interconnection and nickel silicide instead of cobalt silicide.
In order to reduce the parasitic capacitance between the gate structure and the metal plug in the CMOS device, in the prior art, for example, patent nos. CN 102376647 a and CN 102610646 a propose a method of converting silicon nitride or silicon dioxide sidewalls at two sides of the gate structure into air sidewalls, however, the sidewalls at two sides of the gate structure have the function of protecting the gate. Therefore, in the prior art, the sidewall on both sides of the gate structure is changed into the air sidewall to reduce the parasitic capacitance between the gate structure and the metal plug, so that the stability of the gate structure is reduced, and the performance and reliability of the CMOS device are greatly affected.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which is used for reducing parasitic capacitance in a CMOS device and ensuring the stability of a grid structure so as to improve the operation speed and response time of the CMOS device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein a gate structure, a first side wall, a contact etching barrier layer and a dielectric layer are formed on the semiconductor substrate, the first side wall is positioned on the side wall of the gate structure, the contact etching barrier layer covers the gate structure, the first side wall and the surface of the semiconductor substrate, the dielectric layer covers the contact etching barrier layer, and a drain region and a source region which are positioned at two sides of the gate structure are also arranged in the semiconductor substrate;
selectively removing at least part of the contact etching barrier layer covering the surface of the first side wall to form a first opening exposing at least part of the surface of the first side wall;
removing the first side wall along the first opening to form a side wall groove;
forming a second side wall filled in the side wall groove, wherein the dielectric constant of the second side wall is lower than that of the first side wall;
forming at least one source drain contact hole, wherein each source drain contact hole penetrates through the dielectric layer and the contact etching barrier layer and exposes the top surface of the drain region or the top surface of the source region;
and filling a conductive material in each source-drain contact hole to form a source-drain conductive contact plug.
Optionally, the step of forming the dielectric layer on the contact etching barrier layer may include:
depositing a dielectric layer on the surface of the contact etching barrier layer;
and carrying out chemical mechanical planarization on the top of the dielectric layer until the contact etching barrier layer on the top surface of the grid structure is exposed.
Optionally, the first sidewall may be a single-layer sidewall structure or a multi-layer sidewall structure.
Alternatively, the gate structure may include a polysilicon layer and a metal silicide layer sequentially stacked in a direction away from the semiconductor substrate.
Optionally, the material of the second sidewall spacer is the same as the material of the dielectric layer.
Optionally, the value range of the dielectric constant K of the second sidewall spacer may be 1< K < 7.
Optionally, the material of the second sidewall spacer may include silicon dioxide and/or a low-K dielectric with a dielectric constant lower than 4.
Optionally, selectively removing at least a part of the contact etching barrier layer covering the surface of the first side wall by using a dry etching process; and the number of the first and second groups,
and removing the first side wall by adopting a dry etching and wet etching joint process.
Optionally, the material of the first sidewall may include silicon nitride, and the liquid medicine of the wet etching process may include phosphoric acid.
Based on the above-described method for manufacturing a semiconductor device, the present invention also provides a semiconductor device, including:
the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a drain region and a source region which are positioned on two sides of the grid structure are also arranged in the semiconductor substrate;
the second side walls are positioned at two sides of the grid structure;
the dielectric layer is formed on the semiconductor substrate and surrounds the periphery of the side wall;
and each source drain conductive contact plug penetrates through the dielectric layer and is electrically contacted with the top surface of the source region or the top surface of the drain region.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the preparation method of the semiconductor device provided by the invention, the first side wall with high dielectric constant and the dielectric layer between the grid structure and the conductive contact plug are converted into the second side wall with low dielectric constant and no air, so that the parasitic capacitance between the grid structure and the conductive contact plug on the semiconductor substrate is reduced on the basis of realizing the original structural action, and meanwhile, the second side wall is still arranged on the grid side wall, so that the problem that the grid side wall cannot be protected when the air side wall is used can be avoided, the stability of the grid structure is ensured, and the operation speed and the response time of the semiconductor device are further improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to 2f are schematic structural diagrams of a method for manufacturing a semiconductor device in an embodiment of the present invention during a manufacturing process thereof.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 110-a gate structure;
120-a first sidewall; 121-an oxide layer;
122-a nitride layer; 130-contact etch stop layer;
140/140' -dielectric layer; 150-a second sidewall;
160-conductive contact plugs; LDD-low doped source/drain regions;
an S-source region; a D-drain region;
101-a first opening; 102-sidewall trenches.
Detailed Description
As described in the background art, in order to reduce the parasitic capacitance between the gate structure and the metal plug in the CMOS device, a method of converting silicon nitride or silicon dioxide sidewalls at two sides of the gate structure into air sidewalls is proposed in the prior art, however, the sidewalls at two sides of the gate structure have the function of protecting the gate. Therefore, in the prior art, the sidewall on both sides of the gate structure is changed into the air sidewall to reduce the parasitic capacitance between the gate structure and the metal plug, so that the stability of the gate structure is reduced, and the performance and response time of the CMOS device are greatly influenced.
Therefore, the invention provides a preparation method of a semiconductor device, which is used for reducing parasitic capacitance in a CMOS device and ensuring the stability of a grid structure at the same time, thereby improving the operation speed and response time of the CMOS device. For example, referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, the preparation method comprises the following steps:
step S100, providing a semiconductor substrate, wherein a gate structure, a first side wall, a contact etching barrier layer and a dielectric layer are formed on the semiconductor substrate, the first side wall is positioned on the side wall of the gate structure, the contact etching barrier layer covers the gate structure, the first side wall and the surface of the semiconductor substrate, the dielectric layer covers the contact etching barrier layer, and a low-doped source/drain (LDD) region, a drain region and a source region which are positioned at two sides of the gate structure are also arranged in the semiconductor substrate;
step S200, selectively removing at least part of the contact etching barrier layer covering the surface of the first side wall to form a first opening exposing at least part of the surface of the first side wall;
step S300, removing the first side wall along the first opening to form a side wall groove;
step S400, forming a second side wall to be filled in the side wall groove, wherein the dielectric constant of the second side wall is lower than that of the first side wall;
step S500, forming at least one source drain contact hole, wherein each source drain contact hole penetrates through the dielectric layer and the contact etching barrier layer and exposes the top surface of the grid structure or the top surface of the drain region or the top surface of the source region;
and step S600, filling a conductive material in each source/drain contact hole to form a source/drain conductive contact plug.
That is, in the method for manufacturing a semiconductor device provided by the present invention, the first sidewall and the dielectric layer with a high dielectric constant between the gate structure and the conductive contact plug are converted into the second sidewall with a low dielectric constant and not air, so that the parasitic capacitance between the gate structure and the conductive contact plug on the semiconductor substrate is reduced on the basis of realizing the original structural action, and the second sidewall still exists on the gate sidewall, thereby avoiding the problem that the gate sidewall cannot be protected when the air sidewall is used, ensuring the stability of the gate structure, and further improving the operating speed and the response time of the semiconductor device.
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2a to 2f are schematic structural diagrams of a method for manufacturing a semiconductor device in an embodiment of the present invention during a manufacturing process thereof.
In step S100, specifically referring to fig. 2a, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 is used to provide a platform for operation of the subsequent process to generate a CMOS device. The material of the semiconductor substrate 100 is selected from monocrystalline silicon; the semiconductor substrate 100 may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium; the semiconductor substrate 100 may also be other semiconductor materials. An NMOS region and/or a PMOS region (not shown) may be formed on the semiconductor substrate 100, and the NMOS region and the PMOS region may be formed with the same semiconductor structure and isolated by a shallow trench isolation structure. For example, in the embodiment of the present invention, a structure for manufacturing a MOS is mainly used as an example for description. In this embodiment, a gate structure 110, a first sidewall 120, a contact etch stop layer 130, and a dielectric layer 140 are formed on the semiconductor substrate 100, wherein the gate structure 110 includes a polysilicon layer 111 and a metal silicide layer 112 sequentially stacked along a direction away from the semiconductor substrate 100. The first side wall 120 is located on a side wall of the gate structure 110, the contact etching blocking layer 130 covers surfaces of the gate structure 110, the first side wall 120 and the semiconductor substrate 100, the dielectric layer 140 covers the contact etching blocking layer 130, and a drain region D and a source region S located at two sides of the gate structure 110 are further arranged in the semiconductor substrate 100.
In the embodiment of the present invention, the first sidewall 120 may have a single-layer sidewall structure, or may have a multi-layer sidewall structure. For example, in the embodiment of the present invention, the double-layer sidewall structure shown in fig. 2a and fig. 2b may also be a triple-layer sidewall structure of an ONO film layer. For example, in the embodiment of the present invention, each of the double- layer sidewall spacers 120a or 120b may include an oxide layer 121 and a nitride layer 122 stacked in sequence along a direction perpendicular to the sidewall of the gate structure 110, where the oxide layer 121 covers the sidewall of the gate structure 110 and a portion of the surface of the semiconductor substrate 100, and the nitride layer 122 covers the surface of the oxide layer 121, as shown in fig. 2 a. Illustratively, the material of the oxide layer 121 is silicon dioxide, and the material of the nitride layer 122 is silicon nitride.
In addition, in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, a low doped drain/source region LDD may be further disposed in the semiconductor substrate 100 on both sides of the gate structure, wherein the low doped drain/source region LDD may function to prevent a hot electron degradation effect and provide a shallow junction to reduce a short channel effect; alternatively, another structure (not shown) may be provided in the semiconductor substrate 100.
Optionally, an embodiment of the present invention further provides a specific step of forming the dielectric layer 140 on the contact etching blocking layer 130, including:
first, and with particular reference to FIG. 2b, a dielectric layer 140' is deposited on the surface of the contact etch stop layer 130.
Then, the top of the dielectric layer 140' is planarized chemically and mechanically until the contact etch stop layer 130 on the top surface of the gate structure 110 is exposed, thereby forming the dielectric layer 140 as shown in fig. 2 a.
In step S200, referring to fig. 2c specifically, at least a portion of the contact etch stop layer 130 covering the surface of the first sidewall 120 is selectively removed to form a first opening 101 exposing at least a portion of the surface of the first sidewall.
The size of the first opening 101 and the distance between the gate structure and the conductive contact plug may be equal.
In this embodiment, at least a portion of the contact etch stop layer 130 covering the surface of the first sidewall 120 may be selectively removed by a dry etching process, and the first sidewall 120 may be removed by a dry etching and wet etching combination process. For example, the material of the first sidewall spacers 120 may include silicon nitride, and the chemical solution of the wet etching process may include phosphoric acid.
In step S300, referring to fig. 2d specifically, the first sidewall 120 is removed along the first opening 101 to form a sidewall trench 102.
It should be noted that, in the embodiment of the present invention, a process of removing at least a portion of the contact etching blocking layer 130 covering the surface of the first sidewall 120 may be a wet etching process, and may also be a dry etching process, which is not specifically limited in the present invention.
In step S400, referring to fig. 2e specifically, a second sidewall 150 is formed and filled in the sidewall trench 102, and the dielectric constant of the second sidewall 150 is lower than that of the first sidewall 120.
The material of the second sidewall 150 and the material of the dielectric layer 140 may be the same, and for example, the material of the second sidewall 150 and the material of the dielectric layer 140 may be silicon dioxide.
In this embodiment, the value of the dielectric constant K of the second sidewall 150 may be 1< K <7, that is, the dielectric constant of the second sidewall 150 may be any low-K dielectric of dry air that is lower than the dielectric constant of the first sidewall 120 in the prior art and is higher than the dielectric constant of about 1. For example, an ultra-low dielectric constant material porous SICON with a dielectric constant of about 2 may be used. Illustratively, in the embodiment of the present invention, the material of the second sidewall 150 may include silicon dioxide and/or a low-K dielectric with a dielectric constant lower than 4.
In the embodiment of the present invention, the first sidewall 120 with a high dielectric constant, for example, silicon nitride with a dielectric constant of about 7, on both sides of the gate structure 110 is converted into the second sidewall with a low dielectric constant and not being air, for example, silicon dioxide with a dielectric constant of about 4, so that the parasitic capacitance between the gate structure 110 and each source-drain conductive contact plug on the semiconductor substrate 100 is reduced, and the operating speed of the semiconductor device is further increased.
In step S500, referring to fig. 2f specifically, at least one source/drain contact hole (not shown) and at least one gate contact hole (not shown) are formed, where each source/drain contact hole penetrates through the dielectric layer 140 and the contact etching stopper 130, and exposes the top surface of the drain region D or the top surface of the source region S. Each gate contact hole penetrates through the dielectric layer 140 and the contact etch stop layer 130 and exposes the top surface of the gate structure 110. Because the depth of the gate contact hole is different from that of the source drain contact hole, the etching can be realized by successively carrying out photoetching and etching twice.
In step S600, as shown with continued reference to fig. 2f, each of the contact holes is filled with a conductive material to form a conductive contact plug 160. In this embodiment, the conductive material in the contact hole may include a metal material, such as metal tungsten. And forming a conductive contact plug on the top surface of the drain region D or the top surface of the source region S as a source-drain conductive plug, wherein the bottom surface of the conductive contact plug is electrically contacted with the top surface of the drain region D or the top surface of the source region S. The conductive contact plug formed on the top surface of the gate structure 110 is a gate contact plug, and the bottom surface of the conductive contact plug is electrically contacted with the top surface of the gate structure 110.
Based on the above-described forming method, the present embodiment also provides a semiconductor device, including:
the semiconductor device comprises a semiconductor substrate 100, wherein a gate structure 110 is formed on the semiconductor substrate 100, and a drain region D and a source region S which are positioned at two sides of the gate structure 110 are also arranged in the semiconductor substrate 100;
second sidewalls 150 located at two sides of the gate structure 110;
a dielectric layer 140 formed on the semiconductor substrate 100 and surrounding the periphery of the sidewall spacer 150;
and each source-drain conductive contact plug 160 penetrates through the dielectric layer 140 and is electrically contacted with the top surface of the source region S or the top surface of the drain region D.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, the sidewall 120 on both sides of the gate structure 110 is changed from the first sidewall having a high dielectric constant to the second sidewall 150 having a low dielectric constant and not being air, so that the parasitic capacitance between the gate structure 110 and the source-drain conductive contact plug 160 on the semiconductor substrate 100 is reduced, and meanwhile, the second sidewall 150 is still on the gate sidewall, thereby avoiding the problem that the gate sidewall cannot be protected when using an air sidewall, ensuring the stability of the gate structure, and further improving the operation speed and reliability of the semiconductor device.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a gate structure, a first side wall, a contact etching barrier layer and a dielectric layer are formed on the semiconductor substrate, the first side wall is positioned on the side wall of the gate structure, the contact etching barrier layer covers the gate structure, the first side wall and the surface of the semiconductor substrate, the dielectric layer covers the contact etching barrier layer, and a drain region and a source region which are positioned at two sides of the gate structure are also arranged in the semiconductor substrate;
selectively removing at least part of the contact etching barrier layer covering the surface of the first side wall to form a first opening exposing at least part of the surface of the first side wall;
removing the first side wall along the first opening to form a side wall groove;
forming a second side wall filled in the side wall groove, wherein the dielectric constant of the second side wall is lower than that of the first side wall;
forming at least one source drain contact hole, wherein each source drain contact hole penetrates through the dielectric layer and the contact etching barrier layer and exposes the top surface of the drain region or the top surface of the source region;
and filling a conductive material in each source-drain contact hole to form a source-drain conductive contact plug.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the dielectric layer on the contact etch stopper layer comprises:
depositing a dielectric layer on the surface of the contact etching barrier layer;
and carrying out chemical mechanical planarization on the top of the dielectric layer until the contact etching barrier layer on the top surface of the grid structure is exposed.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the first sidewall spacer has a single-layer sidewall spacer structure or a multi-layer sidewall spacer structure.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the gate structure includes a polysilicon layer and a metal silicide layer stacked in this order in a direction away from the semiconductor substrate.
5. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the second sidewall spacer is the same as a material of the dielectric layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein a value of the dielectric constant K of the second sidewall spacer is 1< K < 7.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the second sidewall spacers comprises silicon dioxide and/or a low-K dielectric having a dielectric constant lower than 4.
8. The method for manufacturing a semiconductor device according to claim 1, wherein at least a part of the contact etching stopper layer covering the surface of the first sidewall is selectively removed by a dry etching process; and the number of the first and second groups,
and removing the first side wall by adopting a dry etching and wet etching joint process.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the material of the first sidewall comprises silicon nitride, and a chemical solution of the wet etching process comprises phosphoric acid.
10. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising:
the semiconductor device comprises a semiconductor substrate, a grid structure is formed on the semiconductor substrate, and a drain region and a source region which are positioned on two sides of the grid structure are also arranged in the semiconductor substrate;
the second side walls are positioned at two sides of the grid structure;
the dielectric layer is formed on the semiconductor substrate and surrounds the periphery of the side wall;
and each source drain conductive contact plug penetrates through the dielectric layer and is electrically contacted with the top surface of the source region or the top surface of the drain region.
CN202010884251.6A 2020-08-28 2020-08-28 Semiconductor device and method for manufacturing the same Pending CN112002644A (en)

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Citations (6)

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CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance
CN102142373A (en) * 2010-02-02 2011-08-03 中国科学院微电子研究所 Manufacturing method of semiconductor device
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CN109216451A (en) * 2017-07-03 2019-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance
CN102142373A (en) * 2010-02-02 2011-08-03 中国科学院微电子研究所 Manufacturing method of semiconductor device
US9437694B1 (en) * 2015-04-01 2016-09-06 Stmicroelectronics (Crolles 2) Sas Transistor with a low-k sidewall spacer and method of making same
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